JPS6129019B2 - - Google Patents

Description

[Detailed description of the invention]

This invention uses parallel 10
This relates to a correction circuit for decimal addition and parallel decimal subtraction. In general, a parallel decimal adder using a binary coded decimal code (hereinafter referred to as a BCD code) is an adder that performs 4-bit parallel hexadecimal addition per digit, and the value of the result of the adder's operation is 1.0 per digit. It is composed of a corrector that detects when the value exceeds 6 and performs a correction calculation by adding a value of 6.
A parallel 10 subtracter using a BCD code is a 4-bit parallel hexadecimal subtracter and a compensator that performs a correction operation by subtracting the numerical value 6 when a borrow signal (borrow) to the upper digit occurs as a result of the subtraction. or a corrector that performs correction calculations by adding a numerical value of 10). When a parallel decimal adder/subtractor is configured using a correction method that detects the state of the result of addition or subtraction and then adds or subtracts a specific value, it must be corrected separately from a normal 4-bit parallel adder/subtractor. Requires an adder/subtracter for calculations, making the circuit configuration complicated.
Another problem was the time required for correction calculations. The purpose of the present invention is to configure a correction circuit in a parallel decimal adder/subtracter with a simple logic circuit without using a conventional adder/subtracter for correction calculations, and to perform correction that can perform both addition and subtraction corrections in decimal. The purpose is to provide circuits. According to the present invention, compared to conventional correction circuits, the number of logic elements constituting the circuit can be reduced, and the time required for correction can also be shortened. The decimal correction circuit according to the present invention is a decimal correction circuit that corrects the output of a 4-bit parallel adder/subtracter, and the value of the parallel bit output having a weight of 1-2-4-8 from the parallel hexadecimal adder/subtracter is 10. A logic circuit that determines whether the value is 10 or more in decimal representation or the presence of a hexadecimal carry signal and generates a detection signal, and the signal of the 1 weight digit is the 1 weight output of the hexadecimal adder/subtractor. If the addition correction is instructed by the first control signal connected to the decimal correction circuit, if the detection signal is true, the signal of the weighted digit of 2 is added to and subtracted from the hexadecimal correction circuit. The output of the weight of 2 is obtained by inverting the output of the weight of 2, and the signal of the weight of 4 is obtained by the above 16
It is obtained by detecting the coincidence between the output of the weight 2 of the hexadecimal adder/subtractor and the output of the weight 4, and the signal of the weight digit of 8 is obtained by comparing the output of the weight 2 of the hexadecimal adder/subtractor with the hexadecimal digit. If the detection signal is false, the signals of weights 2, 4, and 8 are obtained from the outputs of weights 2, 4, and 8 of the hexadecimal adder/subtractor, respectively. None, if the subtraction correction is instructed by the second control signal connected to the decimal correction circuit, if the detection signal is true, the signal of the weighted digit of 2 is sent to the hexadecimal adder/subtractor.
The output of the weight of 4 is obtained by inverting the output of the weight of 4, and the signal of the weight of 4 is obtained by the exclusive OR of the output of the weight of 2 and the output of the weight of 4 of the hexadecimal adder/subtractor,
2, 4, and 4 of the above hexadecimal adder/subtractor
If the detection signal is false, the signals of weights 2, 4, and 8 are obtained from the outputs of weights 2, 4, and 8 of the hexadecimal adder/subtractor, respectively. If there is no correction instruction for addition and subtraction by the first and second control signals, the signals of the weighting digits of 2, 4, and 8 are
It is characterized by including a logic circuit that directly obtains the weight outputs of 2, 4, and 8 from the hexadecimal adder/subtractor. Next, the present invention will be explained with reference to FIGS. 1 and 2. FIG. 1 is a block diagram in which a parallel decimal adder/subtractor is constructed using a parallel hexadecimal adder/subtracter and a decimal addition/subtraction correction circuit according to the present invention.Here, a 4-bit single digit will be explained. BCD code inputs X ₁ , X ₂ , X ₄ , X ₈ and Y ₁ , Y ₂ , Y ₄ , Y ₈ each having a weight of 1-2-4-8 are applied to the parallel hexadecimal adder/subtractor 1. Ru. here,
The control signal G1 instructs the adder/subtractor 1 to perform addition or subtraction, and the carry signal (carry or borrow) C _o is input from the lower digits.
Further, the carry signal C _o is a signal generated from the adder/subtractor 1 as a result of parallel hexadecimal operation. Output signals of hexadecimal addition or subtraction performed in adder/subtractor 1 S′ ₁ , S′ ₂ ,
S' ₄ and S' ₈ are the inputs of the decimal addition/subtraction correction circuit 2. Here, the control signal G2 is a signal that determines whether or not the correction circuit 2 performs the addition correction operation, and the control signal G3 is the signal that 2 This is a signal that determines whether or not to perform a subtraction correction operation. Corrected calculation output signal
S ₁ , S ₂ , S ₄ , and S ₈ are corrected and output as BCD codes with weights of 1-2-4-8, respectively, and the carry signal C′ _o+1 to the upper digit is obtained by correction circuit 2. . Here, when performing addition and subtraction of binary coded decimal numbers, the output of hexadecimal adder/subtractor 1 is input to correction circuit 2
C′ _o , S′ ₈ , S′ ₄ , S′ ₂ , and S′ ₁ are expressed as binary numbers in the case of addition, and from 00000 to 10011 in the case of subtraction.
There are 20 possible combinations from 00000 to 01001 and from 10110 to 11111. These outputs are input to the correction circuit 2 and subjected to decimal correction, and the results obtained are divided into addition and subtraction.
Shown in the table. The parts marked with an x in Table 1 are parts that have no possibility of occurring in BCD code operations. Add the output of the hexadecimal adder/subtractor shown in Table 1

[Table] Alternatively, the operation of converting into a BCD code according to subtraction can be done by replacing it with a simple logic gate circuit that uniquely performs code conversion without adding or subtracting a specific numerical value as in the past. Similar decimal correction operations can be performed. The method of configuring the logic gate circuit will be explained below separately for addition correction and subtraction correction with reference to FIG. (b) In the case of addition correction If the decimal carry signal in the case of addition is C′ _o+1 , C′ _o+1 indicates whether the code represented by S′ ₁ to S′ ₈ is 10 or more, or 16 This occurs when the decimal carry signal C' _o is generated, so its logical formula is expressed as C' _o+1 = C' _o + S' ₈ (S' ₄ + S' ₂ )...(1). Since the output S ₁ after decimal correction having a weight of "1" does not require any correction, it is expressed as S ₁ =S' ₁ ......(2). The output S ₂ after decimal correction with a weight of "2" remains S' 2 as is when the hexadecimal operation result is 0 to 9, and is the _{logically inverted version of S' 2 otherwise} , so S ₂ = S ′ ₂・′ _o+1 +′ ₂・C _o+1 ...(3) The output S ₄ after decimal correction with a weight of “4” is equal to S′ ₄ when the decimal carry signal C′ _o+1 is 〓, and when C′ _o+1 is 1, S′ ₄ and S ′ ₂ , so it is expressed as S ₄ =C′ _o+1 (S′ ₄・S′ ₂ +′ ₄・′ ₂ ) +′ _o+1・S′ ₄ ………(4) It can be done. The output S ₈ after decimal correction with a weight of “8” is
When C′ _o+1 is 〓, it is equal to S′ ₈ , otherwise it is C′ _o
It is expressed as the logical product of S′ ₂ , but in the latter case,
This holds true regardless of C′ _o+1 , so it can be expressed as S ₈ =′ _o+1・S′ ₈ +C′ _o・S′ ₂ ……(5). (b) For subtraction correction Decimal carry signal (borrow signal) for subtraction
Let C′ _o+1 be C′ _o+1 and the output S ₁ with a weight of “1” does not require any correction, so it is expressed as C′ _o+1 = C′ _o S ₁ = S′ ₁ . For output S ₂ with weight “2”, C′ _{o+1
It is} sufficient _to find _{the exclusive OR} of The output S ₄ with a weight of "4" is equal to _the S' ₄ output when C' _{o+1 is 4} = C′ _o+1 (S′ ₄・′ ₂ +′ ₄・S′ ₂ ) +′ _o+1・S′ ₄ ………(9). The output S ₈ with a weight of "8" is equal to S' ₈ when C' _o+1 is 〓.Otherwise, it is enough to calculate the logical product of each output of S' ₂ , S' ₄ , and S' ₈ . S ₈ =′ _o+1・S′ ₈ +S′ ₈・S′ ₄・S′ ₂ ……(10) In order to configure the correction circuit 2 in FIG. 1 according to the above logical formulas (1) to (10), the control signals G2, G2 in FIG.
The final logical formula can be obtained by incorporating G3.
Table 2 shows the operation of the correction circuit for the combined input of G2 and G3.

[Table] Combining signals G2 and G3 with logical formulas (1) and (6), the final decimal carry signal C _o+1 is C _o+1 = C′ _o + G2・S′ ₈ (S′ ₄ +S′ ₂ ) ...(11). The reason why there is no term regarding the signal G3 in the logical formula (11) is that C′ _o+1 during subtraction is all included in C′ _o . Regarding the output _S1 , the following formula holds true regardless of addition or subtraction. S ₁ = S' ₁ ......(12) For the output S ₂ , the signal G2,
Relating G3, S ₂ = 2・3・S′ ₂ + (G2+G3) (C′ _o+1・′ ₂ +′ _o+1・S′ ₂ ) = S′ ₂ (2・3+′ _o+1 ) +′ ₂・C′ _o+1・(G2+G3) ………(13) The output S ₄ is calculated by relating the signals G2 and G3 to the above equations (4) and (9) as follows: S ₄ = S′ ₄ (2・3+′ _o+1 )+G2・C′ _o+1 (′ ₄ ′ ₂ +S′ ₄・′ ₂ ) +G3・C′ _o+1 (′ ₄・S′ ₂ +S′ ₄・′ ₂ ) ……(14) Similarly, in the case of output S ₈ , from equations (5) and (10) above, S ₈ = 2・3・S′ ₈ +G2 (′ _o+1・S′ ₈ +C′ _o・S′ ₂ ) + G3・S′ ₈ (′ _o+1 +S′ ₄・S′ ₂ ) =S′ ₈ (2・3+′ _o+1 )+G2・C′ _o・S′ ₂ +G3・S′ ₈・S′ ₄・S′ Represented by ₂ . Next, an example of a specific configuration of the above correction circuit will be shown with reference to FIG. In Figure 2, S' ₁ , S' ₂ , S' ₄ , S' ₈ , C' _o , G
2, G3, S ₁ , S ₂ , S ₄ , S ₈ , and Co ₊₁ have the same meanings as the symbols in FIG. OR gate 3 and AND gate 4 detect that the output of the hexadecimal adder/subtractor is 10 or more, and
The OR gate 5 generates a carry signal C′ _o+1 common to addition and subtraction corrections. AND gate 6 generates control signals G2, _C'o+1 when executing addition correction by ANDing the carry signal C'o ₊ 1 and addition correction instruction control signal G2.
The AND gate 7 generates a control signal G3·C′ _o+1 when executing subtraction. Furthermore _{, the} NOR gate ₈ outputs _a control signal (2+
G3) Generate C′ _o+1 . The S ₁ output with a weight of “1” is calculated by the above equation (12).
Directly connected to S′ ₁ . The S ₂ output, which has a weight of "2", is inverted by the NOR gate 9 during addition and subtraction correction according to equation (13 ₎ above, and when no correction is necessary, the AND gate 10 outputs S' ₂ as it is. The above two signals are then synthesized by an OR gate 11. The S4 output with a weight of " ₄ " is obtained by the AND gate 14 as the output from the exclusive OR gate 12 of S' ₂ and S' ₄ during subtraction correction according to the above equation (14), and the output from the above 12 during addition correction. is inverted by the inverter gate 13 (coincidence signal output of S' ₂ and S' ₄ ) is obtained by the AND gate 15, and when no correction is required, the AND gate 16 outputs S' ₄ as it is, and the above three types are output. It is obtained by combining the symbols using an OR gate 17. The _S8 output with a weight of "8" is obtained by using the AND gate 18 to obtain the logical product of S' ₂ , S' ₄ , and S' ₈ at the time of subtraction correction using the above equation (15), and is calculated from C' _o at the time of addition correction. The logical product of S' ₂ is obtained by the AND gate 19, and when no correction is required, the AND gate 20 outputs S' ₈ as it is, and the above three types of signals are synthesized by the OR gate 21. The carry signal C _o+1 after correction is 16 according to the above equation (11).
It is obtained by combining the advance carry signal C _o and G2·C' _o+1 at the OR gate 22. Formulas (11) to (15) are expressed by the functions of each logic gate above.
The logic of the equation is satisfied, and the parallel decimal addition and subtraction correction operations shown in Table 1 as well as the parallel hexadecimal addition and subtraction operations that do not require correction can be realized with a simple logic circuit, and the time required for correction is also the worst. However, the transmission delay time of several stages of logic gates is sufficient.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a schematic configuration of a parallel decimal adder/subtractor for adding and subtracting one digit BCD code according to the present invention, and FIG. 2 is a block diagram showing an example of a decimal correction circuit according to the present invention. In the figure, 1...parallel hexadecimal adder/subtractor, 2
...This is a decimal correction circuit.

Claims (1)

[Claims] 1. In a decimal correction circuit that corrects the output of a 4-bit parallel adder/subtracter, the value of the parallel 4-bit output from the adder/subtracter is 10 or more in decimal representation, or
a logic circuit that determines the presence of a hexadecimal carry signal and generates a detection signal, the output of a digit having a weight of 1 is obtained by the output of a weight of 1 of the adder/subtractor; When addition correction is instructed by the first control signal, if the detection signal is true, the output of the weight of 2 is obtained by inverting the output of the weight of 2 of the adder/subtractor; A signal with a weight of 8 is obtained by negating the exclusive OR of the output with a weight of 2 and the output with a weight of 4 of the adder/subtractor.
If the detection signal is false, 2, 4, 8
The weight digit signals of the hexadecimal adder/subtractor 2, 4,
8 weights, respectively, and the 10
When the subtractive correction is instructed to the leading correction circuit by the second control signal, if the detection signal is true, 2
A signal with a weight of 2 is obtained by inverting the output of a weight of 2 of the adder/subtractor, and a signal with a weight of 4 is obtained by exclusive of the output of a weight of 2 and the output of a weight of 4 of the adder/subtractor. A signal with a weight of 8 is obtained by a logical AND of the outputs of weights 2, 4, and 8 from the adder/subtractor, and if the detection signal is false, the Signals with a weight of 8 are obtained from the outputs of weights 2, 4, and 8 of the adder/subtracter, respectively, and when there is no correction instruction for addition and subtraction by the first and second control signals, 2, A decimal correction circuit comprising a logic circuit configured to directly obtain signals of weights of 4 and 8 from outputs of weights of 2, 4, and 8 of the hexadecimal adder/subtractor.