JPS6128854A - Capacity variation detecting circuit - Google Patents

Abstract

PURPOSE:To detect the variation of capacity easily as digital numeral, by arranging a detection circuit comprising a capacity switch type oscillator having a switching circuit, a binary counter, a reference oscillator and increment/decrement counter. CONSTITUTION:A capacity variation detecting circuit is made up of a capacity switch type oscillator 4 comprising a switching circuit 11, a binary counter 12 for counting an output pulse CP of the oscillator 4, a reference oscillator 13 for generating a reference pulse XP and an increment/decrement counter 14 for counting the reference pulse XP with the counting direction controlled by a switching signal. Then, counting actions of the counters 12 and 14 are started simultaneously while changes in the capacity are detected as digital numeral from the results of counting of the counter 14 by the output of the counter 12 at the interval of (n+1) bits.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to the field of measurement in which a measured quantity is detected as a change in capacitance. This invention relates to a change detection circuit.

(b) Conventional technology On page 32 of the Cosmetic Society Journal VOL, s, l' 2 (19s1), a conventional technology of a capacitance change circuit in an FVC type moisture meter is disclosed. As shown in Figure 2, this circuit connects the capacitor to be measured Cx in parallel to the zero point setting capacitor C1 of the CR oscillator (1), and sets the oscillation frequency of the CR oscillator (1) by F V C (2). This voltage is converted into a voltage, and this voltage is smoothed by an integrating circuit (3), and the capacitance difference between the capacitance to be measured Cx and the zero point setting capacitor CI is detected as a voltage difference Δ■.

E→ Problem to be Solved by the Invention In the conventional technology, frequency changes based on capacitance changes are converted into voltage, which is an analog quantity. It is necessary to connect an AD converter after step 3), which has the disadvantage of complicating the circuit configuration. Furthermore, since it is necessary to convert the analog voltage into a digital value, it is difficult to obtain a desired value for the amount of change in capacitance, and furthermore, the setting process becomes troublesome.

B) Means for Solving the Problems The present invention provides a capacitor switching type oscillator including a switching circuit that switches and connects either a zero point setting capacitor or a capacitor to be measured as a component of the oscillator, and an output of this oscillator. A binary counter that counts pulses and uses the Rubinto's output as a switching signal for the switching circuit, a reference oscillator that outputs a reference pulse, an up/down counter whose counting direction is controlled by the switching signal and counts the reference pulse, and a capacitance change. A detection circuit is configured to simultaneously start counting operations of a binary counter and an up/down counter, and
The counting operation of the up/down counter is stopped by the output of the (yb-1-1)th bit of the binary counter.

(E) Effect In the present invention, either the zero point setting capacitor or the capacitor under test is connected as a component of the oscillator. Generates a pulse and converts this output pulse into a binary
During the period Tx during which the counter counts 21 pulses, the up/down counter counts up or down the reference pulse. When the rubit-th output of the binary counter occurs, the capacitance of the capacitance switching type oscillator is switched, and furthermore, the counting direction of the up/down counter is reversed.
A period T during which the binary counter similarly counts 2'' output pulses with a frequency corresponding to the zero point setting capacitance. Therefore, the difference in the number of pulses counted from the reference pulse between period Tx and period T. remains in the up/down counter as a count result.Here, period T and T.
This period is proportional to the l capacitance and the zero point setting capacitance, and therefore, the amount of change in capacitance is detected as a digital value from the count result of the up/down counter.

(f) Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention.
) are inverters (5) (6), resistors (power, zero point setting capacitor C8, measured capacitor CI, measured capacitor Cx, and two transmissive gates (8) that switch and connect the zero point setting capacitor C6. (9) and a switching circuit 0υ consisting of an inverter ([O)].
α is a binary counter that counts the output pulse CP of the capacitance switching type oscillator (4), α is a reference oscillator that generates the reference pulse XP, α4 is three decimal up/down counters (14a) (14b) (14c) ) consists of an up/down counter that counts the reference pulse XP, (
15a) (15b) is a display launch circuit that latches the count results of the first and second decimal up-down counters (14a) and (14b), respectively; (10 is a latch circuit for image display (15a); The display (a'?) that digitally displays the contents of 15b) is an R87 lip-flop that uses the start command ST as a reset signal and the binary counter (the output Q+1 of the (rL 1)th bit as a set signal. The Q output of this flip-flop is input to each reset terminal of the binary counter α2 and the decimal up/down counters (14a) (14b) (14c), and is also input to the display latch circuit (15).
a) Supplied as a latch signal of (15b).

Further, the binary counter (12+ rubbit-th output Q and the signal Q inverted by the inverter are respectively transmitted through the transmission gates (8) and (9) of the switching circuit 0υ.
) as a switching signal, and the decimal up/down counters (14a) (14b) (14c)
In this case, as a control signal that controls the counting direction,
It is applied to the up/down terminal U/D.

Next, the operation of this embodiment will be explained with reference to the timing chart of FIG.

First, when the start command ST reaches rHJ, the RS flip-flop (lη) is reset and its Q output becomes rLJ.
Therefore, the binary counter (12+) and the up/down counter (1) are reset and start counting at the same time. At this time, the output Q of the binary counter (121) is as shown in FIG. (As shown in →, it is 5KrLJ, so Transmission Game) (8
) is turned on and 9) is turned off, and the counting direction of the up/down counter 04) is controlled in the up direction. Therefore, the capacitance to be measured Cx is connected as a component, and the capacitance switching type oscillator (4) generates an output pulse CP with a frequency fax according to the capacitance to be measured* and CX (
Figure 3 (a)). The switching of the switching circuit (11) is the output Q%
is not performed between II and I, so the binary counter circle counts 2" output pulses CP of frequency fCX. During this period, up-down counter 04) counts the reference pulse. XP (Figure 3 ((e))
count up (Fig. 3). In FIG. 3, B-CTR and D-CTR indicate the contents of the binary counter σ and the up/down counter 04), respectively.

Then, when the rubit-th output Q of the binary counter circle becomes rHJ, the transminscene gate (8
) turns off and 9) turns on, so the capacitance switching type oscillator (
In 4), the capacity is switched, and this time the zero point setting capacity co
An output pulse CP with a frequency fco corresponding to the frequency fco is generated. At this time, the counting direction of the up/down counter α is switched from up to down. Therefore, the binary counter C1 counts 2'' output pulses CP of the frequency fco as in the case of the output pulse of the frequency fcz, and during this period T, the up/down counter (
14) counts down the reference pulse XP by eight. Then, when the output Q, + of the (a+1)th bit of the binary counter (12+) becomes rHJ, the RS slip-flop output is set, and the Q output causes each of the binary counter α2 and the up/down counter α Advance up/down counter + (:1:4a) (14b)
(14c) is reset, the counting operations of both counters are stopped, and the count results of the up/down counters are latched in the latch circuits (15a) and (15b). That is, the up/down counter α contains the number A of reference pulses XP counted during the period Tx and the period T. The number of pulses (person-B) that is the difference between the number B of reference pulses XP counted during this period is obtained as a count result, and this value is stored in the latch circuit (15g) (15b).

Here, the period T, and T. are the respective capacitances Cx and c.

This is a period in which the same number of frequencies fCX and feo, which are proportional to
The period is proportional to 9. Therefore, the capacitance to be measured Cx
The difference between the zero point setting capacitor C8 and the answer is obtained as a digital value from the up/down counter C[4]. By appropriately selecting the relationship between the oscillation frequency of the capacitance switching type oscillator (4) and the frequency of the reference pulse, for example, a desired value suitable for percentage display can be set on the up/down counter 0.
This can be obtained as a count result of a.

Therefore, as shown in this embodiment, the latch circuit (15a)
(15b) and decimal up/down counter (14a)
By latching the contents of (14b) and supplying them to the display α6), the desired digital numerical value indicating the capacitance change can be displayed on the display (10).

In order to reliably latch the contents of the up/down counter α→, a delay circuit (2) is provided to delay the Q output of the R87 lip µtub αη, as shown by the broken line in FIG. Up/down counter α (a) at output
All you have to do is reset it.

In the above explanation, the up/down counter α(a)
The counting operation was stopped by resetting with the Q output of the RS flip-flop αη or its delayed output, but for example, the O
By providing an R gate and inputting the output of this OR gate to the up/down counter aa, the counting operation may be stopped. The up/down counter αa may be reset using the following method.

(G) Effects of the Invention According to the present invention, since the change in capacitance can be obtained as a digital value from the count result of the counter, it becomes easy to display the measured quantity numerically. In addition, since the configuration uses a counter to count the frequency change based on the capacitance change and converts it into a digital value, the circuit configuration is simplified, and a desired value such as % of the capacitance change can be calculated by changing the frequency of the reference pulse. It has the advantage that it can be easily obtained by

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a block diagram showing a conventional capacitance change detection circuit, and Fig. 3 is a block diagram showing an embodiment of the present invention.
5 is a timing chart for explaining the operation of the illustrated embodiment. Explanation of main figure numbers (4)...Capacitance switching oscillator, 0υ...Switching circuit, Circle...Binary counter, a□□□...Reference oscillator, α4)...Up/down counter , (1υ・
··display.

Claims (1)

[Claims] (1) A capacitor switching type oscillator equipped with a switching circuit that switches and connects either the zero point setting capacitor or the capacitor under test as a component of the oscillator, and the output pulse of the oscillator is counted and the nth bit (n: integer ); a reference oscillator that outputs a reference pulse; and an up/down counter whose counting direction is controlled by the switching signal and counts the reference pulse; While simultaneously starting the counting operations of the counter and up/down counter,
A capacitance change characterized in that the counting operation of the up/down counter is stopped by the output of the (n+1)th bit of the binary counter, and the change in capacitance is detected as a digital value from the count result of the up/down counter. detection circuit.