JPS61288474A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS61288474A
JPS61288474A JP60129966A JP12996685A JPS61288474A JP S61288474 A JPS61288474 A JP S61288474A JP 60129966 A JP60129966 A JP 60129966A JP 12996685 A JP12996685 A JP 12996685A JP S61288474 A JPS61288474 A JP S61288474A
Authority
JP
Japan
Prior art keywords
type
semiconductor
doped
electrodes
photovoltaic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60129966A
Other languages
Japanese (ja)
Other versions
JPH0728046B2 (en
Inventor
Makoto Hirano
真 平野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP60129966A priority Critical patent/JPH0728046B2/en
Publication of JPS61288474A publication Critical patent/JPS61288474A/en
Publication of JPH0728046B2 publication Critical patent/JPH0728046B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
    • H01L31/101Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier
    • H01L31/109Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PN heterojunction type

Abstract

PURPOSE:To prevent the characteristics from deteriorating due to the running of carriers in the impurity-doped semiconductor, by providing with non-doped semiconductor having a small energy gap between the P-N junction. CONSTITUTION:In a case where non-doped GaAs 30 is put between P-doped Al0.5Ga0.5As 29 and N-doped Al0.5Ga0.5As 31, two-dimensional hole gas 40 is produced on the hetero interface between the GaAs 30 and the P<-> Al0.5Ga0.5As 29, and two-dimensional electron gas 39 on the hetero interface between the GaAs 30 and the N<-> Al0.5Ga0.5As. In the non-doped GaAs 42, the potential gradient is created, and thus extremely large internal electrical field may be generated. Accordingly, when electrons 37 and holes 38 are created by light irradiation 44 in the non-doped GaAs layer 42, each carrier flows into the hetero interfaces at an almost saturated speed by the large internal electrical field.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は製造が容易で、かつ高性能な光電池。[Detailed description of the invention] (Industrial application field) The present invention provides a photovoltaic cell that is easy to manufacture and has high performance.

光検出器、N形およびP形電界効果トランジスタ、フォ
トトランジスタおよびこれらの組み合わせによる無バイ
アスの光検出器、無バイアスのフォトトランジスタ、コ
ンプリメンタリ−回路、光電子回路等の半導体装置に関
するものである。
The present invention relates to semiconductor devices such as photodetectors, N-type and P-type field effect transistors, phototransistors, non-bias photodetectors using combinations thereof, non-bias phototransistors, complementary circuits, and optoelectronic circuits.

(発明の概要) 本発明は、基板上に形成されたPN接合を用いた光起電
力半導体装置において、前記のPN接合間に、P形およ
びN形半導体のいずれよりも、バンドエネルギーギャッ
プが小で、かつノンドープないし、低ドープの第3半導
体層を配設し、前記の第3半導体層に対して、P形オー
ミックコンタクトと、N形オーミックコンタクトを夫々
形成して、光起電力装置を構成することにより、光励起
キャリヤーに働く内部電界が大きく、かつ2次元電子ガ
ス拳2次元ホールガスの利用によりネ細物散乱・再結合
による特性劣化の少ない、かつ制作が容易なプレーナ形
で受光面積も大きくできる高性能の光起電力装置を提供
するにある。
(Summary of the Invention) The present invention provides a photovoltaic semiconductor device using a PN junction formed on a substrate, in which a band energy gap between the PN junctions is smaller than that of both P-type and N-type semiconductors. and a non-doped or lightly doped third semiconductor layer is provided, and a P-type ohmic contact and an N-type ohmic contact are respectively formed with respect to the third semiconductor layer to configure a photovoltaic device. By doing so, the internal electric field acting on the photoexcited carrier is large, and by using a two-dimensional electron gas or two-dimensional hole gas, there is less characteristic deterioration due to scattering and recombination of fine objects, and the planar shape is easy to manufacture and has a large light-receiving area. The purpose of the present invention is to provide a high-performance photovoltaic device that can be expanded.

本発明は、基板上に形成された光起電力半導体装置にお
いて、前記のPN接合間に、P形およびN形半導体のい
ずれよりも、バンドエネルギーギャップが小で、かつノ
ンドープないし、低ドープの第3半導体層を配設し、前
記の第3半導体層に対して、2個のN形オーミック電極
を形成し、前記の電極間にバイアス電圧を与えて光電流
検出装置を構成することにより1光励起キャリヤーに働
く内部電界が大きく、かつ2次元電子ガス・2次元ホー
ルガスの利用にょシネ細物散乱・再結合による特性劣化
の少ない、かつ制作が容易なプレーナ形で受光面積も大
きくできる高性能の光電流検出装置を提供するにある。
The present invention provides a photovoltaic semiconductor device formed on a substrate, in which a non-doped or lightly doped semiconductor having a smaller band energy gap than both P-type and N-type semiconductors is provided between the PN junctions. 3 semiconductor layers are arranged, two N-type ohmic electrodes are formed on the third semiconductor layer, and a bias voltage is applied between the electrodes to configure a photocurrent detection device. It has a large internal electric field acting on the carrier, uses two-dimensional electron gas and two-dimensional hole gas, has little characteristic deterioration due to fine object scattering and recombination, and is easy to manufacture in a planar shape that allows for a large light-receiving area. The present invention provides a photocurrent detection device.

本発明は、基板上に形成された光起電力半導体装置にお
いて、前記のPN接合間に、P形およびN形半導体のい
ずれよりも、バンドエネルギーギャップが小で、かつノ
ンドープないし、低ドープの第3半導体層を配設し、前
記の第3半導体層に対して、2個のN形オーミック電極
を形成し、前記の電極間にバイアス電圧を与えて光電流
検出装置を構成し、また同一結晶の他の領域で前記の第
3半導体層に対してP形およびN形オーミック電極を形
成して、光起電力装置を構成し、前記の光起電力装置を
、前記の光電流検出装置のバイアス電源として用い、無
バイアス光電流検出装置全構成することにより、光励起
キャリヤーに働く内部電界が大きく、かつ2次元電子ガ
ス・2次元ホールガスの利−用により不純物散乱φ再結
合による特性劣化の少ない、かつ制作が容易なプレーナ
形で受光面積も大きくできる高性能で、さらに同一結晶
上に制作が容易なプレーナ形で集積化LY構成可能な光
起電力装置を提供するにある。
The present invention provides a photovoltaic semiconductor device formed on a substrate, in which a non-doped or lightly doped semiconductor having a smaller band energy gap than both P-type and N-type semiconductors is provided between the PN junctions. 3 semiconductor layers are arranged, two N-type ohmic electrodes are formed on the third semiconductor layer, a bias voltage is applied between the electrodes to constitute a photocurrent detection device, and the same crystal P-type and N-type ohmic electrodes are formed on the third semiconductor layer in other regions to configure a photovoltaic device, and the photovoltaic device is connected to the bias of the photocurrent detection device. By using it as a power source and fully configuring the non-bias photocurrent detection device, the internal electric field acting on the photoexcited carrier is large, and by using two-dimensional electron gas and two-dimensional hole gas, there is little characteristic deterioration due to impurity scattering φ recombination. It is an object of the present invention to provide a photovoltaic device which has a planar shape that is easy to manufacture, has a high performance with a large light-receiving area, and can be configured as an integrated LY in a planar shape that is easy to manufacture on the same crystal.

(従来技術及び発明尻解決しようとする問題点〕(a)
PN接合を利用した光起電力半導体装置としては、第1
1図に示すように従来、P形半導体工。
(Prior art and problems to be solved by the invention) (a)
The first photovoltaic semiconductor device using a PN junction
As shown in Figure 1, conventional P-type semiconductor processing.

N形半導体2の各々に直接コンタクト電極4゜5を設け
た素子が提供されていた。(参考文献:J、 R,Da
vis et al : Conf、 Rec、 7 
th PhotovoltaSpec、 Conf、 
(9618) p、 85 )しかし、この素子では起
電力はP形半導体1とN形半導体2との間に生じるため
、図中4゛。
A device was provided in which each of the N-type semiconductors 2 was provided with a direct contact electrode 4.5. (Reference: J, R, Da
vis et al: Conf, Rec, 7
th PhotovoltaSpec, Conf,
(9618) p, 85) However, in this element, the electromotive force is generated between the P-type semiconductor 1 and the N-type semiconductor 2, so it is 4゛ in the figure.

5のように本質的にコンタクト電極はPN接合面3に対
して各々反対側につけなければならず、高性能化のため
受光面を大きくするのに不利であった。
5, the contact electrodes essentially had to be placed on opposite sides of the PN junction surface 3, which was disadvantageous in increasing the light receiving surface for higher performance.

また、光照射によって生じた電子・ホール等のキャリヤ
ーは、第12図に示した原理図のようにPN接合面と垂
直方向に不純物結晶中金拡散によって伝導せねばならず
、直列抵抗が大きくまたキャリヤーの再結合等による消
失も大きく光−起電力変換効率を上げるのに困難さがあ
った。図中6は励起光、7は光励起電子、8は光励起ホ
ール、9はN形半導体、10はP形半導体を示す。
In addition, carriers such as electrons and holes generated by light irradiation must be conducted by gold diffusion in the impurity crystal in the direction perpendicular to the PN junction surface, as shown in the principle diagram shown in Figure 12, and the series resistance is large and There is also a large loss of carriers due to recombination, etc., making it difficult to increase the photo-electromotive force conversion efficiency. In the figure, 6 indicates excitation light, 7 indicates photoexcited electrons, 8 indicates photoexcited holes, 9 indicates an N-type semiconductor, and 10 indicates a P-type semiconductor.

(b)また、光導電効果を利用した光電流検出装置  
−としては、第13図に示したように、従来、単に半導
体nに2個のN形オーミック電極13.14をi 形成
し励起光11による励起電流を検出するものがあった。
(b) Also, a photocurrent detection device using the photoconductive effect
Conventionally, as shown in FIG. 13, two N-type ohmic electrodes 13 and 14 are simply formed on a semiconductor n to detect the excitation current generated by the excitation light 11.

(参考文献: R,H,Bube et al、  :
Ph)rs、 Rev、 128 (1962) 53
2 )この場合、半導体中を流れる光電流は、半導体中
の不純物による電子の散乱の次め小さくなるという欠点
があった。
(References: R, H, Bube et al.:
Ph)rs, Rev, 128 (1962) 53
2) In this case, there was a drawback that the photocurrent flowing through the semiconductor was smaller than the scattering of electrons due to impurities in the semiconductor.

(c)一方、光検出用のバイアス電圧を外部から印加す
る必要のない無バイアス光検出器としては、従来第14
図に原理的を示すように、励起光15によって生じた電
子16ヲ結晶の内部電界によって集め、このペテロ界面
にチャネルと基板間の起電力をバイアス電圧として利用
したものがあった。図中17は光励起ホール、18はN
−A九aAa側、19はノンドープ(P−9N−) G
aAa側、加はヘテロ界面、21は2次元電子ガスを示
す。(参考文献:C,Y、 Chen et al :
 Appl、 Phys、 Lett、 41(3) 
p282これは、第15図に示すように基板側に電極を
とらねばならないという素子形成上の欠点のため、工程
が複雑となシ、かつ同一結晶膜上に、他の素子と一緒に
平面構成することが困難であった。
(c) On the other hand, as a non-bias photodetector that does not require external application of a bias voltage for photodetection,
As the principle is shown in the figure, there is a system in which electrons 16 generated by excitation light 15 are collected by the internal electric field of the crystal, and the electromotive force between the channel and the substrate at this Peter interface is used as a bias voltage. In the figure, 17 is a photoexcitation hole, 18 is N
-A9aAa side, 19 is non-doped (P-9N-) G
On the aAa side, KA indicates a hetero interface, and 21 indicates a two-dimensional electron gas. (References: C, Y, Chen et al:
Appl, Phys, Lett, 41(3)
p282 This is because, as shown in Fig. 15, the process is complicated due to the drawback of having to provide electrodes on the substrate side, and the planar configuration is difficult because the electrodes must be placed on the substrate side as shown in Figure 15. It was difficult to do so.

また従来の一般の半導体による光電池、光検出器、フォ
トトランジスタ、電子回路等は、各各必要とする結晶層
構造、電極設置法かまちまちであったため、同一結晶基
板上に1ブレーナ形に組み合わせ構成するのは困難とい
う欠点があった。
In addition, conventional general semiconductor photocells, photodetectors, phototransistors, electronic circuits, etc. required different crystal layer structures and electrode installation methods, so they were combined into one brainer type on the same crystal substrate. The drawback was that it was difficult to do.

(d) tた、半導体ヘテロ界面に生じたN形およびP
形のキャリヤーを用いる両種トランジスタ(参考文献:
 T、 Mimura et al : Jpn、 J
、 Appl、 Phya。
(d) N type and P type generated at the semiconductor hetero interface
Both types of transistors using carriers of the form (References:
T, Mimura et al: Jpn, J
, Appl, Phya.

20(1981) p 598 、  H,L、 St
omer et al : Appl。
20 (1981) p 598, H, L, St.
omer et al: Appl.

Ph1s、 Latt、 44(lυ1. (1984
) p1062 )による°コンプリメンタリー回路の
構成法さしては、従来の個々のデバイスから容易に類推
できる方法としては、第16図に示すように、個々のデ
バイスを多層に積み重ねるものが考えられるが、これは
結晶成長上は上層結晶の結晶品質の劣化という欠点、プ
ロセス上は非プレーナ形で工程が複雑になシ、段差によ
る配線切れなど多くの欠点があつ友。なお、図中85は
基板、86はP −AtGaAa、87はノンドープ(
p−、N−) GaAa、88はN−AtGaAa 。
Ph1s, Latt, 44(lυ1. (1984
) Complementary circuit construction method according to p. 1062) A method that can be easily inferred from conventional individual devices is to stack individual devices in multiple layers as shown in Figure 16, but this It has many disadvantages in terms of crystal growth, such as deterioration of the crystal quality of the upper layer crystal, complexity in the process due to its non-planar shape, and breakage of wiring due to steps. In the figure, 85 is a substrate, 86 is P-AtGaAa, and 87 is a non-doped (
p-, N-) GaAa, 88 is N-AtGaAa.

89は2次元ホールガス、90は2次元電子ガス、91
、93はソース、ドレイン電極、92はゲート電極、9
4.96はソース、ドレイン電極、95はゲート電極、
97はPチャネルFET、98はNチャネルPETを示
す。
89 is a two-dimensional hole gas, 90 is a two-dimensional electron gas, 91
, 93 is a source and drain electrode, 92 is a gate electrode, 9
4.96 is the source and drain electrodes, 95 is the gate electrode,
97 indicates a P-channel FET, and 98 indicates an N-channel PET.

(問題点を解決するための手段) 本発明の目的は、PN接合光起電力装置において、キャ
リヤーが不純物ドープされた半導体内を走行することに
よる特性劣化を防ぎ、またプレーナ形とすることで電極
設置位置からくる工程、素子構造への制限をとりのぞき
、簡便で高性能な光起電力装置を実現すること、また、
これを用いて、高性能な無バイアス光電流検出器、無バ
イアスフォトトランジスタを実現することにある。また
同時に、同一結晶を用いて、プレーナ形の簡便なN形お
よびP形のしきい値制御可能な電界効果トランジスタを
形成して、コンプリメンタリ−回路を実現すること、か
つ上記のさまざまな素子を同一結晶上に組み合わせて、
光電子回路を実現することにある。
(Means for Solving the Problems) An object of the present invention is to prevent characteristic deterioration caused by carriers traveling in an impurity-doped semiconductor in a PN junction photovoltaic device, and to provide a planar type electrode. To realize a simple and high-performance photovoltaic device by removing restrictions on the process and element structure due to installation location, and
The aim is to use this to realize high-performance non-biased photocurrent detectors and non-biased phototransistors. At the same time, it is also possible to realize a complementary circuit by forming simple planar type N-type and P-type field effect transistors with controllable threshold values using the same crystal, and to use the same crystal for the various elements mentioned above. Combined on a crystal,
The goal is to realize optoelectronic circuits.

上記の目的を達成する九め、本発明はPN接合間にエネ
ルギーギャップの小さい、ノンドープ第3半導体装置し
、ヘテロ界面に生じる2次元ガスの伝導を利用すること
により、光励起され結晶の内部電界によって加速された
キャリヤーを、結晶膜面に平行に、かつノンドープ半導
体中を走行させることを第1の主要な特徴とする。従来
の技術とは、結晶層構造が、第3半導体装置という点で
異なシ、またオーミック電極の設置がすべて結晶の同一
表面上でよいという点で異なる。
Ninth, to achieve the above object, the present invention provides a non-doped third semiconductor device with a small energy gap between PN junctions, and utilizes the conduction of two-dimensional gas generated at the hetero interface, which is photoexcited by the internal electric field of the crystal. The first main feature is that the accelerated carriers are made to travel parallel to the crystal film plane and through the non-doped semiconductor. The present invention differs from the conventional technology in that the crystal layer structure is a third semiconductor device, and the ohmic electrodes can all be placed on the same surface of the crystal.

(実施例) 次に本発明の詳細な説明する0なお実施例は一つの例示
でおって、本発明の精神を逸脱しない範囲で、種々の変
更あるいは改良を行いうることは言うまでもない。
(Embodiments) Next, the present invention will be described in detail.The embodiments are merely illustrative, and it goes without saying that various changes and improvements can be made without departing from the spirit of the present invention.

(I)  第1図は、本発明による実施例の結晶構造の
模式図、第2図はそのバンドダイヤグラムである0 第1図に示した例のように、ノンドープのGaAs 3
0をPドープのAto、5 Ga 6.5 AB 29
とNドープのAt□、5 caO,5As 31ではさ
むと、第1図ノヨウにGaAs30のP −Ato、5
Gao、5 AS 29側ヘテロ界面には2次元ホール
ガス40、N −At6.5 Ga O,S As側ヘ
テロ界面には2次元電子ガス39が生じる。あは基板、
あは光照射面を示す。
(I) Figure 1 is a schematic diagram of the crystal structure of an example according to the present invention, and Figure 2 is its band diagram.0 As in the example shown in Figure 1, non-doped GaAs 3
0 is P-doped Ato, 5 Ga 6.5 AB 29
and N-doped At□, 5 caO, 5As 31, as shown in Fig.
A two-dimensional hole gas 40 is generated at the hetero interface on the Gao, 5 AS 29 side, and a two-dimensional electron gas 39 is generated at the hetero interface on the N - At6.5 Ga O, SA side. Aha board,
A indicates the light irradiation surface.

ここで、ノンドープG&As 42中には第2図に示ス
ようなポテンシャルの傾斜が生じ、そこには従ってきわ
めて大きな内部電界が生じることとなる。例として、ノ
ンドープQaAs層厚を100OAとし、GaAsバン
ドエネルギーギャップを1−4eVと仮定すると、計算
上平均内部電界は140 KVlonにも達する。41
はN −AfflaAs 、 43はp −AtGaA
s ’z示す。
Here, a potential gradient as shown in FIG. 2 occurs in the non-doped G&As 42, and an extremely large internal electric field is therefore generated there. As an example, assuming that the non-doped QaAs layer thickness is 100 OA and the GaAs band energy gap is 1-4 eV, the calculated average internal electric field reaches 140 KVlon. 41
is N-AfflaAs, 43 is p-AtGaA
Show s'z.

従って、このノンドープGaAa層42中に光照射射に
よって電子37.ホールあが生ずると、各各のキャリヤ
ーは大きな内部電界によってほとんど飽和速度でヘテロ
界面へと流れ込む。従って、ノンドープGaAsチャネ
ル層に対して、P形およびN形のオーミックコンタクト
を夫々Beイオン、 Stイオン等によるイオン注入お
よびAuZnNi / Ti / Au + AuGe
 /Ni等による70イにより、結晶膜平面上に形成し
、電気的に接続すると、第3図に示すようにこの両電極
間には、最高〜1.4 V (GaAsのバンドエネル
ギーギャップ)の光起電力が生じる。図中45はP形オ
ーミック電極、46はN形オーミック電極、47はメサ
分離、48は励起光、49は光照射半導体全話す。
Therefore, electrons 37. When a hole is generated, each carrier flows into the heterointerface at almost saturation velocity due to the large internal electric field. Therefore, P-type and N-type ohmic contacts are made to the non-doped GaAs channel layer by ion implantation using Be ions, St ions, etc., and AuZnNi/Ti/Au + AuGe.
When formed on the plane of a crystal film using 70mm /Ni etc. and electrically connected, a voltage of up to 1.4 V (band energy gap of GaAs) is generated between these two electrodes as shown in Figure 3. A photovoltaic force is generated. In the figure, 45 is a P-type ohmic electrode, 46 is an N-type ohmic electrode, 47 is a mesa separation, 48 is an excitation light, and 49 is a light irradiation semiconductor.

ヘテロ界面を結晶膜平面と平行に伝導するキャリヤーは
、従来のPN接合光電池と異なりチャネルがノンドープ
QaAs内にあるため不純物散乱が小さく低抵抗となシ
、また再結合もしにくい。このため、光−起電力変換効
率はきわめてよいものになる。また、生ずるキャリヤー
の総数は光受光面積に比例し、プレーナ形構成であるた
め受光面は簡便に任意に大きくできることも、従来装置
と異なるものである。
Unlike conventional PN junction photovoltaic cells, carriers that conduct through the heterointerface parallel to the plane of the crystal film have a channel in non-doped QaAs, so impurity scattering is small, the resistance is low, and recombination is also difficult. Therefore, the photo-electromotive force conversion efficiency is extremely high. Another difference from conventional devices is that the total number of carriers generated is proportional to the light-receiving area, and because of the planar configuration, the light-receiving surface can be easily made arbitrarily large.

(6)一方、上記結晶に第4図に示したように、2個の
N形のオーミック電極55.56i形成し、これらの電
極55.56間にバイアス電圧52を印加し、これらの
電極にはさまれた半導体領域別に照射光50ヲあて、キ
ャリヤーを励起すると、光電流53が両電極間に流れる
ことになる。この際のキャリャーの生成からヘテロ界面
への伝導、ペテロ界面上ノ伝導に関しては、(1)と同
様大きな結晶内部電界により光励起されたキャリヤーが
まず加速され、次にキャリヤーは不純物散乱の少ないノ
ンドープ結晶ヘテロ界面を高速で流れるので、検出速度
、検出効率が一般のものより向上する。
(6) On the other hand, as shown in FIG. 4, two N-type ohmic electrodes 55 and 56i are formed on the crystal, and a bias voltage 52 is applied between these electrodes 55 and 56. When irradiation light 50 is applied to each sandwiched semiconductor region to excite carriers, a photocurrent 53 flows between the two electrodes. Regarding carrier generation, conduction to the heterointerface, and conduction on the Peter interface, as in (1), carriers that are photoexcited by the large internal electric field of the crystal are first accelerated, and then the carriers are transferred to the non-doped crystal with less impurity scattering. Since it flows at high speed through the hetero interface, the detection speed and detection efficiency are improved compared to general ones.

(III)第5図は同一結晶を用いて(I)にて示した
光電池を(ト)にて示した光電流検出器のバイアス電圧
源として用いることにより、無バイアスの光検出器を構
成する場合の例である。図中57は励起光、58はメサ
分離、59はN形オーミック電極、60はP形オーミッ
ク電極、61.62はN形オーミック電極、63 、6
4は光照射半導体を示す。すなわちN形オーミック電極
59.P形オーミック電極ω間に生じた光起電力を、N
形オーミック電極61 、62間にバイアスとして加え
る。ここで電極59 、60間の光起電圧’k 1.4
 Vとして、この電極間の距離を5μmとすると、ヘテ
ロ界面のキャリヤーには3KV/an程度の電界が働き
、十分にキャリヤーを加速することができる。
(III) In Figure 5, a non-biased photodetector is constructed by using the same crystal and the photocell shown in (I) as the bias voltage source of the photocurrent detector shown in (G). This is an example of a case. In the figure, 57 is an excitation light, 58 is a mesa separation, 59 is an N-type ohmic electrode, 60 is a P-type ohmic electrode, 61.62 is an N-type ohmic electrode, 63, 6
4 indicates a light-irradiated semiconductor. That is, the N-type ohmic electrode 59. The photovoltaic force generated between the P-type ohmic electrode ω is expressed as N
A bias is applied between the ohmic electrodes 61 and 62. Here, the photovoltaic voltage 'k between the electrodes 59 and 60 is 1.4
If the distance between the electrodes is 5 μm, an electric field of about 3 KV/an acts on the carriers at the hetero interface, and the carriers can be sufficiently accelerated.

このように単に平面上に配置された各檀オーミック電極
間の配線組み合わせのみによって無バイアスの光検出器
を簡便に実現できる。
In this way, a bias-free photodetector can be easily realized simply by combining the wires between the ohmic electrodes arranged on a plane.

(■第6図は同一結晶を用いて■にて示した光検出装置
を形成し、この2個のオーミック電極66゜67間の半
導体錦上にs Ti+ Au等のショットキーゲート電
極69ヲ設置し、N形電界効果トランジスタないしフォ
トトランジスタを構成する例である。65はメサ分離ケ
示す。
(■ In Fig. 6, the same crystal is used to form the photodetector shown in ■, and a Schottky gate electrode 69 made of sTi+Au or the like is installed on the semiconductor plate between these two ohmic electrodes 66 and 67. This is an example of configuring an N-type field effect transistor or a phototransistor. 65 indicates a mesa isolation.

この場合のゲート電極下のバンド・ダイヤグラムな第7
図に示すが、ゲート印加電圧によりヘテロ界面の2次元
ガスを制御する機構は、通常の2次元電子ガスヘテロ構
造FETと同じである。
In this case, the seventh band diagram under the gate electrode is
As shown in the figure, the mechanism for controlling the two-dimensional gas at the hetero interface using the applied gate voltage is the same as that of a normal two-dimensional electron gas heterostructure FET.

従って、ゲート電極を透明度の高いものにすれば高性能
のフォトトランジスタを形成できる。
Therefore, if the gate electrode is made highly transparent, a high-performance phototransistor can be formed.

フォトトランジスタは光を照射しなければ、通常の電界
効果トランジスタと同様に機能する0また(口)と同様
、同一結晶に形成した光電池と組み合わせれば、無バイ
アスのフォトトランジスタを構成することもできる。
If a phototransistor is not irradiated with light, it functions in the same way as a normal field effect transistor.As with 0, a non-biased phototransistor can be constructed by combining it with a photovoltaic cell formed in the same crystal. .

第7図はバンドダイヤグラムを示す。図中70はゲート
電極、71はN −AtGaAa 、 72はノンドー
プ(p”’、 N−) GaAs 、 73はP −A
tGaAs 、 143は2次元電子ガス、144は励
起光、145は光励起電子を示す。
FIG. 7 shows a band diagram. In the figure, 70 is a gate electrode, 71 is N-AtGaAa, 72 is non-doped (p"', N-) GaAs, and 73 is P-A.
tGaAs, 143 is a two-dimensional electron gas, 144 is an excitation light, and 145 is a photoexcited electron.

(V)  また第7図と同じ原理に基づき、ゲート電圧
を負に印加することでP形結晶とのヘテロ界面に生じた
2次元ホールガスの濃度をコントロールすることにより
(第8図参照9.P形トランジスタも同一結晶で構成で
きる。第8図において、99はゲート電極、100はP
 −AtGaAs、101はノンドープ(p−、N−)
 GaAs 、 102はN −AにaAa 。
(V) Based on the same principle as shown in Fig. 7, the concentration of the two-dimensional hole gas generated at the hetero interface with the P-type crystal is controlled by applying a negative gate voltage (see Fig. 8). P-type transistors can also be constructed from the same crystal.In Fig. 8, 99 is a gate electrode, and 100 is a P-type transistor.
-AtGaAs, 101 is non-doped (p-, N-)
GaAs, 102 aAa to N-A.

103は2次元電子ガス、104は2次元ホールガスを
示す。この場合は、オーミック電極全P形のものを使用
する。N形とP形のトランジスタを同一結晶上にプレー
ナ形に形成することができるので、従来のものより、は
るかに簡便にコンプリメンタリ−回路を構成できる(第
9図参照)。第9図において、105は基板、106は
P−ALGaAa 、 107はノンドープA/[aA
s 、  108はN −AtGaAs 、  109
はノンドープA司aAs 、  110はノンドープG
aAs 1111はノンドープQaAs%112は2次
元ホールガス、113は2次元電子ガス、  114 
、 116はP形オーミック電極、115はゲート電極
、117 、 119はN形オーミック電極、118は
ゲート電極、120 、121はPイオン注入領域、1
22,123はNイオン注入領域、124は素子間分離
を示す。
103 is a two-dimensional electron gas, and 104 is a two-dimensional hole gas. In this case, all P-type ohmic electrodes are used. Since N-type and P-type transistors can be formed in a planar shape on the same crystal, a complementary circuit can be constructed much more easily than the conventional one (see FIG. 9). In FIG. 9, 105 is a substrate, 106 is P-ALGaAa, and 107 is non-doped A/[aA
s, 108 is N-AtGaAs, 109
is non-doped As, 110 is non-doped G
aAs 1111 is non-doped QaAs% 112 is a two-dimensional hole gas, 113 is a two-dimensional electron gas, 114
, 116 is a P-type ohmic electrode, 115 is a gate electrode, 117 and 119 are N-type ohmic electrodes, 118 is a gate electrode, 120 and 121 are P ion implantation regions, 1
Reference numerals 22 and 123 indicate N ion implantation regions, and 124 indicates isolation between elements.

この手法によるコンプリメンタリ−回路構成では、N形
、P形へのドーピング濃度の制御ないしN形、P形の両
トランジスタのゲート下のりセスエッチ量の制御(第1
0図参照)により、しきい値を整合でき高性能を図れる
という利点がある。第10図において、125は基板、
126はN −A九aAs 、  127はノンドープ
AtGaAs s 128はノンドープGaAs 、 
129はノンドープA汚aAs 。
In the complementary circuit configuration using this method, the doping concentration for N-type and P-type is controlled, or the amount of etching under the gates of both N-type and P-type transistors is controlled (first
(See Figure 0) has the advantage of matching threshold values and achieving high performance. In FIG. 10, 125 is a substrate;
126 is N-A9As, 127 is non-doped AtGaAs, 128 is non-doped GaAs,
129 is non-doped A stain aAs.

130はP −AtGaAa s  131はノンドー
プGaAs、132 、134はP形オーミック電極′
% 133はゲート電極、135 、 137はN形オ
ーミック電極、136はゲート電極、138は2次元ホ
ールガス、・139は2次元電子ガス、140 、14
1はりセス−エッチ、142は素子間分離を示す。また
、Ni fゲートメタルとして用い熱処理によりメタル
を沈下させ、しきい値制御するという方法も適用できる
。(参考文献: IEEE、 EDL、Vol、 BD
L−5No、 7 1984 p241 )更に、後述
のように、P形半導体を上層にしN形半導体を下層にす
ることで、P形のコンタミによるパラレルコンダクショ
ンによるリーク電流の影響を除去できる次め、回路の低
消費電力化にも利点がある。
130 is P-AtGaAas, 131 is non-doped GaAs, 132 and 134 are P-type ohmic electrodes.
% 133 is a gate electrode, 135 and 137 are N-type ohmic electrodes, 136 is a gate electrode, 138 is a two-dimensional hole gas, 139 is a two-dimensional electron gas, 140 and 14
1 indicates a process-etch, and 142 indicates isolation between elements. Furthermore, a method of controlling the threshold value by using the Nif gate metal and sinking the metal through heat treatment can also be applied. (References: IEEE, EDL, Vol, BD
L-5 No., 7 1984 p241) Furthermore, as described later, by placing a P-type semiconductor in the upper layer and an N-type semiconductor in the lower layer, the influence of leakage current due to parallel conduction due to P-type contamination can be removed. There is also an advantage in reducing the power consumption of the circuit.

(6)以上のように光電池、光電流検出器、N形および
P形電界効果トランジスタ、フォトトランジスタにすべ
て同一結晶を用いてプレーナ形に形成できるため、同一
ウニノ・−上にこれらt−組み合わせて形成し様々な光
電子回路を構成することができる。
(6) As described above, the photocell, photocurrent detector, N-type and P-type field effect transistors, and phototransistor can all be formed into a planar shape using the same crystal, so these can be combined on the same unit. can be formed to construct various optoelectronic circuits.

(至)なお、以上に用いた結晶の層構造としては、第9
図および第10図に示し友ようにヘテロ界面近傍のAt
O,5Ga 0.5Asの不純物濃度を小さくすると1
不純物の拡散や散乱の効果を抑!Ijして素子性能の向
上に有効である。また、混晶のAt組成比は帆5以外の
ものでも可能である。更に、P。
(To) The layer structure of the crystal used above is the 9th layer structure.
As shown in Fig. 1 and Fig. 10, At near the hetero interface
When the impurity concentration of O,5Ga 0.5As is reduced, 1
Suppresses the effects of impurity diffusion and scattering! Ij is effective for improving device performance. Further, the At composition ratio of the mixed crystal may be other than the sail 5. Furthermore, P.

N半導体について、これらへのドーピング濃度を、ヘテ
ロ界面に近いほど大きく、遠いほど小さくして分布させ
丁度ヘテロ界面へのキャリヤーの供給によってPN半導
体層は空乏化するように構成すると、オーミックコンタ
クトをとった際に、高移動度の2次元ガス以外のパラレ
ルコンダクションをひるわないですむ。
For N semiconductors, if the doping concentration is distributed such that it is higher nearer to the hetero interface and lower closer to the hetero interface, and the PN semiconductor layer is depleted by supplying carriers to the hetero interface, ohmic contact can be made. In this case, there is no need to worry about parallel conduction except for high-mobility two-dimensional gases.

また、一般にMBE結晶では結晶がP−形のコンタミを
持つ定め、P形のパラレルコンダクションを防ぐ手法と
して、結晶の上層tp形として、下層’(zN形とする
方法がある0このように構成すればP形オーミックを結
晶厚方向に深くしすぎなければ容易に、P形のパラレル
コンダクションを除去できる。ALo、sGa 6.5
A8表面に保護用のノンドープGaAa 7m ’ft
キャップとして設けると、表面酸化等から防ぐことがで
きる。
In addition, it is generally assumed that the MBE crystal has P-type contamination, and as a method to prevent parallel conduction of the P-type, there is a method of making the upper layer of the crystal tp type and the lower layer '(zN type). If the P-type ohmic is not made too deep in the crystal thickness direction, the P-type parallel conduction can be easily removed. ALo, sGa 6.5
Non-doped GaAa 7m'ft for protection on A8 surface
When provided as a cap, it can prevent surface oxidation and the like.

(発明の効果) 以上説明したように、本発明によれば、光励起キャリヤ
ーに働く内部電界が大きく、かつ、2次元電子ガス、2
次元ホールガスの利用によりネ細物散乱・再結合による
特性劣化の少ない、高性能の光起電力装置、光電流検出
装置、フォトトランジスタ、またこれら9組み合わせに
よる無バイアスの光検出器、無バイアスのフォトトラン
ジスタ等を同一結晶上に製作が一容易なプレーナ形に構
成できる。これは、光センサ−。
(Effects of the Invention) As explained above, according to the present invention, the internal electric field acting on the photoexcited carrier is large, and the two-dimensional electron gas
High-performance photovoltaic devices, photocurrent detection devices, and phototransistors that have little characteristic deterioration due to particle scattering and recombination by using dimensional hole gas, as well as non-bias photodetectors and non-bias photodetectors made by combining these nine devices. Phototransistors and the like can be formed into a planar shape that is easy to manufacture on the same crystal. This is a light sensor.

光電源等に応用できる。Can be applied to optical power sources, etc.

また更に、同一結晶上に、高移動度の2次元ガスをキャ
リヤーとして用いる高性能のN形。
Furthermore, a high-performance N type using a high-mobility two-dimensional gas as a carrier on the same crystal.

P形の電界効果トランジスタをしきい値整合して形成し
、高性能のコンプリメンタリ−回路を同様にプレーナ形
に構成できる。これら様々な光電子素子を同一結晶上に
組み合わせて構成し高性能の光電子回路を実現し、計算
機、中継器等の光通信機暮などに応用することができる
効果を有するものである。
By forming P-type field effect transistors with threshold matching, high-performance complementary circuits can also be constructed in a planar type. By combining these various optoelectronic elements on the same crystal, a high-performance optoelectronic circuit can be realized, which has the effect of being applicable to optical communication devices such as computers and repeaters.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明による光起電力装置の結晶構造を示す図
、第2図は本発明の第一の特徴を最もよく表わしている
光起電力装置の原理を示すバンドダイヤグラム、第3図
は本発明による光起電力装置の構成図、第4図は本発明
による光、電流検出装置の構成図、第5図は本発明によ
る無バイアス光電流検出装置の構成図、第6図は本発明
による(光)電界効果トランジスタの構成図、第7図は
本発明による(恵電界効果トランジスタの原理を示すバ
ンドダイヤグラム、第8図は本発明の第二の特徴を最も
よく表わしているコンプリメンタリ−回路の原理を示す
)くンドダイヤグラム、第9図は本発明によるコンプリ
メンタリ−回路構成の一実施例、第10図は本発明によ
るコンプリメンタリ−回路構成の他の実施例、第11図
は従来のPN接合光起電力装置の模式図、第12図は従
来のPN接合光起電力装置の原理を示し迄バンドダイヤ
グラム、第13図は従来の光電流検出器の模式図、第1
4図は従来の無バイアス光電流検出器の原理を示したバ
ンドダイヤグラム、第15図は従来の無バイアス光電流
検出器の模式図、第16図は従来のコンプリメンタリ−
回路の構成模式図を示す。 1.10・・・・・・・・・・・・・・・P型半導体2
.9,13.14・・・N型半導体 3・・・・・・・・・・・・・・・・・・・・・PN接
合面4、32,45 、60.91,93.114.1
16.132゜134・・・・・・・・・・・・・・・
・・・P形オーミック電極5、22.23.33.46
.55.56.59,61,62,66゜67、94.
96 、117 、119 、135 、137・・・
・・・・・・・・・・・・・・・・・・・・・・・・・
・・・・・・・・N形オーミック電極6 、11.15
.34.44.48.50.57 、144・・・・・
・・・・・・・・・・・・・・・・・・・・・・・・・
・・・励起光7 、16 、37.145・・・光励起
電子97  ・・・・・・・・・・・・・・・・・・P
チャネルFET98  ・・・・・・・・・・・・・・
・・・・NチャネルFET8.17.38・・・・・・
・・・光励起ホールル、 24.36.49 、54.
63 、64・・・・・・・・・・・・・・・・・・・
−・・・・・・・・・・・・・・・・・・・・・・・・
・・・・光被照射半導体δ・・・・・・・・・・・・・
・・・・・・・・導電層47、51 、58.65・・
・メサ分離18.31,41.71.88. 102.
 108. 126・・・・・・・・・・・・・・・・
・・・・・・・・・・・・・・・−・N−AtGaAs
107 、 109 、 127 、 129 ・・・
・・・・・・・・・・・・・・・・・・・・・・・・・
・・・・・・・・・・・・・・・・・・・・・・・・・
・ノンドープ(p″+、 、f) AtGaAs19.
30.42,72,82. 101 、 110. 1
11. 128゜131・・・・・・・・・・・・・−
・・・・ノンドープ(p−、f) GaAs20・・・
・・・・・・・・・・・・・・・・・・ヘテロ界面12
0 、121・・・・・・・・・rイオン注入領域12
2 、123・・・・・・・・・tイオン注入領域21
.39,90. 103. 113. 139. 14
3 ・・・・・・・・・・・・・・・・・・・・・・・
・・・・・・・・・・・・・2次元電子ガス菊、89 
、 104 、 112 、 138 ・・・・・・・
・・・・・・・・・・・・・・・・・・・・2次元ホー
ルガス 124.142・・・・・・・・・素子間分離26.5
2・・・・・・・・・・・・・・・バイアス電圧n、5
3・・・・・・・・・・・・・・・光電流140.14
1・・・・・・・・・リセス・エッチ29.43,73
,86 、 100 、 106 、 130=−−−
・−・・−−・・・−・・・・・・・・・・・・・・・
・・・・・・・・・P−AtGaAs訪、85.105
.125・・・バッファ一層、基板等69.70,92
.95.99. 115. 118. 133. 13
6・・・・・・・・・・・・・・・・・・・・・・・・
ゲート電極特許出願人  日本電信電話株式会社 第1図 第3図 第4図 第5図 第8図 屡二算二」−レ慣 秦9図 第10図 第11図 9÷10 第15図
FIG. 1 is a diagram showing the crystal structure of the photovoltaic device according to the present invention, FIG. 2 is a band diagram showing the principle of the photovoltaic device that best expresses the first feature of the present invention, and FIG. FIG. 4 is a block diagram of a photovoltaic device according to the present invention. FIG. 4 is a block diagram of a light and current detection device according to the present invention. FIG. 5 is a block diagram of a non-bias photocurrent detection device according to the present invention. FIG. 7 is a band diagram showing the principle of the (optical) field effect transistor according to the present invention, and FIG. 8 is a complementary circuit that best represents the second feature of the present invention. Figure 9 is an example of a complementary circuit configuration according to the present invention, Figure 10 is another example of a complementary circuit configuration according to the present invention, and Figure 11 is a conventional PN junction diagram. A schematic diagram of a photovoltaic device; Fig. 12 is a band diagram showing the principle of a conventional PN junction photovoltaic device; Fig. 13 is a schematic diagram of a conventional photocurrent detector;
Figure 4 is a band diagram showing the principle of a conventional non-bias photocurrent detector, Figure 15 is a schematic diagram of a conventional non-bias photocurrent detector, and Figure 16 is a conventional complementary photocurrent detector.
A schematic diagram of the circuit configuration is shown. 1.10・・・・・・・・・・・・P-type semiconductor 2
.. 9, 13.14...N-type semiconductor 3......PN junction surface 4, 32, 45, 60.91, 93.114. 1
16.132゜134・・・・・・・・・・・・・・・
...P-type ohmic electrode 5, 22.23.33.46
.. 55.56.59,61,62,66°67,94.
96, 117, 119, 135, 137...
・・・・・・・・・・・・・・・・・・・・・・・・
・・・・・・N-type ohmic electrode 6, 11.15
.. 34.44.48.50.57, 144...
・・・・・・・・・・・・・・・・・・・・・・・・
...Excitation light 7, 16, 37.145...Photoexcited electron 97...P
Channel FET98 ・・・・・・・・・・・・・・・
...N-channel FET8.17.38...
...Photoexcitation hall, 24.36.49, 54.
63, 64・・・・・・・・・・・・・・・・・・
−・・・・・・・・・・・・・・・・・・・・・・・・
...Light-irradiated semiconductor δ...
...... Conductive layers 47, 51, 58.65...
・Mesa separation 18.31, 41.71.88. 102.
108. 126・・・・・・・・・・・・・・・
・・・・・・・・・・・・・・・-・N-AtGaAs
107, 109, 127, 129...
・・・・・・・・・・・・・・・・・・・・・・・・
・・・・・・・・・・・・・・・・・・・・・・・・
・Non-doped (p″+, , f) AtGaAs19.
30.42,72,82. 101, 110. 1
11. 128゜131・・・・・・・・・・・・−
...Non-doped (p-, f) GaAs20...
・・・・・・・・・・・・・・・Hetero interface 12
0, 121...r ion implantation region 12
2, 123...T ion implantation region 21
.. 39,90. 103. 113. 139. 14
3 ・・・・・・・・・・・・・・・・・・・・・・・・
・・・・・・・・・・・・Two-dimensional electronic gas chrysanthemum, 89
, 104, 112, 138...
・・・・・・・・・・・・・・・・・・Two-dimensional hole gas 124.142・・・・・・・・・Separation between elements 26.5
2・・・・・・・・・・・・Bias voltage n, 5
3・・・・・・・・・・・・Photocurrent 140.14
1・・・・・・Recess Etch 29.43,73
,86,100,106,130=---
・-・・−−・・・−・・・・・・・・・・・・・・・
・・・・・・・・・P-AtGaAs visit, 85.105
.. 125...Buffer single layer, board etc. 69.70,92
.. 95.99. 115. 118. 133. 13
6・・・・・・・・・・・・・・・・・・・・・・・・
Gate electrode patent applicant Nippon Telegraph and Telephone Corporation Figure 1 Figure 3 Figure 4 Figure 5 Figure 8

Claims (8)

【特許請求の範囲】[Claims] (1)基板上に形成されたPN接合を用いた光起電力半
導体装置において、前記のPN接合間に、P形およびN
形半導体のいずれよりも、バンドエネルギーギャップが
小で、かつノンドープないし、低ドープの第3半導体層
を配設し、前記の第3半導体層に対して、P形オーミッ
クコンタクトと、N形オーミックコンタクトを夫々形成
して、光起電力装置を構成することを特徴とする半導体
装置。
(1) In a photovoltaic semiconductor device using a PN junction formed on a substrate, a P-type and an N-type are connected between the PN junctions.
A non-doped or lightly doped third semiconductor layer having a band energy gap smaller than that of any of the type semiconductors is provided, and a P-type ohmic contact and an N-type ohmic contact are provided to the third semiconductor layer. 1. A semiconductor device characterized in that a photovoltaic device is constructed by forming each of these.
(2)基板上に形成された光起電力半導体装置において
、前記のPN接合間に、P形およびN形半導体のいずれ
よりも、バンドエネルギーギャップが小で、かつノンド
ープないし、低ドープの第3半導体層を配設し、前記の
第3半導体層に対して、2個のN形オーミック電極を形
成し、前記の電極間にバイアス電圧を与えて光電流検出
装置を構成することを特徴とする半導体装置。
(2) In a photovoltaic semiconductor device formed on a substrate, a non-doped or lightly doped third semiconductor having a smaller band energy gap than both P-type and N-type semiconductors is placed between the PN junctions. A photocurrent detection device is constructed by disposing a semiconductor layer, forming two N-type ohmic electrodes on the third semiconductor layer, and applying a bias voltage between the electrodes. Semiconductor equipment.
(3)基板上に形成された光起電力半導体装置において
、前記のPN接合間に、P形およびN形半導体のいずれ
よりも、バンドエネルギーギャップが小で、かつノンド
ープないし、低ドープの第3半導体層を配設し、前記の
第3半導体層に対して、2個のN形オーミック電極を形
成し、前記の電極間にバイアス電圧を与えて光電流検出
装置を構成し、また同一結晶の他の領域で前記の第3半
導体層に対してP形およびN形オーミック電極を形成し
て、光起電力装置を構成し、前記の光起電力装置を、前
記の光電流検出装置のバイアス電源として用い、無バイ
アス光電流検出装置を構成することを特徴とする半導体
装置。
(3) In the photovoltaic semiconductor device formed on the substrate, a non-doped or lightly doped third semiconductor having a smaller band energy gap than both the P-type and N-type semiconductors is placed between the PN junctions. A semiconductor layer is provided, two N-type ohmic electrodes are formed on the third semiconductor layer, a bias voltage is applied between the electrodes to constitute a photocurrent detection device, and a photocurrent detection device is constructed. P-type and N-type ohmic electrodes are formed on the third semiconductor layer in other regions to configure a photovoltaic device, and the photovoltaic device is connected to a bias power source of the photocurrent detection device. 1. A semiconductor device characterized in that it is used as a non-bias photocurrent detection device.
(4)PN接合間にP形およびN形半導体のいずれより
も、バンドエネルギーギャップが小で、かつノンドープ
ないし、低ドープの第3半導体層を配設し素子間分離に
より2個の半導体素子を形成し、前記の一方の半導体素
子の第3半導体層に対し、2個のP形オーミック電極を
形成し、このP形オーミック電極の間に、はさまれた半
導体結晶表面上に、この電極と離してショットキ電極を
設けてP形電界効果トランジスタを構成し、さらに他方
の半導体素子の両側に夫々N形領域を形成し、この領域
にN形オーミック電極を形成し、このN形オーミック電
極間に、この電極と離してショットキ電極を設けN形電
界効果トランジスタを構成して、コンプリメンタリ回路
を構成した特許請求の範囲第1項記載の半導体装置。
(4) A non-doped or lightly doped third semiconductor layer with a smaller band energy gap than both P-type and N-type semiconductors is disposed between the PN junctions, and two semiconductor elements can be separated by device isolation. two P-type ohmic electrodes are formed on the third semiconductor layer of one of the semiconductor elements, and a layer is formed on the surface of the semiconductor crystal sandwiched between the P-type ohmic electrodes. Schottky electrodes are provided separately to form a P-type field effect transistor, and further, N-type regions are formed on both sides of the other semiconductor element, N-type ohmic electrodes are formed in these regions, and between the N-type ohmic electrodes 2. The semiconductor device according to claim 1, wherein a Schottky electrode is provided apart from this electrode to constitute an N-type field effect transistor to constitute a complementary circuit.
(5)N形電界効果トランジスタに形成されたショット
キ電極を透明電極としてフォトトランジスタを形成し、
同一の基板上に形成された光起電力装置と組み合せて、
無バイアスのフォトトランジスタを構成した特許請求の
範囲第1項記載の半導体装置。
(5) Forming a phototransistor using the Schottky electrode formed in the N-type field effect transistor as a transparent electrode,
In combination with a photovoltaic device formed on the same substrate,
The semiconductor device according to claim 1, which comprises a non-biased phototransistor.
(6)P形およびN形半導体としてAl_xGa_(_
1_−_x_)As、Al_yGa_(_1_−_y_
)As(0<x、y≦1)を用い、第3半導体としてノ
ンドープGaAsを用いることを特徴とする特許請求の
範囲第1項、第2項、第3項、第4項または第5項記載
の半導体装置。
(6) Al_xGa_(_
1_-_x_)As, Al_yGa_(_1_-_y_
) As (0<x, y≦1), and non-doped GaAs is used as the third semiconductor. The semiconductor device described.
(7)P形およびN形半導体のヘテロ界面近傍40〜1
50Åの範囲をノンドープとすることを特徴とする特許
請求の範囲第1項、第2項、第3項、第4項、第5項ま
たは第6項記載の半導体装置。
(7) Near the hetero interface of P-type and N-type semiconductors 40-1
7. The semiconductor device according to claim 1, 2, 3, 4, 5, or 6, characterized in that a range of 50 Å is non-doped.
(8)P形およびN形半導体のドーピングを、ヘテロ界
面に近いほど大に、界面より遠ざかるに従い小となるよ
うにプロファイルをもたせたことを特徴とする特許請求
の範囲第1項、第2項、第3項、第4項、第5項、第6
項または第7項記載の半導体装置。
(8) The doping of the P-type and N-type semiconductors is characterized by having a profile such that the doping becomes larger closer to the hetero interface and smaller as the distance from the interface increases. , 3rd term, 4th term, 5th term, 6th term
7. The semiconductor device according to item 7.
JP60129966A 1985-06-17 1985-06-17 Semiconductor device Expired - Lifetime JPH0728046B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60129966A JPH0728046B2 (en) 1985-06-17 1985-06-17 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60129966A JPH0728046B2 (en) 1985-06-17 1985-06-17 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS61288474A true JPS61288474A (en) 1986-12-18
JPH0728046B2 JPH0728046B2 (en) 1995-03-29

Family

ID=15022832

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60129966A Expired - Lifetime JPH0728046B2 (en) 1985-06-17 1985-06-17 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0728046B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016219805A (en) * 2015-05-18 2016-12-22 三星電子株式会社Samsung Electronics Co.,Ltd. Semiconductor element including two-dimensional material, and method of manufacturing the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60247979A (en) * 1984-05-24 1985-12-07 Kokusai Denshin Denwa Co Ltd <Kdd> Semiconductor optical element
JPS61135168A (en) * 1984-12-06 1986-06-23 Nec Corp Semiconductor light-receiving element

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60247979A (en) * 1984-05-24 1985-12-07 Kokusai Denshin Denwa Co Ltd <Kdd> Semiconductor optical element
JPS61135168A (en) * 1984-12-06 1986-06-23 Nec Corp Semiconductor light-receiving element

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016219805A (en) * 2015-05-18 2016-12-22 三星電子株式会社Samsung Electronics Co.,Ltd. Semiconductor element including two-dimensional material, and method of manufacturing the same

Also Published As

Publication number Publication date
JPH0728046B2 (en) 1995-03-29

Similar Documents

Publication Publication Date Title
JPH02135786A (en) Solar battery cell
US7659474B2 (en) Solar cell array with isotype-heterojunction diode
JPS60244078A (en) Back surface illumination photodiode having wide band gap cap layer
WO2018124641A1 (en) Compound semiconductor solar cell
JPH01205472A (en) Solar battery cell
EP0984494B1 (en) Solar battery
JP3368822B2 (en) Solar cell
US6586272B1 (en) Method for manufacturing MSM photodetector or using a HEMT structure incorporating a low-temperature grown semiconductor
JPH0656900B2 (en) Semiconductor optical device
JPS61288474A (en) Semiconductor device
JPH11330536A (en) Semiconductor light receiving element
JP3688909B2 (en) Semiconductor photo detector
Novo et al. Responsivity improvement for short wavelenghts using full-gated PIN lateral SiGe diode
JPH05343731A (en) Photodetector
KR20150014298A (en) Compound semiconductor solar cell
US20220376127A1 (en) Improvements in Direct Semiconductor Solar Devices
JPH0750429A (en) Photodetector and manufacture thereof
JPH07231108A (en) Solar cell
JP2854634B2 (en) Light receiving device
Yacobi Applications of semiconductors
JP2001237454A (en) Semiconductor light-receiving element
RU1003702C (en) Solar photoconverter
JPH01114082A (en) Photodetector
JPS61270879A (en) Modulation-doped photo detector
JPS5987878A (en) Avalanche photo diode

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term