JPS61288457A - Manufacture of multilayer semiconductor device - Google Patents

Abstract

PURPOSE:To contrive the improvement in integration by forming active elements in a semiconductor layer and passive elements in an insulator layer mainly among the side planes of a multilayer semiconductor chip and by connecting those so as to eliminate the necessity of individually providing an intermediate connection circuit for connecting the chips organically. CONSTITUTION:Elements 2 are formed on one side of a semiconductor wafer 1 and another side of this semiconductor wafer 1 is polished to reduce the thickness. Two of such wafers and a conductive film 3 of silver paste or the like are bonded mutually to form a set 4 of the semiconductor wafers 1. Then, plural sets of such semiconductor wafer 1 sets 4 are bonded to form a wafer laminated body 6 comprising the sets of multilayer semiconductor devices. This wafer laminated body 6 is sliced by each set of multilayer semiconductor device to form a multilayer semiconductor device chip 7. Next the side plane of this multilayer semiconductor device chip is polished to expose the plane where the semiconductor layer 1, the conductive film 3, another semiconductor layer 1, and an insulator layer 5 are arranged in this order with a stripe form. In the semiconductor layer 1 of this stripe form plane, active elements 9 are formed mainly. In the insulator layer 5 of the stripe form plane, passive elements 10 are formed and these passive elements 10, said active elements 9 and other wiring 11 are connected with one another.

Description

[Detailed Description of the Invention] [Summary] For the purpose of realizing a three-dimensional integrated circuit, the thickness of a semiconductor wafer on which a plurality of integrated circuits are formed is reduced, and silver paste or the like is used to make them preferable. connect their back surfaces to each other to form a pair of integrated circuits made up of two layers of integrated circuits, stack these sets of integrated circuits, and bond them together with an adhesive or the like mainly composed of silicon dioxide. This is an improvement of a method for manufacturing a multilayer semiconductor device in which a multilayer semiconductor device chip is formed by dividing each integrated circuit into slices. one chip) and a conductive film (
For example, a silver paste layer), a semiconductor layer (the other chip), and an insulating layer (for example, a stack of films mainly composed of silicon dioxide formed by curing a passivation film and an adhesive) are exposed in this order. The striped surface is exposed, active elements are formed on the semiconductor layer of this striped surface, and passive elements are formed on the insulating layer, and these elements are connected to organically connect each semiconductor device chip. However, this is a method for manufacturing a multilayer semiconductor device that functions as an integrated circuit integrated with these cars.

[Industrial application field]

The present invention relates to an improvement in a method for manufacturing a multilayer semiconductor device.

In particular, the present invention relates to improvements in circuits that organically connect layers constituting a multilayer semiconductor device.

[Conventional technology]

Improvements in the degree of integration of integrated circuits have traditionally been achieved by improving the two-dimensional degree of integration by making patterns finer, and by improving printed circuit board mounting technology. Since there are limits to this, a stacked package type multilayer semiconductor device was developed. As shown in FIG. 8, after packaging integrated circuit chips, these packages 20 are stacked to produce a stacked package integrated circuit 21, and then each integrated circuit chip is connected to other semiconductor device chips (intermediate connections). 0,1 In the stacked package type multilayer semiconductor device according to the prior art mentioned above, packages are stacked.
The actual dimensions (height) were quite large, and the contribution to improving the degree of integration could not be said to be extremely significant. Moreover, the disadvantage of requiring an intermediate connection chip was unavoidable.

Therefore, the inventor of the present application has developed a method for manufacturing a stacked chip type multilayer semiconductor device in which integrated circuit chips themselves are stacked, and has already filed a patent application (Japanese Patent Application No. 59-Ei0943).
issue).

As shown in FIG. 9, a plurality of elements 2 are formed on one surface of a semiconductor wafer l, wiring is also formed to form a plurality of integrated circuits, and after the integrated circuits are completed, the plurality of integrated circuits are The other side of the semiconductor wafer l formed therein is polished to reduce the thickness to about 50 to 70 g+s, and the back side of these integrated circuits is polished through a conductive plate 3 such as silver paste. The two layers of integrated circuits are pasted together to form a pair of integrated circuits 4, and these integrated circuit sets 4 are laminated using an adhesive (for example, Fujitsu's silicon dioxide-based adhesive). Broth, etc.) to produce a wafer/\laminate 6 containing a set of multilayer integrated circuits, which is then sliced to form a multilayer semiconductor device chip, and then electrode wiring 11 between each layer. It is something that does.

A multilayer semiconductor device having this structure has a remarkable effect in reducing its dimensions, especially its height, and improving its degree of integration.

[Problem that the invention seeks to solve]

However, the multilayer semiconductor device having the above structure is similar to the above case in that it requires an intermediate connection circuit for organically coupling each chip, and there remains room for further improvement.

An object of the present invention is to eliminate this drawback, and in the method for manufacturing the above-mentioned stacked chip type multilayer semiconductor device,
The present invention provides an improved intermediate connection circuit for organically coupling each chip.

[Means for solving problems]

As shown in FIG. 1, the present invention is a method for manufacturing a stacked chip type multilayer semiconductor device, in which an element 2 is formed on one side of a semiconductor wafer 1, and the other side of the semiconductor wafer 1 is polished. The thickness of 1 is reduced, and two semiconductor wafers 1 with reduced thickness are bonded to each other using a conductive film 3 such as silver paste to form a semiconductor wafer/\1.
A set 4 of semiconductor wafers 1 is formed, a plurality of sets 4 of semiconductor wafers 1 are bonded together to form a wafer stack 6 containing a set of multilayer semiconductor devices, and this wafer stack 6 is attached to the multilayer semiconductor device set 4. After forming a multilayer semiconductor device chip 7 by slicing each group, the side surfaces of the multilayer semiconductor device chip 7 are polished to coat the semiconductor layer 1 (one semiconductor wafer 1) and the conductive film 3 (silver paste, etc.). A semiconductor layer 1 (the other semiconductor wafer l), and an insulating layer 5 (for example, a stack of films mainly made of silicon dioxide formed by curing a passivation film and an adhesive) are juxtaposed in this order. A striped surface is exposed, an active element 9 is mainly formed on the semiconductor layer l on this striped surface, a passive element lO is formed on the insulating layer 5 on this striped surface, and the passive element 10 and It is characterized in that the active element 9 and other wiring 11 are connected.

Then, connection electrode pads 12 are formed on the striped surface,
A connecting semiconductor chip 14 manufactured in advance to be connected to the striped surface is connected to the connecting electrode pad 12;
By including a step of fixing the connecting semiconductor chip 14 so that the electrode pads 13 coincide with each other, the process can be simplified.

Furthermore, if a step of forming a semiconductor layer 17 on the striped surface and forming a circuit 18 connected to the circuit formed in the multilayer semiconductor device chip 7 on this semiconductor layer 17 is included, reliability is improved. Contributes to sexual improvement.

[Effect]

The present invention, in the above-mentioned stacked chip type multilayer semiconductor device, effectively utilizes the side surface of the multilayer semiconductor chip, which was rarely used in the past. By forming passive elements on the insulating layer and connecting these elements, it is no longer necessary to provide a separate intermediate connection circuit for organically connecting each chip.

〔Example〕

Hereinafter, a method for manufacturing a multilayer semiconductor device according to a third embodiment of the present invention will be further described with reference to the drawings.

Milk±1 Referring to FIG. 2, an integrated circuit consisting of a combination of elements 2 is formed on the upper surface of a semiconductor wafer l. At this time, it is necessary to form connection terminals with circuits to be formed on the side surfaces in a later step at the boundaries of each integrated circuit, that is, in regions to be sliced in a later step. In addition, in the T-method below, slice 1. Tatoki rl
It is desirable to select the crystal orientation so that the oO) plane appears.

Refer to Figure 3. Polish the back side of the semiconductor wafer l to a thickness of 50 to 70 J.
After the semiconductor wafers 1 are reduced to about Lm, the back surfaces of these semiconductor wafers 1 are made to face each other and bonded using, for example, silver paste. For example, this silver paste becomes a conductive plate-like body 3 after being pasted, and two semiconductor wafers 1 are fixed to each other to form a set 4 of semiconductor wafers. It is well known that in these two steps it is necessary to support the semiconductor wafer 1 in a lapping machine or press using a thermoplastic adhesive such as Picene.

Refer to FIG. 4. A plurality of sets 4 are bonded to the semiconductor wafer. This process is
Similar to the above, one side of the set 4 of semiconductor wafers is adhered to the press using a thermoplastic adhesive such as picene, and the other side is attached to the press using an adhesive mainly composed of silicon dioxide (pros manufactured by Fujitsu), etc. Glue them together using In other words, the adhesive is sandwiched between two sets of semiconductor wafers 4 and pressed together.

After the bonding of the two sets is completed, a partial region is heated to melt the thermoplastic adhesive on the side bonded to one of the presses, and the next set 4 of semiconductor wafers is laminated and bonded. After curing, the adhesive becomes an insulating layer 5 mainly composed of silicon dioxide. Through this step, a wafer stack 6 containing a multilayered set of semiconductor devices is formed.

Refer to FIG. 1. The wafer stack 6 containing a set of multilayer semiconductor devices is sliced into each set of multilayer semiconductor devices, that is, into each circuit group that will be made into an integrated circuit in a later process. A device chip 7 is formed.

Through this step, the side surface of the multilayer semiconductor device chip 7 is exposed, and the connection terminals 8 described with reference to FIG. 2 are exposed. If the crystal orientation is selected in this way, the (100) plane will be exposed.

When the side surface of the multilayer semiconductor device chip 7 is polished, a striped surface appears in which the semiconductor layer 1, the conductor layer 3, the semiconductor layer 1, and the insulator layer 5 are arranged in a striped manner in this order.

Active elements 9, such as transistors and diodes, are mainly formed on the striped semiconductor layer 1.

On the other hand, passive elements IO such as resistors and capacitors are formed in the insulating layer 5. Furthermore, this passive element is fabricated at the stage of manufacturing an integrated circuit consisting of a combination of elements 2, and placed inside and under the insulating layer 5, and an extraction electrode is brought out as shown in FIG. 12 to further extend this electrode. Wiring on the side also means roaring. It is of course free to form the passive element 1o on the semiconductor layer l. C1 This step needs to be a low temperature process. Otherwise, the already completed device will be destroyed.

Here, a supplementary explanation will be given with reference to the drawings regarding a method for forming an integrated circuit formed by combining the above-mentioned elements 2.

Refer to FIG. 10. A device 2 is formed on a semiconductor wafer 1, an insulating layer 5 such as broth or silicon dioxide is formed, a resistive material layer such as TaN is formed, and this is patterned to form a resistor 19. do.

Refer to FIG. 11. Furthermore, after forming an insulating layer 5, this is patterned.
After selectively forming the electrodes 20, an insulating layer 5 is formed to form the counter electrode 21 of the capacitor.

Refer to FIG. 12 Through the above steps, the circuit shown in FIG. 12 is formed.

See Figure 13 A living room film 22 made of an insulating material layer such as PROS is formed.

Note that 8 shown in the figure is an embedded type connection terminal, and the fifth
It is the same as 8 shown in FIG.

The unit of the multilayer semiconductor device according to the present invention is as described above with reference to FIGS. 10 to 13.

Finally, wiring 11 is applied to the active element 9 and passive element 10 formed on the side surface.

The multilayer integrated circuit manufactured using the above process makes effective use of aspects that were rarely used in the conventional technology, and includes intermediate connection circuits to organically connect each chip. Since the need for separate and independent installation is eliminated, the degree of integration is improved, and the signal transmission distance is shortened.
Furthermore, since the parasitic capacitance is small, there are also effects such as improving the @ signal transmission speed.

Milk 1 Refer to FIG. 5 In the process described above, the multilayer semiconductor device, chip 7
After polishing the side surface, a connection electrode pad 12 is provided on the exposed connection terminal 8.

On the other hand, a connection electrode pad 13 is provided so as to be connectable to the above-mentioned side surface and to be connected to the above-mentioned connection electrode pad 12, and a connection in which a circuit that can organically connect the circuits of each chip is formed in advance. semiconductor auxiliary chip 14 (in the above embodiment, the active element 9 and passive element lO2 wiring 11 formed on the side surface of the multilayer semiconductor device chip 7 are formed in advance by a low-temperature process). A semiconductor auxiliary chip 14) is prepared in advance and fixed so that the electrode pads 12, 13 are connected.

The multilayer integrated circuit manufactured using the above process has not only a simple process but also excellent characteristics of each element that makes up the connection circuit, since the connection semiconductor chip is prepared in advance. It is possible to improve the characteristics.

Refer to FIG. 6 In this embodiment, the process may be changed somewhat as follows: After forming the wafer stack 6 containing a set of multilayer semiconductor devices and before removing it from the support 15. It is sliced using a number of cutters, the connecting semiconductor auxiliary chip assembly 1B is inserted and bonded thereto, and then sliced in the right angle direction. This further simplifies the process.

Refer to FIG. 7 In the step described above, after polishing the side surface of the multilayer semiconductor device chip 7, a polycrystalline semiconductor layer or an amorphous semiconductor layer 17 is formed on this side surface, and this polycrystalline semiconductor layer or amorphous semiconductor layer 17 is for forming the above-mentioned connection circuit.

In this embodiment, all steps must be performed at a low temperature process, and it is necessary to connect to the terminal 8 later using a through hole, etc., but reliability is improved because the connection circuit is integrated. .

〔Effect of the invention〕

As explained above, according to the present invention, in a stacked chip type multilayer semiconductor device, the side surface of the multilayer semiconductor chip, which was rarely used in the past, is effectively utilized. Mainly, active elements and passive elements are formed on the insulator layer, and these are connected, so there is no need to separately provide an intermediate connection circuit to organically connect each chip, and the integration level is improved. has further improved. Furthermore, since the signal transmission distance is short and the parasitic capacitance is also small, the signal transmission speed is improved.

In the above explanation, the set of semiconductor wafers is supposed to be bonded back side to back side through a conductive film, but if this is done, the ground electrode cannot be taken out from the conductive film. It has the advantage of being able to However, it goes without saying that the back surface of the upper wafer and the front surface of the lower wafer may be attached via a conductive film.

[Brief explanation of the drawing]

FIG. 1 relates to the present invention. 1 is a side view of a multilayer integrated circuit manufactured by implementing a method for manufacturing a multilayer semiconductor device. 2 to 4 are side views after completing the main steps of the method for manufacturing a multilayer semiconductor device according to an embodiment of the present invention. FIG. 5 is a process explanatory diagram of a method for manufacturing a multilayer semiconductor device according to another embodiment of the present invention. FIG. 6 is a process explanatory diagram of modification of the embodiment shown in FIG. 5. FIG. 7 is a process explanatory diagram of a method for manufacturing a multilayer semiconductor device according to a third embodiment of the present invention. FIG. 8 is a configuration diagram of a stacked package type multilayer semiconductor device according to the prior art. FIG. 9 is a configuration diagram of a stacked chip type multilayer semiconductor device according to the prior art. FIGS. 10 to 13 are process and circuit diagrams illustrating a method for forming an integrated circuit formed by combining elements. l...Semiconductor wafer, 2...Element 1.3
... conductive film (silver paste), 4. assembly into semiconductor wafers, 5. insulator layer, 6. wafer stack containing a multilayer semiconductor device assembly, 7. multilayer semiconductor device chip, 8... connection terminal, 9...
Active element, lO--Passive element, 11... Wiring,
12.13... Connection electrode pad, 14... Semiconductor auxiliary chip for connection, 15... Support body, 16...
- Semiconductor auxiliary chip assembly for connection, 17... Polycrystalline semiconductor layer or amorphous semiconductor layer, 1st... Circuit formed in multilayer semiconductor device chip, 19...
Resistor, 2o...electrode, 21...counter electrode of capacitor, agent: Patent attorney Hiroshi Matsuoka, Yo""-3
'-(Kyōgo) 13th R'f-Geki 2nd figure 3rd figure, ft area 4th figure, Shokoroku figure 5y4r JljJ, i4th branch 6th mouth 3P good 4j' 1 Fig. 7 Kiimoto Mokusho No. 8 Flash t Wood Attack Fig. 9 Fig. 2 Post-mortem Fig. 10 Artwork 4; Figure 12: Artificial Crime Figure 13

Claims (1)

[Claims] [1] An element (2) is formed on one surface of a semiconductor wafer (1), and two semiconductor wafers (1) on which the element (2) is formed are coated with a conductive film (3). the semiconductor wafers (1) to form a set (4) of the semiconductor wafers (1);
) are bonded together to form a wafer stack (6) containing a multilayer semiconductor device set, and the wafer stack (6) is sliced into each of the multilayer semiconductor device sets. to form a multilayer semiconductor device chip (7), and polish the side surfaces of the multilayer semiconductor device chip (7) to form a semiconductor layer (1), a conductive film (3), a semiconductor layer (1), and an insulating layer ( 5) are arranged side by side in this order to expose a striped surface, and the semiconductor layer (1) on the striped surface mainly contains active elements (9).
a passive element (10) is formed on the insulating layer (5) on the striped surface, and the passive element (10) is connected to the active element (9) and other wiring (11). 1. A method of manufacturing a multilayer semiconductor device, the method comprising the steps of: [2] Form a connection electrode pad (12) on the striped surface, and attach a connecting semiconductor auxiliary chip (14) manufactured in advance so as to be connected to the striped surface to the connection electrode pad (12).
12) and the electrode pad (13) of the connection semiconductor auxiliary chip (14) are fixed together so that they are aligned with each other. [3] Forming a semiconductor layer (17) on the striped surface, and forming a circuit (18) in the semiconductor layer (17) to connect to the circuit formed in the multilayer semiconductor device chip (7). A method for manufacturing a multilayer semiconductor device according to claim 1, characterized in that the method includes: