JPS61288434A - Mounting process of bare chip - Google Patents

Mounting process of bare chip

Info

Publication number
JPS61288434A
JPS61288434A JP60130247A JP13024785A JPS61288434A JP S61288434 A JPS61288434 A JP S61288434A JP 60130247 A JP60130247 A JP 60130247A JP 13024785 A JP13024785 A JP 13024785A JP S61288434 A JPS61288434 A JP S61288434A
Authority
JP
Japan
Prior art keywords
bare chip
substrate
recess
mounting
recession
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60130247A
Other languages
Japanese (ja)
Inventor
Isao Shibata
柴田　勲夫
Yoshinori Arao
荒尾　義範
Yasuo Iguchi
泰男 井口
Masao Ikehata
池端　昌夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP60130247A priority Critical patent/JPS61288434A/en
Publication of JPS61288434A publication Critical patent/JPS61288434A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To mount a bare chip easily with high reliability by a method wherein the bare chip is positioned to be fixed so that the bare chip may come flush with the surface of a substrate abutting against the inner wall of a recession provided in the region where the bare chip is to be mounted. CONSTITUTION:A recession 13 with the same thickness as that of a bare chip 15 as well as the larger configuration size is formed by proper means in the region on the surface of a substrate 11 where the bare chip 15 is to be mounted. Firstly the bare chip 15 is mounted in the recession 13 so that connecting terminals 17 provided on the surface of substrate 11 may be opposed to circuit terminal parts 19 provided on the substrate 11. Secondly the substrate 11 and the bare chip 15 are die-bonded to each other while making a side of the bare chip 15 abut against the inner wall of recession 13 so that the connecting terminals 17 may approach to the circuit terminal parts 19. Finally the region spanning the connecting terminals 17 and the circuit terminal parts 19 is coated with conductive resion 21 and then heat-treated to finish the mounting of the bare chip 15 on the substrate 11.

Description

【発明の詳細な説明】 （産業上の利用分野） この発明はベアチップを基板に実装する方法、特に導電
性樹脂を用いてベアチップを基板に実装する方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for mounting a bare chip on a substrate, and particularly to a method for mounting a bare chip on a substrate using a conductive resin.

（従来の技術） 従来より、基板へベアチップを実装するための種々の実
装方法が提案されている。この方法は例えば文献（工業
調査会「厚膜ＩＣ化技術」（１９８３年１２月）ｐ、１
４４）に開示されている。(Prior Art) Various mounting methods have been proposed for mounting a bare chip onto a substrate. This method is described, for example, in the literature (Kogyo Kenkyukai "Thick film IC technology" (December 1983) p. 1
44).

このような実装方法ではベアチップの接続端子と基板に
設けられた回路との接続はワイヤ、テープキャリア等を
用いて行われている。これらの方法の中でワイヤポンデ
ィング法による実装方法は、ベアチップの交換、接続端
子の配置の変更或いは基板に設けられた回路の変更に伴
なうポンディング位置の変更は、ポンディング装置のソ
フトウェアの変更作業のみで行うことが出来るため、将
来に渡ってベアチップの実装方法として最も用いられる
方法と思われる。In such mounting methods, the connection terminals of the bare chip and the circuits provided on the substrate are connected using wires, tape carriers, or the like. Among these methods, the wire bonding method is used to replace bare chips, change the arrangement of connection terminals, or change the bonding position due to changes in the circuit provided on the board using the software of the bonding device. This method is likely to be the most used method for mounting bare chips in the future, as it can be done by simply changing the process.

（発明が解決しようする問題点） しかしながら、ワイヤポンディング法においては、ポン
ディング時に用いるワイヤが非常に細いため機械的強度
が小さいので、ベアチップの接続端子と基板の接続端子
（以下、回路端子部と称する）との間を渡っているワイ
ヤに外部からの力が加わると、このワイヤが変形し、そ
のため隣接するワ、イヤ同士がショートしてしまうとい
う問題点があった。又、ワイヤに加わる外力が大きい場
合は、ワイヤが切断されて回路がオープン状態となって
しまうという問題点があった。しかも上述したようなワ
イヤの変形や切断を防止するためにはワイヤポンディン
グを行った後、これらのワイヤを保護及び固定する目的
でワイヤを樹脂コートする工程が必要であった。(Problems to be Solved by the Invention) However, in the wire bonding method, the wire used during bonding is very thin and has low mechanical strength. When an external force is applied to the wire passing between the two wires, the wire deforms, causing a short circuit between adjacent wires and ears. Furthermore, if a large external force is applied to the wire, there is a problem in that the wire is cut and the circuit becomes open. Furthermore, in order to prevent the wires from being deformed or cut as described above, it is necessary to perform a step of coating the wires with a resin for the purpose of protecting and fixing the wires after wire bonding.

この発明の目的は、ベアチップの接続端子と基板の回路
端子部との接続を導電性樹脂により行うことにより、簡
易に行えかつ信頼性良く行えるベアチップの実装方法を
提供することにある。An object of the present invention is to provide a method for mounting a bare chip that can be easily and reliably performed by connecting the connection terminals of the bare chip and the circuit terminal portion of the board using a conductive resin.

（問題点を解決するための手段） この目的の達成を図るため、この発明によれば、ベアチ
ップを基板に実装するに当り、基板表面のベアチップ実
装予定領域にベアチップの厚みと同一の、基板面との高
低差を有する凹部を設ける。この凹部にベアチップを載
置した後、この凹部の内壁面にこのベアチップの側面を
接触させ、かつ、この基板表面とベアチップ表面とが同
一面位置となるようにこのベアチップを位置決め固定す
る。次に、このベアチップとこの基板とにそれぞれ設け
られた接続端子の間を導電性樹脂で接続することを特徴
とする。(Means for Solving the Problems) In order to achieve this object, according to the present invention, when mounting a bare chip on a board, a portion of the board surface having the same thickness as the bare chip is placed on the area where the bare chip is to be mounted on the board surface. Provide a recess with a height difference between the two. After placing the bare chip in the recess, the bare chip is positioned and fixed so that the side surface of the bare chip is brought into contact with the inner wall surface of the recess, and the surface of the substrate and the surface of the bare chip are flush with each other. Next, the bare chip and the connection terminals provided on the substrate are connected using a conductive resin.

この発明の実施に当って、ベアチップの位置決　　　　
−め固定をベアチップの側面を凹部の内壁面に突き当て
ながらダイボンディングして行うのが好適である。In carrying out this invention, the bare chip positioning
It is preferable that the bare chip be fixed by die bonding while abutting the side surface of the bare chip against the inner wall surface of the recess.

さらに、この発明の実施に当って、導電性樹脂の供給を
スクリーン印刷法又はペン書き法で行うのが好適である
。Further, in carrying out the present invention, it is preferable to supply the conductive resin by a screen printing method or a pen-writing method.

（作用） このような構成によれば、基板面と凹部の底面との高低
差が、ベアチップの厚みと等しいので基板表面とベアチ
ップ表面とが同一面位置となり、しかも、基板表面に設
けた凹部の内壁面とベアチップの側面とが接触する。従
って、基板表面とベアチップとの間には、基板表面に設
けた回路とベアチップの接続端子との接続のために導電
性樹脂を塗布することの障害となるような段差及び間隙
が生じることはない。(Function) According to such a configuration, the height difference between the substrate surface and the bottom surface of the recess is equal to the thickness of the bare chip, so the substrate surface and the bare chip surface are in the same plane position, and moreover, the height difference between the substrate surface and the bottom surface of the recess is equal to the thickness of the bare chip. The inner wall surface and the side surface of the bare chip come into contact. Therefore, there will be no steps or gaps between the substrate surface and the bare chip that would impede the application of conductive resin for connection between the circuit provided on the substrate surface and the connection terminals of the bare chip. .

（実施例） 以下、図面を参照してこの発明の実施例につき説明する
。(Embodiments) Hereinafter, embodiments of the present invention will be described with reference to the drawings.

尚、これら図において同一の構成成分については同一の
符号を付して示しである。又、これら図はこの発明が理
解出来る程度に概略的に示しであるにすぎず、各構成成
分の寸法、形状及び配置関係は図示例に限定されるもの
ではない。In these figures, the same components are designated by the same reference numerals. Further, these drawings are only schematic representations to the extent that the present invention can be understood, and the dimensions, shapes, and arrangement relationships of each component are not limited to the illustrated examples.

第１図はこの発明のベアチップの実装方法の一実施例を
説明するため、ベアチップ及び基板の配置関係を示した
平面図である。又、第２図は第１図のＡ−Ａ線における
断面図である。FIG. 1 is a plan view showing the arrangement relationship between a bare chip and a substrate, in order to explain an embodiment of the bare chip mounting method of the present invention. Further, FIG. 2 is a sectional view taken along the line A--A in FIG. 1.

先ず、基板１１の表面のベアチップ実装予定領域にベア
チップ１５の厚さと同じ高低差すなわち深さを有しその
開口面積がベアチップ１５の外形寸法より大きい凹部１
３を好適な手段により形成する。次に、ベアチップ１５
のこの場合表面に設けである接続端子１７が、基板１１
上に設けた回路端子部１９と対向するように、ベアチッ
プ１５をこの凹部１３内に載置する０次に、接続端子１
７と回路端子部１９とが近接するようにこのベアチップ
１５の側面を凹部１３の内壁面に当接させながら、基板
１１とベアチップ１５とをダイボンディングする。この
ようにすれば、基板１１の表面とベアチップ１５の表面
とは同一面位置となる。続いて、接続端子１７及び回路
端子部１９上にまたがって、スクリーン印刷法、ペン書
き法又はその他の適当な方法により導電性樹脂２１を塗
布する。その後、この導電性樹脂２１を指定の温度で指
定の時間熱処理を行い硬化させ、ベアチップ１５の基板
１１への実装が終了する。First, a recess 1 is formed in the area where the bare chip is to be mounted on the surface of the substrate 11, which has the same height difference or depth as the thickness of the bare chip 15, and whose opening area is larger than the external dimensions of the bare chip 15.
3 by any suitable means. Next, bare chip 15
In this case, the connection terminal 17 provided on the surface of the substrate 11
The bare chip 15 is placed in this recess 13 so as to face the circuit terminal part 19 provided above.
The substrate 11 and the bare chip 15 are die-bonded while bringing the side surface of the bare chip 15 into contact with the inner wall surface of the recess 13 so that the bare chip 7 and the circuit terminal portion 19 are brought close to each other. In this way, the surface of the substrate 11 and the surface of the bare chip 15 are at the same level. Subsequently, conductive resin 21 is applied over the connection terminals 17 and circuit terminal portions 19 by screen printing, pen-writing, or other suitable methods. Thereafter, this conductive resin 21 is cured by heat treatment at a specified temperature for a specified time, and the mounting of the bare chip 15 on the substrate 11 is completed.

上述した実施例では基板１１に設けた凹部の開口面積を
ベアチップの外形寸法より大きく、かつ、ベアチップ１
５の側面と凹部１３の内壁面とが互いに一面同士で当接
させた例で説明したが、この発明の方法はこの例のみに
限定されるものではない。In the embodiment described above, the opening area of the recess provided in the substrate 11 is larger than the external dimensions of the bare chip, and the bare chip 1
Although the example in which the side surface of the recess 5 and the inner wall surface of the recess 13 are in contact with each other surface-to-surface has been described, the method of the present invention is not limited to this example.

例えば、第３図に示すように凹部１３のコーナ一部分に
ベアチップ１５のコーナーを当接させて、ベアチップ１
５の側面と凹部１３の内壁面とがそれぞれ二つの面同士
で当接するようにしても良い。この場合は、接続端子部
１７と回路端子部１９との接続は、ベアチップ！５と凹
部１３の周辺の基板とが接する二つの接続面領域を利用
できる。又、同様にしてベアチップ１５の側面と凹部！
３の内壁面とがそれぞれ三つの面同士で当接するように
して、！１ｃ続端子部１７と回路端子部１９との接続を
ベアチップ１５と凹部１３の周辺の基板とが接する三つ
の接続面領域を利用しても良い。For example, as shown in FIG.
5 and the inner wall surface of the recess 13 may be in contact with each other. In this case, the connection between the connection terminal section 17 and the circuit terminal section 19 is made using a bare chip! Two connection surface regions where the substrate 5 and the substrate around the recess 13 are in contact can be used. Also, in the same way, the sides and recesses of the bare chip 15!
Make sure that the inner wall surfaces of No. 3 and 3 are in contact with each other, and! The connection between the 1c connection terminal portion 17 and the circuit terminal portion 19 may be made using three connection surface areas where the bare chip 15 and the substrate around the recess 13 are in contact.

又、第４図に示すように凹部１３の開口面積をベアチッ
プ１５の外形寸法と同じ大きさとし、ベアチップ１５を
凹部１３に嵌合させるようにしても良い、この場合、ベ
アチップ１５の外周部の適所に多数設けた接続端子１７
と、凹部１３の周囲の基板上に多数設けた回路端子部１
８とを導電性樹脂を介して接続することが出来る。Further, as shown in FIG. 4, the opening area of the recess 13 may be made the same size as the external dimensions of the bare chip 15, and the bare chip 15 may be fitted into the recess 13. A large number of connection terminals 17 are provided on the
and a large number of circuit terminal portions 1 provided on the board around the recess 13.
8 can be connected via conductive resin.

ここで、基板１１上に設ける凹部１３は、くぼみ、溝、
段差のことを意味し、それぞれ基板面との高低差はベア
チップの厚みと同じにする。この場合にもこの発明のベ
アチップの実装方法の効果を達成出来る。Here, the recess 13 provided on the substrate 11 is a depression, a groove,
This refers to a step, and the difference in height from the substrate surface is the same as the thickness of the bare chip. In this case as well, the effects of the bare chip mounting method of the present invention can be achieved.

（発明の効果） 上述した説明からも明らかなように、この発明のベアチ
ップの実装方法によれば、導電性樹脂により基板に設け
た回路端子部とベアチップの接続端子とを接続する。従
って、従来のような細いワイヤを用いて回路端子部と接
続端子とを接続する実装方法と比較して、接続個所の機
械的強度に優れその接続個所の信頼性は非常に高く、当
然のことながら、ワイヤに樹脂コートを行うための工程
も必要ない。(Effects of the Invention) As is clear from the above description, according to the bare chip mounting method of the present invention, the circuit terminal portion provided on the substrate and the connection terminal of the bare chip are connected using a conductive resin. Therefore, compared to the conventional mounting method of connecting circuit terminals and connection terminals using thin wires, the mechanical strength of the connection points is excellent and the reliability of the connection points is extremely high. However, there is no need for a process to coat the wire with resin.

又、ベアチップの位置決め固定をベアチップのし 側面を凹部の内壁面に突き当てながら、かつ、ベアチッ
プ表面と基板表面とが同一面位置となるようダイポンデ
ィングして行うため、ベアチップの側面と凹部の内壁面
との間には段差及び間隙が出来ることがない。従って、
スクリーン印刷法により導電性樹脂の塗布が行えるので
、一度に必要とする全ての接続個所に接続のための導電
性樹脂の塗布が出来る。このため、ワイヤポンディング
法により基板に設けた回路端子部とベアチップの接続端
子とを一ケ所毎に接続することと比較して、短時間に接
続作業が行える。In addition, the bare chip is positioned and fixed by pressing the side surface of the bare chip against the inner wall surface of the recess and by die-bonding so that the surface of the bare chip and the surface of the substrate are flush with each other. No steps or gaps will be created between the wall and the wall. Therefore,
Since the conductive resin can be applied by screen printing, the conductive resin can be applied to all the required connection points at once. Therefore, the connection work can be completed in a shorter time than when the circuit terminals provided on the board and the connection terminals of the bare chip are connected one by one using the wire bonding method.

又、この方法に用いる設備はワイヤポンディングで用い
る設備と比較しその設備費が安価である。Furthermore, the equipment used in this method is less expensive than the equipment used in wire bonding.

これがため、簡易で、かつ、信頼性に優れたベアチップ
の実装方法が提供出来る。Therefore, it is possible to provide a bare chip mounting method that is simple and highly reliable.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの発明のベアチップの実装方法の一実施例を
説明するため、ベアチップ及び基板の配置関係を示した
平面図、 第２図は第１図のＡ−Ａ線における断面図、第３図及び
第４図はこの発明の他の実施例を説明するための線図で
ある。 １１・・・基板、　　　　　　１３・・・凹部１５・・
・ベアチップ、　　　１７・・・接続端子１９・・・回
路端子部、　　　２１・・・導電性樹脂。 特許出願人　　　　沖電気工業株式会社“〜・テ゛し・
′ ｌＩ：幕板　　　　　Ｉｑ；回語感芹Ｐ１３：凹卸　　
　　　２１：些箇脂 １５：ベアテνデ ＩＴ棉軽螺子 ごめ号−日月２＝ｅ３ベアチップの賓裟７３？、のｖ！
、哨の第１図 擬１図のＡ−Ａ菊１；あ寸ト酢内ロ 第２図 こめ臂ζ別の他のｆＩＪ！方ｅ汐ツの富愛明国第３図 第４図1 is a plan view showing the arrangement relationship between a bare chip and a substrate in order to explain an embodiment of the bare chip mounting method of the present invention; FIG. 2 is a sectional view taken along line A-A in FIG. 1; FIG. 4 is a diagram for explaining another embodiment of the present invention. 11... Substrate, 13... Recessed part 15...
- Bare chip, 17... Connection terminal 19... Circuit terminal portion, 21... Conductive resin. Patent applicant: Oki Electric Industry Co., Ltd.
′ lI: Makuban Iq; P13: Indentation
21: Shokka fat 15: Beate ν de IT cotton light screw gome issue - Sun Moon 2 = e3 Bear chip's guest 73? , no v!
, A-A chrysanthemum 1 in Fig. 1 pseudo-1 of the watch; Azu Tozuuchi Ro Fig. 2 Kome arm ζ other fIJ! Figure 3 Figure 4

Claims (3)

【特許請求の範囲】[Claims] （１）ベアチップを基板に実装するに当り、基板表面の
ベアチップ実装予定領域に凹部を設け、 該凹部の内壁面に該ベアチップの側面を接触させ、かつ
、該基板表面とベアチップ表面とが同一面位置となるよ
うに位置決め固定し、 該ベアチップと該基板とにそれぞれ設けられた接続端子
間を導電性樹脂で接続すること を特徴とするベアチップの実装方法。(1) When mounting a bare chip on a board, a recess is provided in the area where the bare chip is to be mounted on the surface of the board, the side surface of the bare chip is brought into contact with the inner wall surface of the recess, and the surface of the board and the surface of the bare chip are flush with each other. 1. A method for mounting a bare chip, comprising: positioning and fixing the bare chip in the desired position, and connecting connection terminals provided on the bare chip and the substrate using a conductive resin. （２）ベアチップの位置決め固定をベアチップの側面を
凹部の内壁面に突き当てながらダイボンディングして行
うことを特徴とする特許請求の範囲第１項記載のベアチ
ップの実装方法。(2) The bare chip mounting method according to claim 1, wherein the bare chip is positioned and fixed by die bonding while the side surface of the bare chip is abutted against the inner wall surface of the recess. （３）導電性樹脂の供給をスクリーン印刷法又はペン書
き法で行うことを特徴とする特許請求の範囲第１項記載
のベアチップの実装方法。(3) The bare chip mounting method according to claim 1, wherein the conductive resin is supplied by a screen printing method or a pen writing method.
JP60130247A 1985-06-15 1985-06-15 Mounting process of bare chip Pending JPS61288434A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60130247A JPS61288434A (en) 1985-06-15 1985-06-15 Mounting process of bare chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60130247A JPS61288434A (en) 1985-06-15 1985-06-15 Mounting process of bare chip

Publications (1)

Publication Number Publication Date
JPS61288434A true JPS61288434A (en) 1986-12-18

Family

ID=15029661

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60130247A Pending JPS61288434A (en) 1985-06-15 1985-06-15 Mounting process of bare chip

Country Status (1)

Country Link
JP (1) JPS61288434A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012178448A (en) * 2011-02-25 2012-09-13 Fujitsu Ltd Semiconductor device and manufacturing method of the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012178448A (en) * 2011-02-25 2012-09-13 Fujitsu Ltd Semiconductor device and manufacturing method of the same

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