JPS61285769A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent deterioration in withstanding voltage due to pattern deviation, by arranging and forming source and drain electrodes at the inner side of an ion implanted operating layer, and gradually expanding the interval between the source and drain electrodes outward in the vicinity of the input/output part of a gate electrode. CONSTITUTION:Source and drain electrodes 2 and 4 are formed at the inner side of an ion implanted operating layer 5. The interval between the source and drain electrodes 2 and 4 is gradually expanded outward in the vicinity of the input/output part of a gate electrode 3a. The distance (d) between the inner side of the boundary of the ion implanted operating layer 5 and the source and drain electrodes 2 and 4 can be d=3mum, when mask aligning accuracy is + or -1.5mum. This value is larger than ordinary mask aligning accuracy. Even if mask alignment is deviated, the basic configuration of the element itself is not changed, and stable performance is obtained in this electrode arrangement. The reason why the electrodes are gradually expanded outward in the vicinity of the input/output part is to avoid concentration of the electric field at the electrode pattern corner.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to semiconductor devices, and in particular to sources and gates of FET parts in GaAs, FETs, and MMICs.

Reduction of reverse leakage current between drain and gate.

This relates to improvements in device structure to improve pressure resistance.

[Conventional technology]

Generally GaAs. FET is the only transistor that can be used in the microwave band, and is used in microwave communications.

It is widely used in other fields, and this G
Research and development of semiconductor integrated circuits (GaAs ICs) using aAs' and FETs as active elements has progressed further as high-speed devices and high-frequency devices, and some have already reached the stage of practical use.
sIC is an IC in the microwave band, so MM
IC (Microwave Monolithic I)
It is called G).

This is a conventional example of Ga with this type of brainer structure.
1s, the basic electrode arrangement of the FET is shown in FIG.

That is, in the configuration shown in FIG. 3, numeral 1 represents GaAs.
It is a semi-insulating substrate, and 2 is a source electrode, 3 is a gate electrode pad, and 4 is a drain electrode. The gate electrode 3a extending from the gate electrode pad 3 is formed passing between the source and drain electrodes 2.4, and may have a slightly thicker portion 3h formed at its end.

As shown in FIGS. 4(a) to 4d), the GaAs FET manufacturing process first involves ion implantation into a substrate 1 to form active layers such as source and drain regions.
, and then source and drain electrodes 2 and 4 are formed. For forming each of these electrodes, for example, A
A common method is to deposit a metal material such as u, Ge, or Ni, form a pattern by a lift-off method, etc., and then heat treat it to make it into an ohmic contact mode. The interval sentences in between are usually set to about 1, for example, about 4. Subsequently, the intermediate portions of the source and drain electrodes 2.4 are slightly dug, a metal material such as AIL is used in this portion, and the gate electrode 3a extending from the gate electrode pad 3 and the tip thereof are formed using a lift-off method or the like. Thus, a portion 3b is formed.

[Problem that the invention seeks to solve]

However, in GaAs, FE↑9, which is configured in this way, for example, especially in high-output transistors, the higher the voltage resistance between the source and the gate and between the drain and the gate, the better the operation can be expected. Several means have already been proposed in the past as parameters of the device structure for improving the pressure resistance, but here we will examine means for improving the electrode shape.

FIG. 5 shows an enlarged view of the shape of the arrow 7 in FIG. 3, and the portion indicated by the dotted line is the boundary of the ion implantation region. That is, impurity ions are implanted into the left side of the boundary to form the operation M5 as described above, and the right side is not implanted with such ions and forms a semi-insulating G.
The substrate 1 of aAsJl is left in the middle.

In a device configuration using such an electrode shape,
Gate electrode 3a and source electrode 2 or drain electrode 4
When a reverse bias is applied and the breakdown voltage is measured, the breakdown voltage value may be abnormally low, resulting in the problem that the device cannot obtain sufficient electrical characteristics.

After examining the cause of this in detail, we found that
In equipment devices that are actually used, the shapes of these electrodes are not necessarily formed as shown in FIG. It turns out that this is because the structure is formed as shown in (d). In other words, the same figure (a)
(b) shows the opposite case, and (C) and (d) show the case where the ion implantation operation layer 5 is formed biased toward the source and drain electrodes 2.4. This is a case where the electrode 3a is formed biased toward the source electrode 2 side or the drain electrode 4 side, and furthermore, these cases may occur in combination. Misalignment of the electrode pattern arrangement causes a decrease in breakdown voltage in the semiconductor device described above.

Therefore, it is an object of the present invention to provide a semiconductor device in which the drop in breakdown voltage caused by pattern misalignment as described above is improved.

[Means for solving problems]

In order to achieve the above object, a semiconductor device according to the present invention has source and drain electrodes arranged and formed inside the ion implantation operation layer, and the interval between the source and drain electrodes is set near the entrance and exit of the gate electrode. It gradually expanded outward.

[For production]

That is, in this invention, the source and drain electrodes are formed inside the ion-implanted active layer, and the spacing between the source and drain electrodes is shaped to gradually expand outward near the entrance and exit of the gate electrode. Therefore, it is possible to stabilize the device performance regardless of the misalignment of the mask, and at the same time, it is possible to effectively improve the device breakdown voltage.

〔Example〕

Hereinafter, different embodiments of the semiconductor device according to the present invention will be described in detail with reference to FIGS. 1 and 2.

Figures 1 and 2 are 1. FIG. 5 is an explanatory plan view corresponding to the conventional example in FIG. 5 when the second embodiment is applied;
In each of these figures, the same reference numerals indicate the same or corresponding parts.

In the first embodiment shown in FIG. 1, the source and drain electrodes 2.4 are formed inside the ion implantation operation layer 5, and the gate electrode 3a is arranged with respect to the spacing between the source and drain electrodes 2.4. It is designed to gradually expand outward near the entrance/exit.

Here, the amount d of the source and drain electrodes 2 and 4 from the inside of the boundary of the ion-implanted active layer 5, which is one of the important points, is larger than the normal mask alignment accuracy.For example, if the mask alignment accuracy is ± If it is 1.51Lm, then d
-3p weight (does not necessarily have to be twice), and with this electrode arrangement, even if the mask alignment is misaligned, the basic form of the element itself does not change, and stable performance can be obtained. The reason why the source and drain electrodes 2.4 are formed inside the ion implantation operation layer 5 in this way is that when comparing the arrangement states of FIGS. 4(a) and 4(b), the arrangement shown in FIG. This is based on the fact that the withstand voltage is higher and the performance is more stable.

Also, the other point is the source.

The reason why the distance between the drain electrodes 2.4 is gradually widened outward near the entrance and exit of the gate electrode 3a is to avoid electric field concentration at a part of the electrode pattern corner, especially as shown in FIG. The effect is large when the gate electrode 3a is located biased toward either the source or drain electrodes 2 or 4, as shown in c) and (d). As in the first embodiment shown, the source,
Drain electrode 2.4 with rounded corner part pattern 2
a, 4a.

In addition to using a rounded pattern as described above, it is also possible to use straight-cut corner patterns 2b and 4b as in the second embodiment shown in FIG. It is sufficient to gradually expand outward near the entrance and exit of the gate electrode 3a.

〔Effect of the invention〕

As described in detail above, according to the present invention, the active layer is made of planar structure formed by ion implantation.
In the case of semiconductor devices such as As and FETs, source and drain electrodes are formed inside the ion implantation operation layer,
In addition, the spacing between the source and drain electrodes is arranged so that it gradually expands outward near the entrance and exit of the gate electrode, making it possible to stabilize the device performance, and also improve the device breakdown voltage and the electrical power of this type of device. This method has the advantage of being able to significantly improve the physical characteristics and uniformity thereof, increasing the manufacturing yield, and being extremely easy to implement since it is only a simple change in the settings of the electrode pattern.

[Brief explanation of the drawing]

FIGS. 1 and 2 show a first diagram of a semiconductor device according to the present invention.
FIG. 3 is an explanatory plan view showing an outline of each electrode pattern arrangement for the active layer in the second embodiment, and FIG. 3 is an explanatory plan view showing an outline of each electrode pattern arrangement of a general semiconductor device. Figures (a) to d) are shown in Figure 3 IV.
5 is an explanatory plan view showing the arrangement of each electrode at the arrow V section in FIG. 3, and FIG. 6 (a) to d)
FIG. 5 is an explanatory plan view showing the actual state of each electrode arrangement configuration in FIG. 5. FIG. l...GaAs semi-insulating substrate, 2...source electrode, 2a...partial corner pattern of the source electrode,
3...Gate electrode pad, 3a...Gate electrode, 4...Drain electrode, 4a...Partial corner pattern of the drain electrode, 5...Ion implantation operation layer. Agent Masuo Oiwa Figure 4 Figure 5 Figure 6 (Q) Figure 6

Claims (1)

[Claims] GaAs.The active layer has a planar structure formed by ion implantation. In semiconductor devices such as FETs, the source and drain electrodes are formed inside the ion-implanted active layer, and the distance between the source and drain electrodes is gradually expanded outward near the entrance and exit of the gate electrode. Characteristic semiconductor devices.