JPH08236757A - Ldmos device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a p-channel LDMOS device which can be manufactured with an n-channel LDMOS device in an effective VLSI process forming complementary laterally doubly diffused metal oxide semiconductor(LDMOS) devices. SOLUTION: A p-channel LDMOS device 10 with an intermediate breakdown voltage and low Rsp is provided with a high voltage (n-) N well 38, a low voltage (n+) N well 44 forming the back gate of a transistor, a pair of low voltage (p+) P wells 42 forming the drain area of the transistor, a p+ window source region 62 formed in the well 44 and an n+ back gate contact 66 formed in the well 44 through the window region of the well 44. A channel region is formed between the edge part of the region 62 and the wells. 42. A gate 58 is extended onto the channel region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a medium voltage LDMOS (lateral double-diffused metal oxide semiconductor) device.

[0002]

Due to its performance advantages, LDMOS (lateral double diffused MOS) devices are rapidly becoming bipolar devices as power devices in power ICs such as terminals having an information processing function. It is taking over.
With the ever-increasing variety of applications for power ICs, devices with a wide breakdown voltage (BVdss) are desired. However, the LDMOS device currently used in the VLSI process has a medium voltage (40 to 60) suitable for the LDMOS device having a small specific resistance (R _sp ).
V) VLSI cannot be used, so high breakdown voltage (60
~ 80V).

[0003]

Accordingly, there is a need for LDMOS devices with medium breakdown voltage and low R _sp . Generally, in one form of the invention, the transistor is
A semiconductor layer having a first conductivity and a high-voltage well formed on a surface of the semiconductor layer, the high-voltage well having a second conductivity opposite to the first conductivity; A low voltage well having an impurity concentration of 1 and formed on the surface of the high voltage well and having the second conductivity, the low voltage well being higher than the first impurity concentration. Second
A pair of low voltage wells having the first conductivity and formed on the surface of the high voltage well, and between the pair of low voltage wells. The first low-voltage well having conductivity is formed, and the pair of low-voltage wells forms a drain region and is formed on a surface of the low-voltage well having second conductivity.
A source region having a conductivity of, a channel region is formed between the source region and the pair of low voltage wells having the first conductivity, and a gate extending above the channel region, At least one back gate contact region formed on the surface of the low voltage well having the second conductivity, and a pair of drain contact regions having the first conductivity, the drain contact region Each is formed on an associated surface of the pair of low voltage wells having the first conductivity.

An advantage of the present invention is that it provides a transistor with a medium breakdown voltage BV and low R _sp that can be manufactured in an effective VLSI process without additional process cost. Another advantage of the present invention is the complementary LDM
In an effective VLSI process that forms an OS device, n
It is to provide a p-channel LDMOS device that can be manufactured with a -channel LDMOS device.

[0005]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows an LDMOS according to the present invention.
FIG. 6 is an arrangement plan view showing a photomask plane used when manufacturing the transistor 10. The photomask planes will be described in the order in which they will be used. As shown in FIG. 1, a high voltage N-well mask 12 is used to expose regions 13 of p-type epitaxial layer 14 where an n-type implant is performed to form a high voltage (n-) N-well or tank. It
Regions outside region 13 are protected by high voltage N-well mask 12 during implantation. Low voltage (n +) to expose region 22 of N well region 13 where n-type implant is performed to form a N well or tank.
+) N-well mask 20 is used. Regions outside region 22 are protected by low voltage N-well mask 20 during implantation. P-well mask 16 exposes regions 18a, 18b of N-well region 13 where p-type implantation is performed to form a low voltage P-well mask or tank.
A mask 26 protects regions 26a-26c as the field oxide is grown by exposing regions other than regions 26a-26c to form thick and thin regions of oxide. When the polysilicon gate mask 28 forms the gate of the LDMOS transistor during gate etching,
The polysilicon is protected in the region 30 while exposing the polysilicon in the region other than the region 30. An n + back gate contact mask 36 protects the rest of the device during the n-type implant performed to form the n + back gate contact regions, leaving regions 34a-34c.
To expose. The p + source / drain contact mask 32 protects the regions 34a-34c while exposing the regions outside the regions 34a-34c during the p-type implant performed to form the p + source / drain contact regions.

FIGS. 2-10 are cross-sectional views taken along line 9-9 of FIG. 1, which show the LDM at successive stages in manufacturing.
The OS transistor 10 is shown. LDMOS
The manufacture of transistor 10 is described in US Pat. No. 5,242,8.
It is compatible with the VLSI process described in U.S. Pat. No. 41, thus allowing the LDMOS transistor 10 to be fabricated on the same chip as the device described in US Pat. No. 5,242,841. US Patent No. 5,24
The flow of the process described in No. 2,841 is shown in FIG. Referring to FIG. 2, in manufacturing the LDMOS transistor 10, first, p + on the p + substrate 11 is performed.
-Starting with the formation of the epitaxial layer 14 (step 102 in figure 12). Then, an oxide layer (not shown) is formed on the p-epitaxial layer 14. A nitride layer (not shown) is formed on the oxide layer, and a window exposure region 13 (see FIG. 1) is formed on the surface of the epitaxial layer 14, so that a high voltage N well mask 12 (see FIG.
Patterning) and etching. Then, to form a high voltage N well 38, an n
Type impurities with an energy of about 80 KeV to about 4.0E
An amount of 12 atoms / cm ² is implanted from the window into the region 13 of the p-epitaxial layer 14 (step 103 in FIG. 12). The oxide and nitride layers are then removed, for example by plasma etching. Then, a drive-in step is performed to diffuse the high voltage N well 38 (step 105 in FIG. 12), and the structure of FIG. 2 is obtained. The N well 38 is a well of low concentration (n-) and high diffusion.

Then, on the surface of the epitaxial layer 14,
An oxide layer 40 about 300 angstroms thick is deposited and grown. The photoresist layer 2 is formed on the oxide layer 40.
0a is deposited, patterned using a low voltage N-well mask 20 (see FIG. 1) and etched to expose region 22 on the surface of N-well 38. Then, an n-type impurity such as phosphorus is added to form the low voltage N well 44.
Approximately 8.0E12 atoms / cm ² at an energy of approximately 80 KeV
Is injected into the region 18 of the N well 38 (step 106 in FIG. 12) to obtain the structure of FIG. The photoresist layer 2 is then formed, for example by wet etching.
0a is removed, a photoresist layer 16a is deposited on the oxide layer 40, patterned using the P-well mask 16 and etched to form a region 18 on the surface of the N-well 38.
Exposing a and 18b. Then, the low voltage P-well 42
To form a p-type impurity such as boron to about 4
It is implanted into the regions 18a and 18b of the N-well 38 at a dose of about 2.5E12 atoms / cm ² with an energy of 0 KeV (FIG. 12).
In step 108), the structure shown in FIG. 4 is obtained. Then, the photoresist layer 16a is removed by, for example, wet etching. 80 at 1100 ° C
The drive-in step is performed for a minute to diffuse the low voltage N well 44 and the low voltage P well 42 deeper into the N well 38 (step 110 in FIG. 12). Then, the oxide layer 40 is removed.

A pad oxide layer 50 is formed on the surface of the p-type epitaxial layer 14 and on the N-well 38 to a thickness of about 400 Å. An LPCVD nitride layer 52 of approximately 1400 Å thick is formed on the pad oxide layer 50. A photoresist layer 26 ₁ is deposited on the nitride layer 52, patterned using a mask 26 and etched (see FIG. 1). Then region 26
nitride layer 52 using photoresist layer 26 ₁ as a mask to cover a-26c and expose N-well 38 and regions 26d-26g on the surface of epitaxial layer 14.
Is patterned and etched to obtain the structure shown in FIG. The width c of the opening in the nitride layer 52 exposing the regions 26e, 26f is chosen to be very narrow, preferably such that photolithography is possible. For a 1.04 micron process, the width c is also preferably 1.04 micron. The photoresist layer 26 ₁ is then removed, and the photoresist layer 27 is evaporated, patterned and etched to expose areas where any p-type channel stop implants will be made. In order to form the channel stop region 29 indicated by the + sign, a p-type impurity such as boron is added at an energy of about 30 KeV to about 3.0.
An amount of E13 atoms / cm ² is implanted from the region 27a of the p-type epitaxial layer 14 (step 11 in FIG.
3), the structure shown in FIG. 6 is obtained.

Then, the photoresist layer 27 is removed, and the field oxide regions 5 are formed on the exposed portions 26d to 26g.
4a to 54d are thermally grown (step 1 in FIG.
12), the structure shown in FIG. 7 is obtained. Field oxide region 54
The thickness of a and 54d is, for example, about 7600 angstroms. Since the opening of the nitride layer 52 exposing the regions 26e and 26f of FIG. 5 is narrower than the opening exposing the regions 26d and 26g of FIG. 5, the field oxide regions 54b and 54c are the field oxide regions. 54a, 5
It is thinner than 4d. The pad oxide layer 50 and nitride layer 52 are then removed, for example by plasma etching. Then, adjacent field oxide regions 54a-5
Gate oxide layer 56 on the surface of N-well 38 between 4d.
To a thickness of about 500 Å (Fig. 12
At 116). Then, an arbitrary blanket p-type threshold value adjustment V _t may be injected (step 118 in FIG. 12). Then, over the gate oxide layer 56 and the field oxide regions 54a-54d, about 4
A 500 Å thick polysilicon layer is deposited and doped with impurities such as phosphorus to render it conductive.
A photoresist layer 28a is deposited on the polysilicon layer, patterned using the gate mask 28 and etched (see FIG. 1). The polysilicon layer is then etched using the photoresist layer 28a as a mask to form the annular gate 58 (step 12 of FIG. 12).
2), the structure shown in FIG. 8 is obtained. The gate 58 extends above the field regions 54b and 54c.

Next, the photoresist layer 28a is removed. A photoresist layer 36a is formed over the device and patterned and etched using an n + drain / source contact mask 36 to expose regions 34a-34c while protecting the rest of the device (see FIG. 1). Then, an n-type impurity such as phosphorous having an energy of about 80 KeV and about 4.0E14 atoms / cm ² and an n-type impurity such as arsenic having an energy of about 120 KeV suitable for forming the source / drain regions are formed. About 5.0E15at
oms / cm ² implantation, n + back gate contact region 6
6 is formed (step 126 in FIG. 12), and the structure shown in FIG. 9 is obtained. Then, the photoresist layer 36a is removed and n
+ Anneal the back gate contact region 66.
Then, a photoresist layer 32a is formed on the device,
Pattern and etch using p + back gate contact mask 32, which protects regions 34a-34c (see FIG. 1). Then, about 25 p-type impurities, such as boron, suitable for forming the source / drain regions are formed.
Implanting at a dose of about 2.0E15 atoms / cm ² with KeV energy to form p + source region 62 and p + drain contact region 64 (step 126 in FIG. 12),
The structure is shown in FIG. At this point in the process, the p + source region 62 is continuous in the region between the n + back gate contact regions 66, as shown in FIG. 11, which is a cross-sectional view taken along line 10-10 of FIG. . p + source region 62 with a plurality of n + back gate contact regions 66 extending through the window of p + source region 62
The use of a .. provides efficient contact with the low voltage N-well 44 and reduces the distance between the gates 58 that protects the area.

Next, the photoresist layer 32a is removed.
Source region 62 and drain contact region 64
Anneal. p + source region 62, p + drain
Contact region 64 and n + back gate contact
To contact the area 66, use conventional techniques to
Contact holes and metal contacts (not shown).
12) are formed (steps 128, 130, 1 in FIG. 12).
32, 134). n + back gate contact region 66
And p + source region 62 are typical of power IC applications.
Connect by a single metal contact (not shown)
May be. Transistor 10 includes low voltage P-well 42
Drift region consisting of channel stop region 29
With RESURF (reduced surface field) LDMO
S device. Channel stop area is in the field
Self-aligned with oxide regions 54b and 54c
And thus the pitch of the device, and thus R_sp(R_sp= R
_dson* Area) is reduced. Area components are reduced. High voltage
The pressure N well 38 is the body / channel region of the transistor.
Area, and the source-drain internal breakdown voltage BV
It has a large breakdown voltage. Forming a back gate
Therefore, the low voltage N well 44 is formed in the body region of the transistor.
(High voltage N well 38). Low voltage N well 44
The increase in channel doping provided by
While preventing short-term emissions of
Enables tunnel length. The low voltage N-well 44 is also a saw
Region 62, low voltage N well 44 and low voltage P well
Of vortex PNP transistor formed by 42
Form a low resistance path for reverse bias current that reduces
It Use of low voltage N-well 44 in high voltage N-well 38
Is also very effective Gaussian channel doping
It provides a profile and a higher breakdown voltage.

The use of field oxide regions 54b, 54c formed using the smallest feature nitride openings results in a fine pitch of transistor 10. This reduces both the resistance of the drift region and the device area which reduces R _sp (R _sp = R _dson * area). In FIG. 13, V _gs =
6 is a graph showing BV as a function of lc for several values of lp at 15V. Where lc is the distance of the low voltage N-well 42 extending under the LOCOS field oxide regions 54b, 54c and lp is the distance of the low voltage P-well to the source moat. In FIG. 14, V _gs = 15
R _sp as a function of lc for some values of lp at V
5 is a graph showing V _t and V _t . The curve S in FIG. 14 is
It shows the slope below the threshold. As can be seen from FIGS. 13 and 14, according to the present invention, the medium voltage L having a low R _sp.
A DMOS is provided. An advantage of the present invention is that it provides a medium voltage LDMOS transistor with low R _sp that is compatible with VLSI processes. The foregoing has described in detail some preferred embodiments. It should be understood that the scope of the present invention also includes embodiments different from the above description within the scope of the claims.

Although the present invention has been described with reference to the illustrated embodiments, the above description is not meant to be construed in a limiting sense. Various modifications and variations of the illustrated embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art upon reference to the above description.
Therefore, the appended claims are intended to cover such variations and modifications.

[Brief description of drawings]

FIG. 1 is a layout plan view showing a mask plane of an LDMOS transistor according to the present invention.

2 is a cross-sectional view taken along line 9-9 of FIG. 1, showing the LD of the present invention at some of its successive stages in manufacturing.
It shows a MOS transistor.

FIG. 3 is a cross-sectional view taken along line 9-9 of FIG. 1, showing the LD of the invention at some of the successive stages in manufacturing.
It shows a MOS transistor.

4 is a cross-sectional view taken along line 9-9 of FIG. 1, showing the LD of the present invention at some of its successive stages in manufacturing.
It shows a MOS transistor.

FIG. 5 is a cross-sectional view taken along line 9-9 of FIG. 1, showing the LD of the invention at some of the successive stages in manufacturing.
It shows a MOS transistor.

6 is a cross-sectional view taken along line 9-9 of FIG. 1, showing the LD of the present invention at some of its successive stages in manufacturing.
It shows a MOS transistor.

7 is a cross-sectional view taken along line 9-9 of FIG. 1, showing the LD of the invention at some of the successive stages in manufacturing.
It shows a MOS transistor.

8 is a cross-sectional view taken along line 9-9 of FIG. 1, showing the LD of the invention at some of the successive stages in manufacturing.
It shows a MOS transistor.

FIG. 9 is a cross-sectional view taken along line 9-9 of FIG. 1, showing the LD of the invention at some of the successive stages in manufacturing.
It shows a MOS transistor.

10 is a cross-sectional view taken along line 9-9 of FIG.
The L of the present invention at some of the successive stages in manufacturing
3 shows a DMOS transistor.

11 is a cross-sectional view taken along line 10-10 of FIG. 1, showing an LDMOS transistor of the present invention at a manufacturing stage similar to that of FIG.

12 is a flow diagram of a VLSI process used to fabricate the LDMOS transistor shown in FIGS.

FIG. 13 B of the LDMOS transistor of the present invention
5 is a graph showing V as a function of lc.

FIG. 14 shows R of the LDMOS transistor of the present invention.
₃ is a graph showing _sp and V _t as a function of lc.

[Explanation of symbols]

 10 LDMOS Device 38 High Voltage N Well 38a Channel Region 42 Low Voltage P Well 44 Low Voltage N Well 58 Gate 62 Source Region

Claims (1)

[Claims] 1. A semiconductor layer having a first conductivity, and a high voltage well formed on a surface of the semiconductor layer and having a second conductivity opposite to the first conductivity. The voltage well has a first impurity concentration and comprises a low voltage well having a second conductivity formed on a surface of the high voltage well, the low voltage well having a first impurity concentration. A pair of low voltage wells having a second impurity concentration higher than the impurity concentration and having a first conductivity formed on the surface of the high voltage well; A low voltage well having the second conductivity is formed therebetween, and the pair of low voltage wells forms a drain region, and is formed on a surface of the low voltage well having the second conductivity. A source region having the first conductivity,
A channel region is formed between the source region and the pair of low-voltage wells having the first conductivity, the gate extending above the channel region, and the low conductivity layer having the second conductivity. At least one back gate contact region formed on the surface of the voltage well, and a pair of drain contact regions having the first conductivity, the drain contact regions each having the first conductivity. A transistor formed on an associated surface of the pair of low voltage wells.