JPS61285765A - Manufacture of bipolar npn transistor - Google Patents

Abstract

PURPOSE:To make the deterioration of withstanding voltage due to punch- through phenomenon less, by forming pre-contact patterns on an emitter layer larger than the emitter layer, so that the peripheral part of the emitter layer does not become deeper than other parts and the depth of the entire emitter layer is constant. CONSTITUTION:A P-type base layer 22 is formed on an N-type silicon substrate or an N-type silicon substrate 21 as a collector comprising said substrate and an epitaxial layer on the substrate. Then an emitter diffused pattern 24 is formed on a silicon oxide film 23 on the surface of the substrate 21. Phosphorus is deposited on the surface part of the base layer 22 through the emitter diffused pattern 24 by thermal diffusion. Then wet oxidation is performed, and an N-type emitter layer 25 is formed in the base layer 22. thereafter, through an silicon oxide film 26 and the silicon oxide film 23, i.e., through the oxide film on the surface of the substrate, pre-contact patterns 27a, 27b and 27c are formed on the emitter layer 25, on the base layer 22 and on the substrate 21 by ordinary photolithgraphy processes.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a bipolar NPN transistor.

(Prior Art) FIG. 3 shows a conventional method of manufacturing a bibo, -ra NPN transistor. The figure shows the emitter photolithography process after forming the base layer and before the contact photolithography process.

In FIG. 3(a), 1 is an N-type silicon substrate as a collector consisting of an N-type silicon substrate or an epitaxial layer on the substrate. First, P-type impurities are diffused into this substrate 1 to form a base. After forming layer 2, substrate 1
A emitter diffusion pattern (opening) 4 is formed in the silicon oxide film 3 on the surface by a normal photolithography process.

Next, phosphorus is deposited on the surface of the base layer 2 through the emitter diffusion pattern 4 by thermal diffusion, followed by wet oxidation at 900° C. for about 10 to 20 minutes, as shown in FIG. As shown in b), an N-type emitter layer 5 is formed in the base layer 2.

At this time, a silicon oxide film 6 is formed on the surface of the emitter layer 5.

Next, on the silicon oxide film 6 and silicon oxide film 3,
As shown in FIG. 3C, a pre-contact pattern (opening) 7 is formed on the emitter layer 5, the space layer 2, and the base (collector layer) 1 by a normal photolithography process. This pre-contact pattern 7 is formed approximately 1 to 4 μm inward from the edge of each layer.

Next, by performing dry oxidation at 1000° C. for about 60 minutes, the depth of the emitter layer 5 is set to a predetermined depth.
The hFI of the bipolar NPN transistor is controlled to a predetermined value (usually about 50 to 200). At this time, a silicon oxide film 8 of the same thickness is formed on each blur contact putter foot portion, as shown in FIG. 3(d).

FIG. 4 shows the cross-sectional structure of the bipolar NPN transistor manufactured in this manner during operation. Here, 11 is a depletion layer formed in the pace layer 2 by a reverse bias applied between the pace and the collector, and 12 is a depletion layer formed in the collector layer (substrate 1).

(Problems to be Solved by the Invention) By the way, in the above method, as disclosed in the Proceedings of the National Conference of the Telecommunications Division of the Institute of Electronics and Communication Engineers in 1988,
When dry oxidation is performed in the process of Figure G), the emitter layer 5
The depth at the periphery is deeper than the rest. This is because even if the pre-contact pattern 7 is opened in the step shown in FIG. 3(c), the silicon oxide film 6 remains on the surface around the emitter layer 50, and the formation This is because phosphorus taken in during the wet oxidation in FIG. 3(b) diffuses into the emitter layer 5 again during the dry oxidation in FIG. 3(d).

As is generally known, when the distance between the bottom of the emitter layer 5 and the bottom of the base layer 2, that is, the base length becomes short, the depletion layer 11 shown in FIG. 4 formed in the base layer 2 comes into contact with the emitter layer 5. However, a punch-through phenomenon occurs in which the transistor no longer operates. In the transistor according to the conventional method, since the depth of the peripheral portion of the emitter layer 50 is deep, the voltage at which punch-through occurs is low, and the operating voltage range of the transistor is narrowed.

Figure 5 shows the resistivity of the n-type silicon substrate 1, which is 1.50.
Base layer 2 sheet resistance 200Ω/mouth, depth 2.2μm
hFI and BY in a transistor according to the conventional method of
The relationship of CK8 is shown. When hFE becomes 80 or more, BV
CΣS decreases. This is because the base length becomes shorter due to the deeper peripheral part of the emitter layer 5.
This is because punch-through occurs and current begins to flow to the emitter layer 5 below the normal breakdown voltage of the base layer.

In order to prevent the depth of the peripheral part of the emitter layer 5 from becoming deep, the pre-contact pattern 7 is not provided on the emitter layer 5, and in addition, with this structure, the emitter layer 5 with an optimum depth can be obtained. It is conceivable to control the dry oxidation shown in FIG. 3(d).

However, if the pre-contact pattern 7 is not provided on the emitter layer 5, the thickness of the etched silicon oxide film on the base layer 2 and collector layer (substrate 1
) Unlike the above, since the etching time is longer, there is a problem in that pattern reproducibility is reduced due to side etching.

(Means for Solving the Problems) In order to solve the above problems, the present invention forms a pre-contact pattern on the emitter layer larger than the emitter layer.

(Function) By doing this, the silicon oxide film that has absorbed phosphorus is also removed from the surface of the peripheral part of the emitter layer, so the peripheral part of the emitter layer does not become deeper compared to other parts. The entire emitter layer has a constant depth. Further, a silicon oxide film having the same thickness as on the base layer and the collector layer can be formed on the emitter layer.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing an embodiment of the present invention in the order of steps. However, this figure shows the emitter photolithography process after the formation of the paste layer and before the contact photolithography process.

In FIG. 1 (&), 21 is an N-type silicon substrate as a collector consisting of an N-type silicon substrate or the substrate and an epitaxial layer thereon.
After forming a P-type base layer 22 (poron is used as an impurity) with a sheet resistance of 200Ω and an R of about 2 μm on the substrate 1, a emitter diffusion pattern is formed on the silicon oxide film 23 on the surface of the base 21 by a normal photolithography process. (Opening) 24 is formed.

Next, phosphorus is applied to the surface of the paste layer 220 through the emitter diffusion pattern 24 at a concentration of 2 to 5 x 10"α"".
2 by heat diffusion, followed by 900'C,
By performing Couette oxidation for about 15 minutes, Fig. 1 (
As shown in b), an N-type emitter layer 25 with a depth of about 1 μm is formed in the base layer 22. At this time, emitter layer 2
A silicon oxide film 26 is formed on the surface of the silicon oxide film 50 .

Next, the silicon oxide film 26 and the silicon oxide film 23 are
That is, a pre-contact pattern (blur contact opening) 2 is formed on the oxide film on the surface of the substrate as shown in FIG.
7a, 27b, and 27c on the emitter layer 25 and the base layer 2.
2 and the base (collector layer) 21 by a normal photolithography process. Here, the base layer 22
The pre-contact patterns 27b and 27c on the rectifier layer 21 on the upper and lower substrates are formed about 1 to 4 μm inward from the edge of each layer. On the other hand, the pre-contact pattern 27ati on the emitter layer 25 has a thickness of about 1 to 4 μm i!
Spreading outside the mitta layer 25, the rimashemitsuta layer 25
Form into a large size.

Next, the hFI of the bipolar NPN transistor is controlled to a predetermined value (usually about 50 to 200) by heating the emitter layer 25 to a depth of about 1.9 μm by heating at 1000° C. for about 60 minutes. do. At this time, according to the method of this embodiment, the entire surface of the emitter layer 25 is a pre-contact pattern 27a,
Since the silicon oxide film 26 formed in the process shown in FIG. 1(b) and injected with nine phosphorus does not remain, the depth around the emitter 10 will not become deeper compared to other areas. The entire emitter layer 25 has a constant depth as shown in FIG. 1(d). Also, due to this dry oxidation, the pre-contact patterns 27m, 27b, and 27a are damaged (see FIG. 1).
As shown in d), a silicon oxide film 28 of the same thickness is formed.

(Effects of the Invention) As explained above, according to the method of the present invention, a larger pre-contact pattern is formed on the emitter layer, so the peripheral part of the emitter layer becomes deeper than other methods. Instead, the entire emitter layer has a constant depth.

Therefore, the decrease in breakdown voltage due to the punch-through phenomenon is reduced.

FIG. 2 shows the relationship between hFFj and BYCEB of a bipolar NPN transistor manufactured by the method of the present invention. According to this, hFIc =
There is no decrease in breakdown voltage at about 80%, and the original breakdown voltage of the base layer is maintained up to about -140%. Therefore, the method of the present invention can be used for manufacturing integrated circuit devices such as driver circuits that operate at high voltages.

Furthermore, according to the method of the present invention, it is possible to form a pre-Funtact pattern on the emitter layer in the same manner as on the base layer and the collector layer with the above-mentioned effects. A silicon oxide film with the same thickness can be formed.

Therefore, the contact photolithography process can be easily performed with high precision.

[Brief explanation of drawings]

(Drawings) Fig. 1 is a cross-sectional view showing an embodiment of the method for manufacturing a bipolar NPN transistor of the present invention, Fig. 2 is a characteristic diagram showing the relationship between hrg and BvCts of the transistor according to the method of the present invention, and Fig. 3 4 is a cross-sectional view showing the conventional method for manufacturing a bipolar NPN transistor, FIG. 4 is a cross-sectional view of the transistor during operation using the conventional method, and FIG. 5 is a characteristic diagram showing the relationship between hFI and BYCEB of the transistor according to the conventional method. be. 21... NW silicon IJ contact base, 22... Pa base layer, 23... silicon oxide film, 24... emitter diffusion pattern, 25... N-type emitter layer, 26...
Silicon oxide film, 27a, 27b, 27c... pre-contact pattern, 28... silicon oxide film. Figure 1 FIE (a)

Claims (1)

[Claims] After forming a P-type base layer on an N-type silicon substrate that will serve as a collector, there is a step of forming an N-type emitter layer in the P-type base layer by thermally diffusing phosphorus and subsequent wet oxidation, and then forming an N-type emitter layer on the substrate surface. A method for manufacturing a bipolar NPN transistor comprising the steps of forming a pre-contact opening in an oxide film on a substrate, an emitter layer and a base layer, and then performing heat treatment,
A method for manufacturing a bipolar NPN transistor, characterized in that a pre-contact opening on an emitter layer is provided larger than the emitter layer.