JPS61284898A - Sound-recording device - Google Patents

Abstract

PURPOSE:To make a silent part unnecessary, and to reproduce selectively an optional sound recording data by providing a memory means for storing a head address of a voice data which has been stored in a semiconductor storage means, and reading out the voice data in order from the head address which has been selected by a selecting means. CONSTITUTION:When a sound recording switch S1 is depressed, it is inputted to a sound recording control part 7, an output signal (a) is outputted, and a gate 18 and a gate 16 become on. As a result, the contents (0000) of a decimal counter 5 are set to an address counter 1, and to a memory area of a designated head address memory part 3, the contents (0000) of an address counter 2 are stored through the gate 18. When the sound recording switch S1 is being operated, the contents of the address 2 are added by '1' successively, therefore, a voice code data is stored in each memory area a voice data memory part 4 designated by the address counter 2. When the sound recording switch S1 is released, an output signal (c) is outputted, the contents of the decimal counter are added by '1' from (0000) and become (0001).

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an audio recording device capable of electronically recording audio data in a semiconductor memory and selectively reproducing them.

[Prior art and its problems]

Audio recording and reproducing devices using semiconductor memory are highly reliable because they have no mechanically operating parts, and are attracting attention because they can be made compact.

In this type of audio recording/playback device, when there is a plurality of contents to be recorded, it is difficult to record each recorded contents separately and to selectively reproduce them, that is, to find the beginning of the recording.

In order to solve this problem, it is conceivable to detect the beginning and end of each audio data by detecting silent parts, as in the case of conventional magnetic tape.

When a semiconductor memory is used, there is a problem in that the memory area is wasted.

[Purpose of the invention]

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a voice recording device capable of selectively reproducing arbitrary voice data from prerecorded recording contents.

[Key points of the invention]

In order to achieve the above object, the present invention provides a storage means for storing the start addresses of the audio data stored in the semiconductor storage means, and selects any one of the start addresses stored in the storage means. However, the audio data is read out in order from the first address selected by the selection means.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail.

FIG. 1 is a block diagram of a voice recording device according to the present invention.

This embodiment relates to a voice recording device that also has a clock function. The human analog audio signal from the microphone 21 is
Amplifier 22. After being converted into a digital audio signal by the A/D converter 24 via the low-pass filter 23, it is encoded into audio code data by the encoding circuit 25 and stored in the audio data storage section 4. The audio data storage unit 4 is, for example, 128
A RAM with a storage capacity of kilobytes, and the A/
The sampling period in the D converter 24 is 8 Kllz.
.

If the number of quantization bits is 8 bits (1 byte).

Since 8 kilobytes of voice code data is converted per second, it is possible to store 128 kilobytes/8=16 seconds worth of voice data. Next, the audio coded data stored in the audio data storage section 4 is decoded into a digital audio signal by a decoding circuit 26, converted into an analog audio signal by a D/A converter 27, and then processed by a low-pass filter 28. The signal is output from the speaker 30 via the amplifier 29. on the other hand,
A signal from the recording switch S1 is input to the recording control section 7 via the chuck prevention circuit 8. The output signal a from the recording control section 7 turns on the gate 18, and also.

The gate 16 is turned on via the OR circuit 12.

Similarly, the output signal is the recording amplifier 22,
Low pass filter 23. The A/D converter 24° and the encoding circuit 25 are activated, and the AND circuit 14. The contents of the address counter 2 are updated via the OR circuit 15 at the timing of the clock φ input to the AND circuit 14. Similarly, the output signal C updates the contents of the decimal counter 5 via the OR circuit 11. On the other hand, the signal from the regeneration switch s2 is the chuck prevention port li! The signal is input to the playback control unit 6 via &9. The output signal d from the reproduction control section 6 is as follows.

The gate 17 is turned on, and the gate 16 is also turned on via the OR circuit 12. Similarly, the output signal e is transmitted to the reproduction amplifier 29. Low pass filter 28. D/A
Converter 27. and the decoding circuit 26, and the AND circuit 13. The contents of the address counter 2 are updated via the OR circuit 15 at the timing of the clock φ input to the AND circuit 13. Further, the signal from the trunk designation switch S3 is transmitted to the chuck prevention circuit 10. OR circuit 11
The contents of decimal counter 5 are updated via . and,
The output of decimal counter 5 is transferred to address counter 1 via gate 16.

The output of the address counter 1 designates each address on the top address storage section 3 constituted by a RAM, and the designated address and the output of the address counter 2 are stored via the gate 18. Further, the output of the head address storage section 3 is transferred to the address counter 2 via the gate 17, and the output of the address counter 2 specifies each address on the audio data storage section 4. On the other hand, the contents of the decimal counter 5 are displayed on the display section 20 via the display control section 19. Also.

Reference numeral 31 denotes an oscillator, and the output of the oscillator 31 is frequency-divided by a frequency dividing circuit 32, clocked by a counter 33, and displayed as a clock on the display section 20 via the 2-display control section 19. At this time 1
The clock φ from the frequency dividing circuit 32 is supplied to the AND circuit 13.
14.

In the audio recording apparatus having the above configuration, the recording operation will first be explained using FIGS. 2(a) and (bl).

When the recording switch S1 is pressed, it is input to the recording control section 7, an output signal a is output, and the gates 18 and 16 are turned on. Due to this.

The contents of decimal count 5 (0000) are then sent to address counter 1 through gate 16.

Starting address storage section 3 specified by address counter 1
The contents of address counter 2 (0000) are stored in the storage area of
is stored via the gate 18 (FIG. 2(a)). Also, while the recording switch S5 is being operated, the output signal S is output continuously, and the amplifier 22. Low pass filter 23. A/D converter 24. and the encoding circuit 25 is activated. In addition, since the AND circuit 14 is turned on and the contents of the address counter 2 are sequentially incremented by 1 at the timing of the clock φ, the audio code data inputted from the encoding circuit 25 is transferred to the audio data storage unit 4 specified by the address counter 2. (Fig. 2 (address (0) of bl)
000) to just before address (0100)).

When the recording switch S1 is released, the output signal C is stopped and the output signal C is outputted, and the contents of the decimal counter are incremented by 1 from (0000) to (0001).

Next, when the recording switch is pressed again, the content of the decimal counter (0
001) is set in the address counter 1 via the gate 16, and the contents of the address counter 2 (0100), which is the first address of the second recording, are stored in the storage area of the first address storage section 3 specified by the address counter 1. is stored via the gate 18 (FIG. 2(a)). and,
The recording switch S1 is activated by the output signal that is subsequently output.
While pressing , the contents of the address counter 2 are sequentially incremented by 1 by the clock φ, and the second recording is made in the audio data storage unit 4 (Fig. 2(b)) at the address (01).
00) to just before (0150)), Sui Nochi S1
When is released, the content of the decimal counter is incremented by 1 by the output signal C to become (0010).

Thereafter, every time the recording switch S1 is pressed, the audio code data input from the microphone 21 is stored in the audio data storage section 4, and the start address storage section 3 stores the audio code data input from the microphone 21 at the beginning of the audio code data on the audio data storage section 4 for each switch operation. The address will be remembered.

Next, the playback operation will be explained. First, the trunk selection switch S3 is used to select the number of recorded data to be played back. At this time, by setting the decimal counter 5 to a desired value, the selection result is displayed on the time display on the display unit 20, as shown in FIG. 3, for example, and can be visually recognized.

Now, suppose we select the third recorded data as shown in Figure 3.

(0010) is entered in the decimal counter 5.

Next, when the playback switch S2 is pressed, the playback control section 6
Output signal d is output from , and gates 16 and 17 are turned on. This sets the contents of the decimal counter (0010
) is set in address counter 1 via gate 16. Then, the contents (015) of the address (0010) of the start address storage section 3 specified by the address counter 1
0) is preset in the address counter 2 via the gate 17 (see FIG. 2(a)). Further, while the regeneration switch S2 is being operated, the output signal e is continuously outputted, and the output signal e is outputted from the amplifier 29° low-pass filter 28. D/8 converter 27. and the encoding circuit 26 is activated. In addition, the AND circuit 13 is turned on and the contents of the address counter 2 are sequentially incremented by 1 from (0゛150) at the timing of the clock φ, and the voice code data is stored from each address on the voice data storage unit 4 specified thereby. is read out, sent to the decoding circuit 26, and finally the third and subsequent recording data are output from the speaker 30.

With the above operation, it becomes possible to selectively reproduce any recorded data while looking at the display section 20 with a simple switch operation.

Next, FIG. 4 is a block diagram of a second embodiment of the audio recording device according to the present invention. The difference from the embodiment shown in FIG. 1 is that the regeneration switch S2 also serves as the trunk determination switch S3 (FIG. 1). Therefore, a switch determination section 35 is provided after the chatter prevention circuit 9, and its output signal g is input to the reproduction control section 6, and the output signal f is input to the OR circuit 3.
4 to the decimal counter 5. Further, the output signal e of the reproduction control section 6 is also inputted to the decimal counter 5 via the OR circuit 34, and furthermore, the newly provided coincidence detection path 36 is activated. The match detection circuit 36 compares the output of the address counter 2 with the output of the contents of the specified address on the start address storage section 3 specified by the address counter 1.

In the audio recording apparatus configured as described above, the recording operation is exactly the same as that shown in FIG.

Next, in the playback operation, when the playback switch S2 is pressed for a short time, the switch judgment unit 35 outputs only the output signal f, and
Advances the contents of the O-address counter. That is, if the playback switch S2 is pressed for a short time.

It functions exactly the same as the 1-rank designation switch shown in FIG. Following this, when the playback switch S2 is pressed for a long time, the switch judgment section 35 outputs only the output signal g. In this case, the operation of the regeneration switch in FIG. 1 is exactly the same. In the following, as in the case of FIG. 1, the contents of the decimal counter are first set in the address counter 1 by the output signal d, and then the contents of the specified address on the start address storage section 3 specified by the address counter 1 are set. is preset in address counter 2. Then, by the subsequent output signal e, the contents of the address counter 2 are sequentially incremented by 1 starting from the preset start address.

The contents of the corresponding address in the audio data storage section 4 are read out and reproduced. However, at this time, unlike in Figure 1,
The contents of the decimal counter are further incremented by 1 by the output signal e, and the first address is written as 0 via address counter 1.
The start address value of the next recording section is sent from the section 3 to the coincidence detection circuit 36. Therefore, the playback progresses and the address counter 2
When the output becomes the start address value of the next recording part, the match detection circuit 36 outputs a match signal e, which is input to the playback control unit 6 and output of the output signal e is stopped, so playback stops at that point. .

That is, in the embodiment shown in FIG. 1, everything after the designated start address is reproduced, but in the case of FIG. 2, only the designated recording portion is reproduced. Further, in FIG. 2, there is no need to provide a track designation switch, and the device can be made more compact.

〔Effect of the invention〕

According to the present invention, it is possible to selectively reproduce any recorded data, and since silent parts are not required, memory is not wasted. Further, data selection can be performed by a simple switch operation.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a first embodiment of a voice recording device according to the present invention. FIG. 2(a) is an explanatory diagram of stored data in the head address storage section, and FIG. 2 fbl is an explanatory diagram of stored data in the audio data storage section. FIG. 3 is an explanatory diagram of display data on the display section. FIG. 4 is a block diagram of a second embodiment of the audio recording device according to the present invention. 1.2...Address counter. 3...Start address storage section. 4...Audio data storage section. 6...Reproduction control section. 7... Recording control section. 20...Display section. 24...A/D converter. 25... Encoding circuit. 26...Decoding circuit. 27...D/A converter. 35...Switch judgment section. 36... Match detection circuit. S! ...Recording switch. S2... Playback switch. S3...Track designation switch. Patent Applicant Casio Computer Co., Ltd. (a) Figure 2 Figure 3

Claims (1)

[Claims] In a voice recording device that converts voice input from the outside into voice code data and records it in a semiconductor storage means, and reproduces the voice code data recorded in the semiconductor storage means into voice, the semiconductor memory is used for each recording operation. a start address storage means for storing a start address of the voice code data stored in the means; a selection means for selecting any one of the start addresses stored in the start address storage means; 1. A voice recording device comprising: reproduction control means for reading voice code data stored in said semiconductor storage means from a selected top address and reproducing voice.