JPH05217292A - Data reproducing device - Google Patents

Abstract

PURPOSE:To smoothly reproduce a next music without an interruption equivalent to a required access time, or through a continuous or with a constant no sound period. CONSTITUTION:An access operation takes place when the data reading of a third music from a recording medium such as a disk is completed, move a pickup 2 at an eighth music during a time Ta. While reading the data of the eighth music, store the data which are read from the recording medium on a buffer memory 6 and read the data with a delay time Td which is longer than the access time Ta. During the access time Ta, the data of the previous third music from the memory 6 are read so as to keep the reproduction. Immediately after the completion of the reading of the third music or after a constant no sound period T0, the data of the eighth music are read.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data reproducing apparatus for storing data read from a recording medium in a memory, reading the data from the memory at a constant rate and reproducing the data.

[0002]

2. Description of the Related Art Generally, in a tape recorder, a disc player or the like for recording and / or reproducing a digital audio signal or a digital video signal, the recorded digital signal is digital audio data which has been subjected to error correction coding processing or interleave processing. Many have main data such as digital video data and auxiliary data such as address information and control information. For example, in a so-called compact disc (CD) format, stereo left and right two-channel audio signals are sampled at 44.1 kHz and quantized with 16 bits to produce an audio PCM signal, and a CIRC (cross.
Interleaved Reed-Solomon code) is used as main data. This main data includes information such as identification information between songs and between songs, song number (track number), elapsed time from the beginning of each song (lap time), absolute time (absolute time), emphasis control, etc. Data, so-called sub-code data, is added as recording data, and this recording data is processed by EFM (8-
14 modulation) to obtain a recording signal.

When a compact disc (CD) having such a format is reproduced by a normal reproducing apparatus, a PLL is generally used from an EFM signal read from the disc.
A clock component is detected (clock reproduction) using a (phase locked loop) configuration, binary data is taken in by the reproduced clock, and EFM signal demodulation is performed.
The data after EFM demodulation is usually RA for decoding processing.
M is used to perform error correction based on CIRC and decoding (decoding) processing including deinterleaving to obtain a digital audio signal (PCM signal). Data is written to the decoding RAM in synchronization with the PLL reproduction clock, and data is read out in synchronization with a clock from a reference oscillator such as a crystal oscillator. The digital audio PCM signal obtained by the decoding process becomes an analog audio signal via a D / A converter and a low pass filter (LPF).

[0004]

Here, in a general CD player or the like, a so-called program reproduction mode or shuffle reproduction in which each music recorded on a disc is selected or reproduced at random as desired. There are modes, but for example, if you try to play the 8th song after playing the 3rd song, the optical pickup will access the 8th song after the 3rd song is over, so there will be no sound for the required access time. As a result, the waiting time for the user of the device has been unreasonable.

Further, in intro reproduction in which only the first part of a music is reproduced one after another, or in repeat reproduction of one music, repeat reproduction of all music, etc., access to a distant position on the disk is required during reproduction, There will always be a silent wait time during this access.

On the other hand, the data reproducing apparatus, especially the above-mentioned CD
In a device such as a player equipped with an optical pickup, a servo system such as a focus servo or a tracking servo of the optical pickup may be disengaged due to mechanical disturbance such as impact or vibration on the device, and normal data reproduction may be performed. It may not be possible. In this case, it is impossible to deal with the error correction as described above, and there is a possibility that the reproduction is temporarily interrupted.

Therefore, the applicant of the present application has previously described that, in the specification and drawings of Japanese Patent Application No. 3-25566, the reproduced data is stored in a relatively large-capacity buffer RAM and is read at a constant rate. And the RAM for the buffer
By always storing a predetermined amount or more of reproduced data in the buffer, even if normal data cannot be obtained from a medium such as a disk due to a read error or the like, the buffer R
A system is proposed in which the data stored in the AM is read to compensate for interruptions in the reproduced signal such as sound breaks.

The present invention has been made in view of such a situation, and when data of a plurality of files (songs, etc.) is recorded on a medium such as a disk, a discontinuous file is recorded on the medium. It is an object of the present invention to provide a data reproducing apparatus that effectively avoids a reproduction interruption state such as a silent state due to an access time at the time of access and enables continuous and smooth reproduction.

[0009]

A data reproducing apparatus according to the present invention is a data reproducing apparatus for reading data recorded on a recording medium to reproduce the data, and the recorded data is recorded from the recording medium at a rate higher than a standard. A data reading means for reading the data, a buffer memory for storing the data read at a high speed from the recording medium, and the data reading means for the buffer memory before the stored data falls below a predetermined amount. Memory control means for reading the subsequent recording data of the recording medium and writing the same by connecting to the last written data of the buffer memory and for reading the data stored in the buffer memory at a constant rate. And a system controller for controlling the operations of the data reading unit and the memory control unit. The system control means performs an access operation on the recording medium while reading the stored data from the buffer memory, and the accessed and read data is stored in the buffer RAM. The above problem is solved by causing the last data in the data to be written continuously.

For example, for each file (for example, for each song)
When a recording medium (for example, an optical disk) on which the divided recording data is recorded is used, the system control unit causes the reading unit to read the data on the recording medium while reading the stored data from the buffer memory. The next file access operation is performed, and the data of the accessed and read file is read by the buffer R.
The memory control means is controlled so that the data of the previous file in the AM can be continuously written.

[0011]

Since the access operation of the recording medium such as the disk is performed while the data is read from the buffer memory and is actually reproduced, the reproduction is continuously performed during the access operation, and the reproduction is performed. There is no adverse effect such as interruption of.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of a device of one embodiment in which a data reproducing device according to the present invention is applied to a so-called compact disc (CD) player. That is, the optical disc 1 has a so-called C
Recorded data in D format is recorded. Briefly explaining this so-called CD format, 1
The upper and lower 8 bits of 16-word PCM digital audio data are separated into a symbol that is an error correction coding unit.
(Cross interleaved Reed-Solomon code) adds error correction parity and interleaves. A total of 32 symbols of 24 symbols of this CIRC-encoded audio data and 8 symbols of parity
Main data of symbol is one recording unit (frame)
Then, a so-called sub code, which is 8-bit auxiliary data, is added to this, so-called EFM (8-14 modulation).
By being modulated by the method and adding the frame synchronization pattern, one frame is recorded on the optical disc 1 as an EFM signal of 588 channel bits.
The sub-code is made up of one block (sub-coding frame) in 98 frames and carries auxiliary information for eight channels P to W. The Q channel of this subcode contains auxiliary data such as the song number, index number, elapsed time within the song, and absolute time.

In FIG. 1, an optical disk 1 is rotationally driven by a drive motor 18 at a speed (for example, twice the speed) higher than a standard speed (linear speed), and an optical pickup 2 intermittently or burstly outputs a signal. It is read, amplified by the preamplifier 3, and sent to the signal processing unit 4 as a so-called RF signal. This RF signal is a signal modulated by the EFM method described above, and the signal processing unit 4 performs processing such as EFM demodulation, deinterleaving, error correction, interpolation, and subcode decoding, and the main data ( Audio PCM data) output is from the RAM controller 5
It is stored in the buffer RAM 6 via. The data transfer rate up to this point is higher than the standard reproduction rate (for example, double the rate) in response to the high-speed disk rotation drive. However, the reading of data from the optical disc 1 is performed intermittently or in a so-called burst manner, and even if the instantaneous data transfer rate is higher than the standard, the average rate including the read pause period is almost standard playback. It is a rate. In this way, the data sent to and accumulated in the buffer RAM 6 intermittently or in bursts is continuously read out at a standard reproduction rate by the RAM controller 5, and the D / A converter 7, LP
By passing through an F (low-pass filter) 8, an analog audio output signal is taken out.

The servo control circuit 9 includes, for example, a focus servo, a tracking servo, a spindle motor servo,
The sled (head movement) servo and other control operations are performed. That is, the focus servo controls the focus of the optical system of the optical pickup 2 so that the focus error signal becomes 0, and the tracking servo controls the tracking of the optical system of the optical pickup 2 so that the tracking signal becomes 0. Further, the spindle motor servo controls the rotation of the spindle motor (driving motor) 18 so that the optical disc 1 is rotationally driven at a predetermined linear velocity (for example, double the standard linear velocity). Further, the sled servo controls the movement of the optical pickup 2 to the target track position of the optical disc 1 designated by the system controller 10. The servo control circuit 9 that performs such various control operations outputs information indicating the operating state of each unit controlled by the servo control circuit 9 to
It is being sent to the system controller 10.

The system controller 10 stores a CPU (central processing unit) such as a microprocessor for controlling the operation of each unit, a ROM (read only memory) in which a control program executed by this CPU is stored in advance, and various data. RAM for writing / reading and temporary storage
It is a so-called microcomputer system configured by including a (random access memory) and an I / O (input / output) circuit that transmits and receives various signals between the CPU and the outside. The system controller 10 includes a display unit 11 for displaying the operation state of each unit and a key input operation unit 12 for instructing various operations.
Etc. are connected. The display unit 11 includes, for example, an LCD
(Liquid crystal display), LED (light emitting diode) display device,
An FL display device, a plasma display device, or the like is used. The key input operation unit 12 is provided with various operation keys such as a play button, a stop button, and a fast-forward button. In addition, the system controller 10
Sends and receives signals to and from the signal processing unit 4 and the RAM controller 5 to control the operations of the signal processing unit 4 and the RAM controller 5.

Here, for example, when the servo system is disturbed by disturbance or the like and the reproduction signal is interrupted, that is, specifically, for example, a) out of focus, b) subcode Q data When it becomes discontinuous, c) when the PLL system becomes unstable for a certain period of time, d) when interpolation processing is performed (interpolation flag is raised), etc. Monitor and
The writing to the buffer RAM 6 is interrupted. And
After the servo system is restored, for example, the address immediately before the interruption of the reproduction signal is accessed, and writing is restarted from that address position. As a result, continuous reproduction output can be obtained unless the data stored in the buffer RAM 6 becomes empty. Further, even when the data stored in the buffer RAM 6 becomes full, the writing to the RAM 6 is temporarily stopped and the pause operation or the like is started.

By the way, the RF signal input to the signal processing unit 4 is synchronized with a so-called PLL system clock including uneven rotation of the optical disc 1, whereas the main data output to the RAM controller 5 is: Since it is synchronized with, for example, a so-called crystal system clock as a reference clock, jitter exists between the two. For this reason,
If the timing of starting writing to the buffer RAM 6 depends on the absolute time obtained by decoding the so-called sub-code Q data in the signal processing unit 4, a connection error such as data loss or duplication occurs. Therefore, a data comparison block is provided in the RAM controller 5, and data of the last several samples of the data written in the buffer RAM 6 and the RA from the signal processing unit 4 are stored.
The data sent from the M controller 5 to the RAM 6 are compared with each other, and the data from the signal processing unit 4 is written to the buffer RAM 6 at the timing when these data match.

That is, FIG. 2 shows a specific example of the signal processing unit 4, and FIG. 3 shows a specific example of the RAM controller 5. In FIG. 2, the RF signal from the preamplifier 3 is sent to the EFM demodulation circuit 21, the synchronization detection circuit 22 and the PLL / timing generation circuit 23, respectively. The EFM demodulation circuit 21 demodulates the RF signal modulated by the EFM system, and sends the main data signal to the data bus DB and the subcode data signal to the subcode Q processing circuit 24. The synchronization detection circuit 22 detects the sub-coding frame synchronization signal and sends it to the PLL / timing generation circuit 23. PLL / timing generation circuit 23
Detects the channel bit clock (EFM clock) component of the RF signal and locks the PLL, and
The channel bit clock is divided by using the sub-coding frame synchronization signal to generate a word clock, a bit clock of data after EFM demodulation, and the like, and a write clock WCK is read / write control circuit 27. Send to. The PLL / timing generation circuit 23 outputs a sub-coding frame synchronization signal or the like for use in, for example, a spindle servo. Subcode Q data and the like are serially output from the subcode Q processing circuit 24 and used as current position information of the optical pickup 2 on the optical disc 1.

The main data (audio data and parity data for error detection and correction) sent from the EFM demodulation circuit 21 to the data bus DB includes a PLL / timing generation circuit 23 containing a jitter component due to uneven rotation of the optical disc 1 or the like. Data is written in the decoding processing RAM 26 by the read / write control circuit 27 in synchronization with the write clock WCK from. Thereafter, while the read / write control circuit 27 controls the read / write to the decoding processing RAM 26, error detection / correction processing and deinterleave processing are performed by the error correction processing circuit 25 based on the CIRC. .. The decoding processing RAM 26 is
In addition to the capacity required for RC decoding (for example, about 108 frames), it has a capacity for allowing a predetermined (for example, ± 24 frames) margin to absorb the above jitter. For example, a 32 kbit RAM is used. Be done. The decoded main data (PCM data) has a timing generation circuit 2 including a reference oscillator such as a crystal oscillator.
In synchronization with the read clock RCK from 9, the read / write control circuit 27 reads from the decoding processing RAM 26 and sends it to the interface circuit 28. From the interface circuit 28, the decoded main data, the bit clock BCK, and the word clock W are input.
Various clocks such as DCK, LR (for switching stereo left and right channel words) clock LRCK, etc. are output, and the RAM controller 5 and the system controller 10 are output.
Etc. Here, the write / read operation is intermittently performed at a speed higher than the standard, for example, double speed.

Next, referring to FIG. 3, the signal processing circuit 4 is described.
The input data from (the interface circuit 28 of) is
16 sample PCM sent to register 31
It is stored as data, and the system controller 10
Is permitted to write data, the data is written in the buffer RAM 6 according to the write address output from the address generation circuit 34 via the data selector 32. At this time, data writing is intermittently performed at a speed faster than the standard. Data is read from the buffer RAM 6 via the data selector 32 in accordance with the read address output from the address generation circuit 34 to the register 33.
Sampling frequency (eg 44.1k
It is continuously output from the register 33 at a constant reproduction rate according to (Hz) and sent to the D / A converter 7.

Here, the buffer RAM as described above
When the writing to 6 is suspended and then the writing is resumed, that is, when data connection is performed, the address when the last data is written to the buffer RAM 6 is output from the address generation circuit 34, and the data is used for the buffer. It is taken into the register 35 from the RAM 6 via the data selector 32. This data is compared with the data input to the register 31 from the signal processing unit 4 by the data comparator 36, and when both match, a coincidence output is output to determine the timing of data connection. That is, the input data from the next signal processing unit 4 for which a coincident output is obtained may be written in the buffer RAM 6.

Next, FIG. 4 schematically shows the write / read operation for the buffer RAM 6 in the memory space, and FIG. 5 shows an example of the internal configuration of the address generation circuit 34. 4 and 5, in FIG.
When the write enable signal W-EN from the system controller 10 is sent to the write address counter 13, the write address counter 13 operates and the write address is advanced (incremented) at a speed faster than the standard. W
A is generated. Data is written in the buffer RAM 6 by the write address WA. Further, the system controller 10 or the like checks the subcode information or the like to check for skipped sounds, etc., and sends a good state signal SOK to the effective write address latch 14 if there is no problem. Effective write address latch 14 latches write address WA from write address counter 13 in response to this signal SOK, and outputs it as effective write address VWA. The stored data up to the address VWA is reproducible data with no skipped sound, and can be sent to the D / A converter 7.

The read address counter 15 operates in response to the read enable signal R-EN from the system controller 10 to advance the read address RA at the standard speed.
And the data written in the buffer RAM 6 are sequentially read. Since the step speed (write speed) of the write address WA is higher than the speed (read speed) of the step (increment) operation of the read address RA, the address WA is the address RA in the loop memory space. However, at this time, the stepping operation of the write address WA is stopped, and the writing is restarted when the read address RA advances and the remaining amount of data falls below a predetermined amount (the step of the write address WA. Restart the advancing operation). The remaining amount of data at this time indicates the amount of actually reproducible data from the valid write address VWA to the read address RA. The subtracter 16 obtains the address difference ΔA by subtracting the address RA from the address VWA.

Here, the data read from the buffer RAM 6 and sent to the D / A converter 7 and the system controller 1 obtained by the subcode Q processing circuit 24 and the like.
The time difference between the subcode time information held by 0 is the sum of the delay amount in the decoding process RAM 26 and the delay amount in the buffer RAM 6 and is the delay amount in the decoding process RAM 26. Is about ten and several msec including the above-mentioned jitter correction amount, and can be ignored in the case of time display or the like. Therefore, only the delay amount in the buffer RAM 6 is taken into consideration in the following description.

Therefore, the time difference Td between the actual reproduction data and the time information of the subcode is the address difference ΔA.
The data amount Dm corresponding to (= VWA-RA) is divided by the data read rate Dr. RAM 6 for buffer
If the number of bits of the storage unit (word) for one address is n bits, the time difference Td is as follows: Td = Dm / Dr = (n × ΔA) / Dr (1)

From the above, the system controller 1
For 0, the subcode information received from the subcode Q processing circuit 24 or the like of the signal processing unit 4 may be delayed by the time difference Td to perform control operations such as actual time display and de-emphasis switching. That is, the display unit 11
Absolute time T _ABS and elapsed time in the song (lap time) T
When displaying the _{LAP and the} like, it is _sufficient to display the values obtained by subtracting the time difference Td from the absolute time T _QABS and the in-tune time T _{QLAP and the} like obtained from the sub-code Q information, and switching control such as de-emphasis is performed. Also in the case of switching, it is possible to match the content of the reproduced audio signal by delaying and switching the time difference Td. The same applies to the display of song numbers (track numbers) and index numbers.

Further, even in a special reproduction state such as pause (pause) and re-beat between A and B, the time difference Td is taken into consideration and the control is performed so that the display, audio output and key operation are performed between the device. You can avoid giving it an unnatural feel.

For the address difference ΔA, it is not necessary to obtain all the bits of the address (for example, 20 bits).
You may make it use about several high-order bits according to the required precision. Here, as a specific example of the buffer RAM 6, the storage capacity is such that the bit number n of one word is 4 bits and the address bit number is 20 bits (A _{0 to} A ₁₉ ).
When using an M-bit memory, the upper 4 bits (A ₁₆
When to A ₁₉₎ using only becomes distinguishable accuracy 0.25M bits. The data read rate Dr is about 1.
When it is set to 4 Mbits / sec, the data amount [M bits] with respect to the value of the upper 4 bits (A _{16 to} A ₁₉ ) of the 20-bit address (A _{0 to} A ₁₉ ) representing the address difference ΔA and the time conversion amount [Second. Frame] is shown in Table 1 below.

[0029]

[Table 1]

In this case, however, an error may occur in the calculated data, and the time may return when the elapsed time of the CD is displayed. In such a case, an unnatural feeling can be prevented by using a program so that the calculated value does not decrease due to the error.

Further, the address difference ΔA is displayed on the display unit 11 by a number or a visual expression of a visual quantity so that the user of the device can know the remaining memory capacity of the buffer RAM 6 and the memory storage data quantity. Can inform,
This is useful for checking the operating status. Here, the display that expresses the visual amount is, for example, the buffer RAM 6
And a fixed display element that represents a container that reminds of
6 and a variable display element that expresses the reproducible data amount stored in the storage device 6.

Next, a so-called shuffle reproduction mode in which the music numbers (track numbers) recorded on the disc 1 are randomly replaced and reproduced will be described with reference to FIG. In FIG. 6, for example, from the third song to 8
An example of an operation of moving to a music piece and reproducing is shown.

FIG. 6A shows the data read from the disc 1, and the optical pickup 2
Starts to move after reading the data of the third music from the disk 1, finds the head position of the eighth music through the access operation of time Ta, and restarts the data reading operation. In the conventional general CD player, no reproduction sound can be produced during the time Ta of the access operation, and muting is performed to prevent noise and the like, so that there is no sound. here,
If the main data can be stored in the buffer RAM 6 so that the delay amount Td is equal to or longer than the access time Ta (Td ≧ Ta) due to the storage capacity of the buffer RAM 6, as shown in B of FIG. During the access time Ta, the main data of the previous music piece (third music piece) can be continuously reproduced. Before the reproduction of the third music is completed, the access to the next music (8th music) on the disc 1 is completed and the reading of data is started. After reading the third song from RAM6,
Immediately, the next 9th song can be read out, and continuous smooth reproduction can be performed without a silent portion as in the conventional case.

Here, the system controller 10
Controls the optical pickup 2 and the drive motor 18 to read data faster than the standard, and controls the RAM controller 5 to prohibit the writing of main data to the buffer RAM 6 during the access operation. ing. For this purpose, for example, when the RF signal from the preamplifier 3 cannot be obtained, or when the subcode data from the signal processing unit 4 cannot be obtained, the write operation may be prohibited. Then, from the time when the data of the next song (8th song) is read by the optical pickup 2 and the RF signal or the subcode data is obtained, the writing of the main data to the buffer RAM 6 is restarted.

Further, as shown in FIG. 6C, with respect to the main data read from the buffer RAM 6 and reproduced, a silent period of an appropriate time T ₀ between the end of the third music and the beginning of the eighth music. Can be provided. This can be easily realized by controlling the reading of the buffer RAM 6. Since the silent time T _{0 in} this case can be set to be constant irrespective of the actual access time Ta, it is possible to align the silent time between songs when recording on a tape, for example. It is convenient because it can be used to find the beginning of a song or search on a tape recorder. Also,
It may be easier to hear when there is a proper silence period than when songs are continuously connected. This silent time T ₀ is
It can be set to an appropriate value in consideration of the above-mentioned point, and for example, the access time Ta is prevented from being unduly long such as several seconds or more, and is set to a fixed time, for example, about 2 to 3 seconds. be able to.

Although FIG. 6 has been described with reference to the case where access is made in units of music, such as shuffle reproduction and program reproduction, repeat reproduction between A-B and
It is needless to say that the same can be realized in the case of performing access from the middle of a song to the middle of a song such as intro reproduction.

As is apparent from the above description, according to the embodiment of the present invention, it is sufficient to store the main data in the memory (RAM 6) and the memory capacity can be effectively used.
Moreover, the read main data can be controlled by the information of the write data. Further, in a reproduction mode such as shuffle reproduction in which an access operation is in the middle, it is possible to avoid silence due to access time and realize smooth reproduction with a continuous or proper silence period. Further, from the absolute time T _QABS by the sub-code Q data and the elapsed time in the song (so-called lap time) T _{QLAP, the} buffer RA
Only by subtracting the delay time Td in M6, it is possible to obtain time information with a timing coincident with the actually reproduced main data, and it is possible to perform an appropriate display. It is also possible to display the amount of reproducible data of the device to inform the operating state of the device.

The present invention is not limited to the above-mentioned embodiment, and for example, as the recording medium, other than the optical disk, a magneto-optical disk, a magnetic disk, a magnetic tape, etc. can be used, and the format is so-called. It is not limited to the CD format. In addition to PCM audio data, video data, compressed data, etc. can be used as the main data. Further, the auxiliary data is not limited to the above subcode data, and can be applied to a format in which error correction processing is not performed. Of course, the hardware configuration is not limited to the illustrated example.

[0039]

As is apparent from the above description, according to the data reproducing apparatus of the present invention, in the data reproducing apparatus which reads the data recorded on the recording medium and reproduces the data, the standard from the recording medium is used. Data reading means for reading recorded data at a higher speed than that, a buffer memory for storing the data read at high speed from the recording medium, and the stored data in the buffer memory is less than or equal to a predetermined amount. Before the data reading means reads the subsequent recording data of the recording medium and connects to the last written data of the buffer memory and writes the data, and the data stored in the buffer memory is fixed. Operation of memory control means for controlling reading at a rate, the data reading means, and the memory control means And a system control unit for controlling the system. The system control unit performs an access operation on the recording medium while reading the stored data from the buffer memory, and also accesses the read data. Since the last data in the buffer RAM is continuously written, the reproduction is continuously performed during the access operation, and there is no adverse effect such as the interruption of the reproduction.

Therefore, when the present invention is applied to, for example, a so-called CD (compact disc) player, 1-track repeat playback, all-track repeat playback, AB repeat playback, shuffle playback, intro playback, program playback, etc. Efficient and smooth reproduction can be performed by avoiding the silent period for the time required for the disk access operation and having a continuous or constant appropriate silent period.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall schematic configuration of an embodiment of a data reproducing apparatus according to the present invention.

FIG. 2 is a block circuit diagram showing a specific example of a signal processing unit in the above embodiment.

FIG. 3 is a block circuit diagram showing a specific example of a RAM controller in the above embodiment and its periphery.

FIG. 4 is a diagram for explaining movement of a write address and a read address in the memory space of the buffer RAM in the above embodiment.

5 is a block diagram showing an example of an internal configuration of an address generation circuit in FIG.

FIG. 6 is a diagram for explaining the operation of the embodiment.

[Explanation of symbols]

 1 ... Optical disc 2 ... Optical pickup 4 ... Signal processing unit 5 ... RAM controller 6 ... Buffer RAM 9 ... Servo control circuit 10 ... System controller 11 ... Display unit 12 ... Key input unit 21 ... EFM demodulation circuit 23 ... PLL / timing generation circuit 24 ... Sub-code Q processing circuit 25 ... Error correction processing circuit 26 ... Decoding processing RAM 27 ... Read / write control circuit 29 ... Timing generation circuit 31, 33 , 35 ... Register 36 ... Data comparator

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Toru Tsunono 134 Toyohama Business Park East Tower 11F Kobe Tower, Hodogaya-ku, Yokohama, Kanagawa Prefecture Sony LSI Design Co., Ltd.

Claims (1)

[Claims] 1. A data reproducing apparatus for reading data recorded on a recording medium to reproduce the data, comprising: a data reading unit for reading the recorded data from the recording medium at a rate higher than a standard; and a high-speed reading from the recording medium. A buffer memory for storing the read data, and the subsequent recording data of the recording medium is read by the data reading means before the stored data is less than or equal to a predetermined amount in the buffer memory. Memory control means for connecting and writing to the last written data of the buffer memory and controlling reading of the data stored in the buffer memory at a constant rate; operation of the data reading means and the memory control means And system control means for controlling the The access operation on the recording medium is performed while the stored data is being read from the memory for memory, and the accessed and read data is continuously written to the last data in the buffer RAM. A data reproducing device characterized by: