JPS61283934A - Control system for microprogram - Google Patents

Abstract

PURPOSE:To improve the reliability of a control system for a microprogram by using a means which shows the validity of the information stored in a control memory and therefore setting and changing easily the contents of a register and an address conversion table. CONSTITUTION:A register 1 holds some of the real addresses corresponding to the micrological addresses. A conversion table 6 is retrieved by those micrological addresses and secures some of the corresponding real addresses. An address array 4 stores the information showing whether the information within a block of a corresponding control memory 3 is valid or not and bits 0-3 of the micrological address of a microinstruction held in the block of the memory 3. Then the microinstruction which loaded the contents of the register 1 and the table 6 to the memory 3 from a main storage 7 is defined as the valid information and executed for setting. Thus the contents of the register 1 and the table 6 can be set and changed easily with no use of the complicated hardware. This improves the reliability and the degree of free designing for a control system for microprogram.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprogram control system in which a control memory executes a microprogram loaded from a main memory into a control memory.

[Conventional technology]

Conventionally, in this type of device in which a microprogram is loaded from a large-capacity memory to a high-speed control memory and executed, an address conversion table is provided that shows the correspondence between a micro logical address and a real address in the main memory. ,
A method was used in which the loading operation of microinstructions from the main memory to the control memory was controlled in units of blocks (Japanese Patent Application No. 183389/1983).

[Problem that the invention seeks to solve]

In the conventional microprogram control system described above, when the real address of the area storing the microprogram in the main memory is a large value, the number of bits required for the real address pointing to one microinstruction in the address translation table is large. There is a problem with becoming a thing. In addition, as the number of microprograms increases, the address translation table requires a larger capacity, which not only increases the cost of the address variation table but also reduces the efficiency of using the address translation table.

[Means for solving problems]

The apparatus of the present invention includes a first register holding a micro-logical address, a control memory accessed by a first partial address of the micro-logical address and comprising a plurality of blocks and holding a micro-instruction; Stores a second partial address of a micro logical address corresponding to a microinstruction accessed from a partial address of a first partial address and stored in each of the plurality of blocks of the control memory and a bit indicating its validity. a comparison means for comparing a valid output from said address array with a second partial address of a micro-logical address held in said first register; and a real address corresponding to said micro-logical address. a second register holding a first partial address of the micro-logical address; and a third partial address of the micro-logical address containing the second partial address of the micro-logical address. an address conversion cheaple for outputting the second partial address of the address; an area for storing an initial setting microprogram consisting of a series of micro instructions for initializing the system; a first partial address of the real address obtained from the second register and the address conversion table; and a second partial address.
and a load control device that loads the microinstructions from the main storage device to the control memory in units of blocks when the results of the comparison means do not match and when the output from the address array is invalid.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

A block diagram of one embodiment of the present invention is shown in FIG.

The microprogram control system in Figure 1 is register 1.
, register 2, control memory 3, and address array 4
, a comparator 5 , an address conversion table 6 , a main memory 7 , a load control device 8 , and a NAND circuit 9 .

In this embodiment, it is assumed that the microprogram consists of 16 bytes per word and has a capacity of 65,536 words, and its micro logical address consists of 16 bits. In FIG. 1, register ] is a register for holding a 16-bit micro logical address, control memory 3 is a memory consisting of 1 word of 16 bytes and has a capacity of 4,096 words, and address array 4 has 256 entries. This is a circuit with The control memory 3 is divided into 256 blocks of 16 words each, and each block corresponds to each entry of the address array 4. Bits 1-4 to 15 of register 1 are given to control memory 3 as address information, and bit 4 is given to address array 4.
~11 is given as address information. Each entry in the address array 4 contains information indicating whether the information in the corresponding block of control memory 3 is valid or not, and information indicating the micro logical address of the microinstruction held in the corresponding block of control memory 3. Pit I-0 to I-3 are stored. Comparator 5 compares bits O to 3 of register 1 with the output of address array 4, and determines whether or not the microinstruction corresponding to the micrologic address held in register 1 is held in control memory 3. To detect. A NAND circuit 9 performs a NAND operation between the output information of the comparator 5 and the output information indicating whether or not the information in the corresponding block of the control memory 3 held for each entry in the address array 4 is valid. This is a circuit that instructs. register 2 is 1
This register consists of 2 bits and is set by the execution of a microprogram that initializes the system and is held in register 1 to hold a part of the real address of the microinstruction corresponding to the micro logical address. Address conversion table 6 is composed of 256111i1 items using bits O to 7 of register 1 as index information.

The main memory 7 has an area for storing microprograms stored from address zero where system initialization is performed, and a real address 65,536 that corresponds to the micro logical address indicated by register 1 after initialization. 32 including an area for storing word microprograms.
It is accessed by a real address consisting of bits. After being stored in this main memory and not initialized, there are 256 microprograms each having a real address corresponding to the micro logical address indicated by register 1.
It is divided into groups of words, and the first real address of each group is held in the register 2 and each corresponding item of the address conversion table 6. The load control device 8 is a circuit for controlling the loading operation of microinstructions from the main storage device 7 to the control memory 3 in units of blocks. When the microinstruction corresponding to the micrologic address held in register 1 does not exist in control memory 3, first, load control device 8 instructs this, and bits O to 11 of load control device 8 are filled with the microinstruction from register 2. , bits 12 to 19 contain the pin I and bits from the address conversion table 6.
Address information is supplied from bits 8 to 11 of register 1 to bits 20 to 23, respectively, information of all zeros is given to bits 24 to 31, and the start address of the corresponding block is determined from these pieces of information. According to the obtained real address, 16 words containing the microinstruction corresponding to the contents of register 1 are read from main memory 7 and loaded into the corresponding block of control memory 3. At this time, it is simultaneously instructed to write the contents of bits 0 to 3 of register 1 to the corresponding entry of address array 4, and the information indicating whether the information in the block of control memory 3 is valid is determined to be valid. be instructed to become

Next, the operation of this embodiment will be explained in detail with respect to a specific example.

The starting real address of the area for storing a microprogram consisting of a series of microinstructions for initializing the system is "OO" in hexadecimal.

oooooo", and after initialization is performed, the starting real address of the area for storing a microprogram consisting of a series of microinstructions with a real address corresponding to the micro logical address indicated by register 1 is set in hexadecimal as "O".
O1oo 000''(°°°' indicates a hexadecimal number). Initially, register 1, register 2, control memory 3,
All information stored in the address array 4 and address translation table 6 is unknown and invalid. Therefore, all information stored in register 1, register 2, control memory 3, address array 4, and address conversion table 6 is replaced with zero by hardware.

When the load control bag N8 is activated, hexadecimal ``000'' is read from the register 2 to the output signal line 28, and hexadecimal ``00'' is read from the address conversion table 6 to the output signal line 27.
is read out, the output signal line 27 and the output signal line 28 are coupled, and hexadecimal "oooooo" is read out on the output signal line 29 and sent to the load control device 8. Load control device 8
is the upper 20 bits and is the information of the output signal line 29" o o
o o o" is output in bits 20 to 23, and the information in bits 8 to 11 of register 1 is output. The receiver adds °'00" information to bits 24 to 31, making it a real address on the main memory 7, and outputting it as a real address. Read the 16-word microinstruction from the address “ooooooooo’” and write the hexadecimal address “
This is written sequentially to addresses "000" to "OOF", and at the same time, a binary "1 (21") is written to the bit indicating whether or not the information in the corresponding block of control memory 3 of address array 4 is valid. is written ("(21" indicates a binary number). Next, hexadecimal °'000"' is supplied from register 1 to control memory 3 as an address, and hexadecimal '
The contents of the address O(') O'' are read out to the output signal line 21. At the same time, the address array 4 receives the hexadecimal address '00'.
°" is supplied, and hexadecimal "0" is read out to the output signal line 22. Also, output bits 0 to 3 of register 1 are also 1.
Since it is '0°' in hexadecimal, both inputs of comparator 5 are 1.
Because it is hexadecimal “0゛°,” the output signal line 24 has binary “°”.
] (21°° is read out. At this time, the output signal line 23 shows the binary information held by the bit indicating whether or not the information in the control memory 3 block corresponding to the entry of the address array 4 is valid. °'1 (2," is read out. The output signal line 31 is supplied with binary °0 (21
" is read out. As a result, the contents of the output signal line 21 read out from the control memory 3 become valid, and this microprogram is executed. This microprogram initializes the system, and its execution controls the Memory 3 hexadecimal address 001” ~ “OOF”
Call and execute the microprogram at the address. By executing these microprograms, hexadecimal "001" is set in the register 2 from the input signal line 25, and the real address corresponding to the micro logical address indicated by the register 1 is set in the address conversion table 6 from the input signal line 26. Information indicating a part of the block is set, and finally all bits indicating whether or not the information in the block of control memory 3 of address array 4 is valid are set to all binary □ "0 (2)". Writing from the input signal line 30 ends the execution of this microprogram.

Next, consider the case where a microinstruction sequence as shown in FIG. 2 is executed. Figure 3 shows a series of initial settings for the system, an area for storing the My20□ program consisting of Taro instructions, and a real address corresponding to the micro logical address indicated by the register after the initial settings. This figure shows an area for storing a microprogram consisting of a series of microinstructions and its real address on the main storage device.

First, hexadecimal '0200' is set in register 1.

Step 1: Write “ in hexadecimal as the address in control memory 3.
200" is supplied, and the contents of the hexadecimal address "200" are read out to the output signal line 21. At the same time, the hexadecimal address "20°" is supplied to the address array 4, and the contents of the hexadecimal address "200" are read out to the output signal line 2. A hexadecimal value of 0° is read.

Since both inputs of the comparator 5 are hexadecimal "0", a binary "1"(21") is read out to the output signal line 24. At this time, the entry in the control memory 3 corresponding to the entry in the address array 4 is read out. The binary “0 (2,”) of the information indicated by the bit indicating whether or not the information in the block is valid is read out to the output signal line 23, and the binary 1 is changed to 1.
(21''' is read.

The output signal line 3 is output from the NAND circuit 9. The contents of the output signal line 21 of the control memory 3 are then invalidated and the load control device 8 is activated. Also, '02°' in hexadecimal is supplied as an address to the address conversion table 6, and one of the real addresses on the main memory 7 in which the microinstruction corresponding to the micro logical address '0200' in hexadecimal is stored. Part "02" is read out to the output signal line 27, and part "001"' of the real address on the main memory N7 where the microinstruction held in the register 2 is stored is read out to the output signal line 28. be done. A portion of the real address on the main memory 7 in which the microinstruction corresponding to the hexadecimal micrological address "0200" is stored, combined with the contents of the output signal line 27 and the output signal line 28. " is read out to the output signal line 29 and sent to the load control device 8 together with output bits 8 to 11 (="o'") of the register 1. The load control device 8 receives the information on the output signal line 29 at the 1st 20th bit, receives the information on the output bits 8 to 11 of the register 1 using the next 4 bits, and adds "00" to the lower 8 bits. By doing this, the real address “00102 000゛” on the main storage device 7 where the microinstruction corresponding to the hexadecimal micrological address “0200” is stored is obtained, and by this real address, the hexadecimal microinstruction is stored from the main storage device 7. Read the 16-word microinstruction corresponding to the logical addresses ``0200'' to ``02OF'' and read the hexadecimal addresses ``200'' to ``20F'' in the control memory 3.
At the same time, write hexadecimal data "1" in address array 4, and write "1" in binary to the bit indicating whether the information in the block of control memory 3 is valid. (21" is written. When the above process is completed, the contents of the new hexadecimal address "200" are read out to the output signal line 21 of the control memory 3, and the contents of the new hexadecimal address "200" are written to the output signal line 22 of the address array 4. The new content "0'" of the address "20'' is read out and input to the comparator 5. Since both inputs of the comparator 5 are 0", the output signal line 24 has a binary "1 ( 21'' is read out, and binary "1, 2." is read out to the output signal line 23 from the bit indicating whether or not the information in the block of the control memory 3 corresponding to the entry of the address array 4 is valid. As a result, binary "0 (2)" is read from the NAND circuit 9 to the output signal line 31, the output signal line 21 is enabled, and the hexadecimal address of step 2 is written to the register 1. '0202' is set.

Step 2: Write “ in hexadecimal as the address in control memory 3.
202°” is supplied, and the contents of the hexadecimal address 202” are read out to the output signal line 21. At the same time, a hexadecimal address "20" is supplied to the address array 4, and a hexadecimal 0" is read to the output signal line 22.

Since the inputs of the comparator 5 are both hexadecimal 0'', a binary 1 (21'') is read on the output signal line 24, and the information in the block of the control memory 3 corresponding to the entry of the address array 4 is valid. A binary “1 (21)” is read out to the output signal line 23 from the bit indicating whether the " is read out and made valid on the output signal line 21, and the hexadecimal address of the next step is set in the register 1.

Thereafter, similar operations are repeated. Next, in step N, the address array 4 is set to address ``31'' in hexadecimal to indicate whether the information in the block of control memory 3 corresponding to this encoder is valid or not. It is assumed that binary l1 (old II) is written in the indicated bit.

Step N: From control memory 3 to hexadecimal address “31”
The contents of the address '4'' are read out to the output signal line 21. At the same time, the contents of the hexadecimal address '31', that is, hexadecimal '2', are read out from the address array 4 to the output signal line 22. Since one input of the comparator 5 is a hexadecimal value "1" and the other is a hexadecimal "2" degree, the output signal line 24 has a binary value "O(21"). Also, a binary "1 (21") is read out to the output signal line 23 from the bit indicating whether or not the information in the block of the control memory 3 corresponding to the entry of the address array 4 is valid. .

- From this, the NAND circuit 9 is connected to the output signal line 31.
Then, the binary "l", 2.I+ is read out, the contents of the output signal line 21 are invalidated, and the load control device 8 is activated.Operation after the load control device 8 is activated is the same operation as the operation after the load control device 8 is activated in step 1.

In subsequent steps, any one of the operations of step 1, step 2, and step N is performed.

In this way, in this embodiment, the contents of register 2 and the contents of the address conversion table can be changed without the need for complicated hardware, increasing the degree of freedom in setting. Despite the large value, by setting that part of register 2, the capacity of the address translation table can be reduced and its usage efficiency can be improved.

〔Effect of the invention〕

As explained above, according to the present invention, there is a register that holds a part of the real address corresponding to a micro logical address, and a register that provides a part of the real address corresponding to the micro logical address by being indexed by the micro logical address. An address translation table for the purpose of the control memory and a means for indicating the validity of the information stored in the control memory are provided, and a microinstruction that loads the register and the contents of the address translation table from the main memory into the control memory is provided with valid information. By executing this instruction, the contents of registers and address translation tables can be easily set and changed without the need for complex hardware, improving reliability and providing greater freedom in design. It has the effect of becoming. Furthermore, it is possible to freely associate micro logical addresses with real addresses on the main memory using an address translation table with the minimum necessary capacity, which increases the efficiency of address translation table use and makes it cheaper. This has the effect of realizing a microprogram control system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing an example of a microinstruction sequence, and FIG. It is a figure showing an example of correspondence. 1...Register, 2...Register, 3...Control memory, 4...Address, 5. ... Comparator, 6...
Address conversion table, 7... Main storage device, 8...
Load control device, 9...NOT/path, 21<
31...Signal line.

Claims (1)

[Scope of Claims] A first register that holds a micro-logic address; a control memory that is accessed by a first partial address of the micro-logic address and is made up of a plurality of blocks and that holds micro-instructions; Stores a second partial address of a micro logical address corresponding to a microinstruction accessed by a partial address of the first partial address and stored in each of the plurality of blocks of the control memory and a bit indicating its validity. a comparison means for comparing a valid output from said address array with a second partial address of a micro-logical address held in said first register; and a real address corresponding to said micro-logical address. the first of
a second register holding a partial address of the micro-logical address; and a second register of the real address corresponding to the micro-logical address by being indexed by a third partial address of the micro-logical address containing the second partial address of the micro-logical address. 2, an area for storing an initial setting microprogram consisting of a series of micro instructions for initializing the system;
a first portion of the real address obtained from the second register and the address conversion table; a main memory accessed by an address signal including an address and a second partial address; and a main memory accessed by an address signal including an address and a second partial address; and a main memory accessed from the control memory when the results of the comparison means do not match and when the output from the address array is invalid. A microprogram control system comprising: a load control device that loads the microinstructions in units of the blocks.