JPS61283932A - Control system for microprogram - Google Patents

Abstract

PURPOSE:To improve the application efficiency of an address conversion table by providing a register holding a part of a real address, an address conversion table and an adder which adds the addresses of said register and table together and controlling the loading operations of a main storage into an control memory for each block. CONSTITUTION:A register 1 holds a micrological address of 16 bits and a register 2 holds a part of a real address of the macroinstruction corresponding to the logical address of 20 bits and held by the register 1. An address conversion table 6 consists of 256 items using bits 0-7 of the register 1 as the retrieval information. An adder 7 adds the real addresses of the register 2 and the table 6 together. A load controller 9 controls the operation to load a microinstruction into a control memory 3 from a main storage 8 by the real address given from the adder 7. Thus it is possible to secure the correspondence between the logical and real addresses by means of the table 6 of the minimum necessary capacity.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprogram control system that executes a microprogram loaded into a control memory from a main storage device on the control memory.

[Conventional technology]

Conventionally, in this type of device in which a microprogram is loaded from a large-capacity memory to a high-speed control memory and executed, an address conversion table is provided that shows the correspondence between micro logical addresses and real addresses on the main memory. A system was used in which the loading operation of microinstructions from the main memory to the control memory I\ was controlled in units of blocks (Japanese Patent Application No. 183389/1983).

[Problem that the invention seeks to solve]

In the conventional microprogram control system described above, when the real address of the area storing the microprogram in the main memory is a large value, the number of bits required for the real address pointing to one microinstruction in the address translation table is large. There is a problem with becoming a thing. In addition, as the number of microprograms increases, the address translation table requires a larger capacity, which not only increases the cost of the address translation table but also reduces the efficiency of using the address translation table.

[Means for solving problems]

The device according to the present invention includes a first
a control memory that is accessed by a first partial address of the micro logical address and is made up of a plurality of blocks and holds micro instructions; an address array storing second partial addresses of micro logical addresses corresponding to micro instructions stored in each of a plurality of blocks of the control memory;
a second register for holding a first partial address of the real address corresponding to the micro logical address; an address conversion table that outputs a second partial address of the real address corresponding to the micro logical address by being indexed by a third partial address of the micro logical address including the second partial address of the logical address; Adding means for adding a first partial address and a second partial address of an address, and a main memory that is accessed by an address signal containing the addition result of the addition, which includes an area for storing a microprogram consisting of a series of microinstructions. and a load control device that loads the microinstructions from the main storage device to the control memory in units of blocks when the results of the comparison means do not match.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

An embodiment of the present invention is shown in FIG. The microprogram control system in FIG. 1 has register 1, register 2,
It is composed of a control memory 3, an address array 4, a comparator 5, an address conversion table 6, an adder 7, a main storage device 8, and a load control device 9.

In this embodiment, it is assumed that the microprogram consists of one word of 16 bytes, has a capacity of 65,536→-words, and its micro logical address consists of 16 bits. In FIG. 1, register 1 is a register for holding a 16-bit micro logical address, control memory 3 is a memory consisting of 1 word of 16 bytes and has a capacity of 4,096 words, and address array 4 is a memory with a capacity of 4,096 words.
This is a circuit with 2 entries. Control memory 3 is 16
Each word is divided into 256 blocks, and each block corresponds to each entry in the address array 4.

Bits 4 to 15 of register 1 are given to control memory 3 as address information, and bit 4 is given to address array 4.
~11 is given as address information. Each entry of address array 4 stores bits O-3 of the micro logical address of the micro instruction held in the corresponding block of control memory 3. Comparator 5 compares bits 0 to 3 of register 1 with the output of address array 4 and detects whether the microinstruction corresponding to the micro logical address held in register 1 is held in control memory 3. . Register 2 is a register consisting of 20 bits I and for holding a part of the real address of the microinstruction corresponding to the micro logical address held in register 1. The address conversion table 6 is composed of 256 items using the pins 1-O to 7 of the register 1 as index information.

The adder 7 adds the real address held in the register 2 and the real address given from the address conversion table 6. The main memory 8 includes an area for storing a microprogram of 65.degree. 536 words and is accessed by a real address consisting of 32 bits. The microprograms stored in the main storage device 8 are divided into groups of 256 words each, and information regarding the first real address of each group is held in the register 2 and each corresponding item of the address conversion table 6. There is. The load control device 9 is a circuit for controlling the loading operation of microinstructions from the main storage device 8 to the control memory 3 in units of blocks.

When the microinstruction corresponding to the micrological address held in register 1 does not exist in control memory 3'2, first, load control device 9 instructs this, and bits 0 to 19 of load control device 9 contain register 2. The address information obtained by adding the 20-bit information held in the address conversion table 6 and the 8-bit information given from the address conversion table 6 using the adder 7 is supplied, and the address information obtained by adding the 20-bit information held in
23 is supplied with address information from bits 8 to 11 of register 1, information of all zeros is given to bits 24 to 31, and the start address of the corresponding block is determined from these pieces of information. 16 containing the microinstruction corresponding to the contents of register 1 from main memory 8 according to the obtained real address.
The word is read and loaded into the corresponding program in control memory 3. At this time, bit O of register 1 is simultaneously applied to the corresponding entry of address array 4.
You will be instructed to write the contents of ~3.

Next, the operation of this embodiment will be described in detail with respect to a specific example of executing a microinstruction sequence as shown in FIG.

In this case, the start address of the microprogram area in the main memory 8 is hexadecimal "00098000°". FIG. 3 shows the microprogram area in the main memory 8 and its real address on the main memory 8. .In Figure 1, register 2 contains hexadecimal '0009.
8" is written in the address array 4. Also, in the address array 4, as an initial value, "0" and "
Assume that a hexadecimal value "°2°" is written at address '31'("" represents a hexadecimal number).

First, '02 (10)' is set in register 1.

Step 1: Enter hexadecimal ° as address in control memory 3.
'200' is supplied, and the contents of the hexadecimal address '200°' are read out to the output signal line 11. At the same time, the hexadecimal address '20' is supplied to the address array 4, and the contents of the hexadecimal address '200°' are read out to the output signal line 12. Hexadecimal '0'' is read.

Both inputs of comparator 5 are hexadecimal "' 0°', the output signal line 11 is Register 1 when enabled. Hex address of step 2 ゛02 02'' is set.

Step 2: 1 of control memory 3 in the same way as step 1.
The contents of the hexadecimal address "'202°" are read and validated.

Register 1 contains the hexadecimal value of step 3. The dress °’1314” is set.

Step 3: Hexadecimal address '31' from control memory 3
The contents of the 4°° address are read out to the output signal line 11. At the same time, the contents of the hexadecimal address "31", ie, hexadecimal "2", are successively output from the address array 4 to the output signal line 12. Since one input of the comparator 5 is 16 advanced '1'' and the other is 2 in hexadecimal, the contents of the output signal line 11 of the control memory 3 are invalidated, and the contents of the output signal line 11 of the control memory 3 are invalidated. In addition, the address conversion table 6 is supplied with hexadecimal "13" as an address, and the main memory 8 stores the microinstruction corresponding to the hexadecimal micro logic address "X"1300. Part of the information regarding the above real address "'10°" is read out to the output signal line 13, and part of the real address "0 0098°" at the beginning of the microprogram area held in the register 2 is output signal It is read out on line 14. The contents of this output signal line 13 and the contents of the output signal line 14 are added by the adder 7, and the result is executed in the main memory 8-1- where the microinstruction corresponding to the hexadecimal micrologic address ``1310'' is stored. Part of the address °゛00108''
° is read out to the output signal line 15 and sent to the load control device 9 along with output bits 8 to 11 (-'''1'') of the register 1. The load control device 9 receives the information of the output signal line 15 in bits 0 to 19, and adds "00'' to bits 24 to 31. Then, find the real address "00108100" on the main memory device 8 where the microinstruction corresponding to the hexadecimal micro logical address "1310" is stored, and use this address to read the hexadecimal number from the main memory device 8. At the same time, the 16-word microinstructions corresponding to the micro logical addresses "13 10" to "131F" are read out and sequentially written to the hexadecimal addresses "'3 10" to "31 F" in the control memory 3. , hexadecimal data ``'1'' held in bits 0 to 3 of data 1 at hexadecimal address ``31'' in address array 4.

Write ゛. The above process ends and to the output signal line 11 of the control memory 3. is the new hex address 314”' The contents of the address are read and the address The output signal line 12 of Ray 4 has a hexadecimal New contents of address “31” ``1'' is read and input to comparator 5 be done. The inputs of comparator 5 are both 1°, so the output signal line 11 is present. At the same time, it is set to register 1. Step 4 hex address "13" 15'' is set.

Thereafter, similar operations are repeated.

In this way, in this embodiment, even though the real address of the area storing the microprogram in the main memory is a large value of 32 bits, a part of it is held in register 2 and the value of register 2 is stored by the adder. By adding the output value of the address conversion table and the output value of the address conversion table to obtain the real address, the capacity of the address conversion table can be reduced and its usage efficiency is improved.

〔Effect of the invention〕

As explained above, according to the present invention, the second register holds a part of the real address corresponding to the micro logical address, and the real address corresponding to the micro logical address is indexed by the micro logical address. An address conversion table for giving a part of the address and an adder for adding the real address held in the second register and the real address given from the address conversion table are provided, and access is made by the real address obtained from the adder. By controlling the loading operation of microinstructions from main memory to control memory on a block-by-block basis, micro logical addresses and real addresses on main memory can be freely changed using an address translation table with the minimum required capacity. This has the effect of increasing the efficiency of using the address conversion table, and realizing a microprogram control system at a lower cost.

[Brief explanation of drawings]

FIG. 1 shows a block diagram showing an embodiment of the present invention, FIG. 2 shows an example of a microinstruction sequence, and FIG. 3 shows a microprogram area in a storage device and the correspondence between micro logical addresses and real addresses. It is a figure showing an example. 1...Register, 2...Register, 3...Control memory, 4...Address array, 5...Comparator, 6...
-Address conversion table, 7...Adder, 8...Main storage device, 9...Load control device, 11-15...Signal line. =15- Real address θρθ 3θθθ θρlθθθFθ θθ/ (M /l:ρ riθ15'7FFθ

Claims (1)

[Scope of Claims] A first register that holds a micro-logic address; a control memory that is accessed by a first partial address of the micro-logic address and is made up of a plurality of blocks and that holds micro-instructions; an address array storing a second partial address of a micro logical address corresponding to a microinstruction accessed by a first partial address of the address and stored in each of the plurality of blocks of the control memory; comparison means for comparing an output from the array with a second partial address of the micro-logical address held in the first register; and a first partial address of the real address corresponding to the micro-logical address; outputting a second partial address of the real address corresponding to the micro logical address by being indexed by a second register and a third partial address of the micro logical address that includes the second partial address of the micro logical address; an address conversion table for adding the first partial address and the second partial address of the real address; and an area for storing a microprogram consisting of a series of microinstructions; and a load control device that loads the microinstructions from the main storage device to the control memory in blocks when the results of the comparison means do not match. microprogram control system.