JPS61283077A - Synchronizing clock reproducing device - Google Patents

Abstract

PURPOSE:To adjust always optimumly and automatically the identifying level of an input signal and to obtain a satisfactory synchronizing clock signal by integrating a identifying level correcting signal fed from the code deciding device and providing an accumulating part to adjust the identifying level. CONSTITUTION:At a conventional synchronizing clock reproducing device, a code deciding device 11 and an accumulating part 15 are provided. In the deciding device 11, it is decided whether the zero cross point of the input signal is generated by the rise or by the fall, then, the phase error signal code is decided and the identifying level correcting signal is outputted. The correcting signal, in the accumulating part 14, is accumulated, attenuated and made into the identifying off-set signal, the signal is changed, and the identifying level is always optimumly kept. For such a reason, the satisfactory synchronizing clock signal can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a synchronous clock reproducing device for identifying reproduced data in a magnetic tape recorder that records and reproduces PCM signals.

(Prior Art) In recent years, in PCM magnetic tape recorders that perform multi-track recording and playback, development of a synchronous clock playback device has been progressing as a device that is highly stable using digital signal processing and can be downsized using time division multiplexing processing. For example, as in "About a method of data detection in a fixed digital tape recorder" Sugita et al., Institute of Electronics and Communication Engineers Electroacoustic Research Group Material EA-82-59, the multi-track playback signal is made into a time-division multiplexed signal, and the digital A series of devices that use signal processing techniques to reduce or eliminate code amount interference in a reproduced signal and perform data identification including synchronized clock recovery are being actively developed.

FIG. 4 is a block diagram of a conventional synchronous clock reproducing device, FIG. 5 is a signal waveform diagram of each part thereof, and FIG. 6 is a typical example of an eye pattern.

In FIG. 4, 1 is an adder, 2 is a delay device, 3 is a zero crossing determiner, and 4 is a phase calculator. Maku, 5 is a subtractor, 6
7 is an attenuator, 7 is a switch, 8 is an adder, and 9 is a delay device, which constitute a phase synchronization section 10.

A conventional synchronous clock regeneration device configured as described above will be explained.

First, as shown in the signal waveform shown in FIG. 5, the binary PC! [1
The number (,) is a band-limited waveform as shown in the ninth waveform (b) whose recording and playback characteristics are basically band-pass type, including playback waveform equalization, and tape transformer by recording and playback. This includes synchronization clock phase fluctuations due to port mechanism jitter, etc. Therefore, the input signal xn applied to the adder 1 in FIG. 4 becomes a signal of waveform (c) by discretizing the signal of waveform (b). Here, if the inversion period f of the PCM signal is TWC seconds], then the sampling period of the signal (c) is Tφ [seconds]. Now, assuming that the input discretized (,) signal ft is applied to device 2. Here, the applied Xn+Δ
χ is delayed by one sampling and outputted as Xn-1+Δxf, and the zero crossing determiner 3 is manually operated. The output xn+ΔX of the adder 1 is also applied to the zero crossing determiner 3, and when a zero crossing occurs between the two sample values represented by the output Xn-1+ΔX of the delay device 2, that is, (In+ΔK).
- Outputs 1" when (3Cn-1+ΔX)≦O, and no zero crossing occurs, when 59, that is, (xn+ΔX)
- When (Xn-, +ΔI)>O, outputs "O" t- and inputs it to switch 7. The phase calculator 4 calculates the output xn+ΔX of the adder 1 and the output +Δ! of the delay device 2.
As an input, the zero-crossing phase signal φ, n is defined as the phase value corresponding to the point xn+ΔX as shown in FIG. Calculate and output.

φn1 = 180"("n+Δ")/l
so'・(g("n"!1-1) The subtracter 5 receives the zero crossing phase signal φ1 calculated by the above formula.
n and the output φ of the delay device 9, which is the recovered clock phase signal.
The phase error signal φ is the difference signal between the phase error signal φ and the phase error signal φ. nt-n output and input to attenuator 6. Attenuator 6 has a specific attenuation rate α
The input phase error signal φ, ! Multiply by l and switch 7
input. The switch 7 receives the output of the zero crossing determiner 3 at 1# and the output of the attenuator 6 at 9 o'clock α·φ. n, and 10'' when it was 10'' is input to the adder 8, and here the phase value corresponding to the output of the switch 7 and 180', and the output φ of the delay device 9, n are added, and the modulus is calculated. 360a is output.

According to the configuration of the adder 8 and the delay device 9, when the output of the switch 7 is '0' as shown in FIG.
/Tv (Hz), and when the output of the switch 7 is 'O'', the output of the switch 7 is accumulated and outputted in addition to the free-running frequency component. It operates like an oscillator and outputs the recovered clock phase signal φ as the output of the delay device 9.

In this way, the phase periodicity unit 10 determines that the output of the zero crossing determiner 3 is “
When it is 1', it operates to follow the output φ1n of the adder 4, and when it is ``O'', it operates as a free-running oscillator, and the reproduced clock phase signal φrn can be taken out as the output of this device. Even if the time at which the zero crossing point of the synchronous clock of the input signal In occurs fluctuates, its output can be obtained continuously at the sampling time as a reproduced clock signal that follows it.

(Problem to be Solved by the Invention) However, in the above configuration, the discrimination level of the input signal is fixed, and the tracking operation of the phase synchronization unit 10 is required for an input signal having an offset in the discrimination level. became worse, and it was necessary to adjust the identification offset signal in order to obtain a good synchronized clock phase signal. Another problem is that it is impossible to adapt when the optimal discrimination level of the input signal changes. That is, FIG. 6 shows a typical example of the eye pattern of the input signal, and as shown in (a),
If the eye/4 turns are vertically symmetrical, the discrimination level may be zero, but if the eye/4 turn is vertically symmetrical, the discrimination level may be zero, but if the eye/4 turns are vertically symmetrical, it may occur due to DC offset of the ψ converter, etc. when inputting recorded and reproduced signals to this device. In the case of an eye/four turn such as (C) caused by nonlinearity of the recording/reproducing system, the optimum discrimination level does not become zero and the ninth discrimination offset signal needs to be adjusted. Nine.

SUMMARY OF THE INVENTION In view of the problems of the conventional devices described above, the present invention provides a synchronous clock regeneration device that requires adjustment of the identification offset signal and can automatically adjust the optimum identification level.

(Means for Solving the Problems) In order to achieve the above object, the synchronous clock regeneration device of the present invention includes an adder, a delay device, a zero crossing determiner, a phase calculator, and a phase synchronization section. In addition to the configuration of the conventional synchronous block device, a sign determiner and an accumulator are provided, and when the zero crossing point occurs due to the rising edge of the input signal, when the phase error signal is positive @1'', it is negative. 9"-1#, when the zero crossing occurs due to the falling edge of the input signal, when the phase error signal is positive, "-1#, and when it is negative, 1-1
”, if a zero crossing does not occur, the sign determiner outputs “0”, which is further accumulated and attenuated by the accumulator to become the identification offset signal, thereby changing the identification offset signal. It always maintains the optimum identification level and regenerates a stable synchronized clock.

(Function) With the above configuration, the synchronous clock regeneration device of the present invention can always make the identification level of the input signal normal, so that the tracking operation can be performed optimally even for input signals having an offset. , a good synchronized clock signal can be obtained. 'Furthermore, since the correction signals for the above-mentioned configuration are determined only by the codes of each part of the device, the circuit configuration becomes simple.

(Example) The present invention will be described below with reference to the drawings.

FIG. 1 shows the basic configuration of a synchronous clock reproducing device according to an embodiment of the present invention, and FIGS. 2 and 3 are diagrams explaining the signals in FIG. 1. In FIG. 1, 11 is a sign determiner. 9, 12 is an adder, 13 is a delay device, 1
Reference numeral 4 denotes an attenuator, which constitutes the accumulating section 15.Those with the same numbers as the conventional example have the same configuration and operation, so their explanation will be omitted, but the phase synchronization section 1
0, the phase error signal φ is used in addition to the output reproduced clock phase signal φ. , I'm taking it out and using it. Note that the identification offset signal changes depending on the optimum identification level, so in the explanation of the conventional example, it is expressed as ΔX, but in the following explanation, it is expressed as Δxn symbol.

First, the sign determiner 11 uses the output X+Δx0 of the adder 1 and the output of the delay device 2! Using n-1 ΔX 11-1 and phase error signal φ as input, those signals xn+ΔXj1
When a zero crossing occurs between the two sample values of #x11-4+ΔXn-1, the zero crossing occurs when the input signal xn rises or falls, or the zero crossing does not occur. The phase error signal φ at that time is determined. The sign of the signal is determined, and a discrimination error correction signal expressed as shown below is generated.

However, Igfl(φ.) is It is.

The adder 12 of the accumulator 15 adds the discrimination level correction signal Dn obtained as described above and the output of the delay device 13 and outputs the result, and the attenuator 14 applies a specific attenuation rate β to the output of the delay device 13. The product is multiplied and output as an identification offset signal ΔX. Therefore, the accumulator 15 outputs the identification offset signal ΔXn
The initial value at time n = 0 is set to ΔXO, the identified offset signal D11 is input, and the identified offset signal Δxn as shown in the following equation is output.

ΔxIII=βΣD1+Δx o ・”
(3) Here, the relationship between the optimum discrimination level of the input signal Cn of the apparatus of this embodiment and the discrimination level correction signal D is as follows.

In other words, Fig. 2 is an explanatory diagram of the case where there are many negative offsets at the optimum discrimination level, and (a) shows the opening of the eye/4 turn. A steady time lag occurs between the intersection and the zero intersection at the time of falling, but even in this case, the reproduced clock phase signal φ, which is the output of the phase synchronization unit 10, has a rising edge that is the average of the time lag. The operation is performed on the assumption that there is an average zero crossing point near the center of the zero crossing point and the falling zero crossing point, and the recovered clock phase signal is as shown in FIG. 2(b). On the other hand, a recovered clock phase signal based only on the zero crossing point due to the rising edge is given as shown in (0), and a recovered clock phase signal based only on the zero crossing point due to the falling edge is given as shown in (d). In this case, (b
As can be seen from the phase difference between ) and (c), when a zero crossing point occurs due to a rising edge, the phase error signal is the difference between (e) and (b) and is always negative. Further, as can be seen from the phase difference between (b) and (d), when a zero crossing point occurs due to a falling edge, the phase error signal is the difference between (d) and 6) and is always positive.

Similar to FIG. 2, FIG. 3 shows the case where a positive offset occurs in the optimal discrimination level. Similarly to the explanation of FIG. 2, when a positive offset occurs in the optimal discrimination level, ,
When a zero crossing point occurs due to a rising edge, the phase error signal is always positive, and conversely, when a zero crossing point occurs due to a falling edge, the phase error signal is always negative. Therefore, the above formula (2)
From the relationship, when a negative offset occurs in the optimal discrimination level, the discrimination level correction signal D, which is given due to the occurrence of all zero crossing points, always takes a value of "1", and conversely, when the optimum discrimination level If a positive offset occurs, the discrimination level correction signal Df is given by the occurrence of all zero crossing points.
i always takes a value of 1-1#. In the above operation, the eye pattern aperture is ideally 4, so the effects of reeds, code amount interference, and noise are ignored, but even if there is fluctuation at the zero intersection, the average operation is It can be considered as described above, and in particular, the present invention operates without problems because the discrimination level correction signal D is averaged in the form of the above equation (3) to obtain the discrimination offset signal Δx1m.

Therefore, when a negative offset occurs in the optimal discrimination level, the discrimination correction signal becomes positive on average, the discrimination offset signal ΔX increases, and the discrimination level can be brought closer to the optimum value, so that the discrimination level is always positive. When an offset occurs, the discrimination level correction signal becomes negative on average, the discrimination offset signal ΔX decreases, and the discrimination level can be brought closer to the optimum value.

That is, the present invention provides the sign determiner 11 in the synchronous clock regeneration device as described above, and thereby determines whether a zero crossing point is caused by a rising edge or a falling edge of the input signal x4.
The phase error signal φ at this time is determined. . The discrimination level correction signal Dn is determined by the combination with the sign of , and the discrimination level correction signal D is further averaged and added to the input signal In as the discrimination offset signal ΔX.1) The discrimination level is always optimal. automatically adjusted so that Furthermore, let the time constant of the accumulation part be infinite, that is, a perfect integral, fc7'c
Therefore, the optimum discrimination level is set without causing any error even with the steady offset of the optimum discrimination level.

(Effects of the Invention) The present invention provides an identification level correction signal by determining whether a zero crossing point of an input signal is caused by a rising edge or a falling edge, and by determining the sign of the phase error signal at that time. By providing a code and a judge that output the discrimination level correction signal, and providing an accumulator that integrates this discrimination level correction signal and adjusts the discrimination level, it is possible to always maintain the discrimination level at an optimum level. Since the configuration is such that determination is made using only the signs of each part signal, an excellent synchronous clock reproducing device can be realized with a simple circuit configuration.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a synchronous clock regeneration device according to an embodiment of the present invention, FIGS. 2 and 3 are signal explanation diagrams, FIG. 4 is a configuration diagram of a conventional synchronous clock regeneration device, and FIG. 5 shows each part. The signal waveform diagram, FIG. 6, is an eye pattern. 1.8.12... Adder, 2.9.13... Delay device, 3... Zero crossing determiner, 4... Phase calculator, 5...
・Subtractor, 6.14... Attenuator, 7... Switch,
10... Phase synchronization unit, 11... Sign determiner, 15.
...Accumulation section. Figure 2 Figure 3 Figure 5 Ward Funeral Figure 6

Claims (1)

[Claims] An adder that adds a binary level identification offset signal of the binary PCM signal to an input signal that discretely samples a band-limited binary PCM signal, and delays the output of this adder by one sampling period. The adder output signal and this delay device output signal are inputted, and if a sign inversion occurs between two points at one sampling period interval, the signal is "1"; otherwise, it is "1". A zero-crossing determiner that outputs "0" is inputted with the adder output signal and the delayer output signal, and calculates the relative time between the zero-crossing time at which the sign inversion occurs and the sampling time, and calculates the zero-crossing phase. A phase calculator that outputs a signal, and inputs the output of the zero-crossing determiner and the output of the phase calculator, and operates to follow the zero-crossing phase signal when the output of the zero-crossing determiner is "1"; a phase synchronization section that outputs a free-running regenerated clock phase signal and at the same time outputs a phase error signal that is a difference signal between the zero crossing phase signal and the regenerated clock phase signal, and the adder output and the delay the output of the phase synchronization part and the output of the phase error signal of the phase synchronization part are input, and when the zero crossing occurs, it is determined whether the zero crossing occurs at the rising edge or the falling edge of the binary PCM signal, and A sign determiner that determines the sign of the phase error signal and outputs "1", "0" or "-1" depending on a specific combination of these two determination results; 1. A synchronous clock reproducing device, comprising: an accumulating unit that integrates the signal and outputs the binary level identification offset signal as the binary level identification offset signal.