JPH01158671A - Data identifying device - Google Patents

Abstract

PURPOSE:To identify data with high stability by identifying the data by the combination of an identification point phase, a reproducing clock phase and the highest-order bit of a phase error. CONSTITUTION:Each time an identification point is generated in an input signal, an identification point phase phii is outputted and a reproducing clock phase phir, a phase error phie and punching number signals UP and Down are obtained by a phase synchronizing circuit 16 consisting of a subtracter 3, a switch 4, an LPF 5, an adder 15 and a delay device 7. The decision of the data is executed by obtaining the correspondence of the detected identification point to a punching clock given by the UP and DOWN. A code interval accumulator 20 obtains the number of '0s' between the identification points, that is, between neighboring codes '1' and '1' in a 2/7 modulation and outputs 3-bit parallel data INT3, INT2 and INT1 and their output timing instructing signal TIMING. The identification of the data is executed by the simple circuit of the combination of the highest-order bit of each phase signal and the punching clock number signal.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a device for recording and reproducing PCM signals, such as a data identification device in a magneto-optical disk device.

2. Description of the Related Art In recent years, magneto-optical disk devices have been actively developed as large-capacity data file devices capable of high-density recording and playback, and data identification devices for playback signals have also been developed to draw in clock components in playback signals at high speed and stably. A data identification device has been developed that has a phase-locked circuit that reproduces data to identify data. Regarding this data identification device, various devices using digital signal processing have been developed in order to achieve high stability and miniaturization.For example, Sugita et al. (IEICE Study Group Material EA82-・59
, 1986) has been developed.

Hereinafter, a conventional data identification device as described above will be explained with reference to the drawings.

FIG. 7 shows the configuration of a conventional data identification device.

Figures 8 and 9 are waveform characteristic diagrams for explaining phase calculation, Figure 10 is a waveform diagram for explaining data judgment, and Figure 11 is a waveform diagram for explaining data judgment.
The figure is a waveform diagram of the output signal. P recorded and played here
The GM signal is an 8-10 converted signal, and the minimum inversion interval (Twin C5ec) is the window width Tw (sea).
The signal is equal to . Clock regeneration is performed on this signal based on the zero crossing information, and data is identified. Here, the PGM reproduction signal which is the input signal of this data identification device has a signal waveform which has fluctuations in its clock component and has been low-pass filtered, as seen in all high-density recording and reproduction devices.

In FIG. 7, 1 is an analog-digital converter, 2
is a phase calculator, 3 and 10 are subtractors, 4 is a switch, 5
is a low-pass filter, 6 and 12 are adders, 7 and 11 are delay devices, and 8 is a phase locked circuit. Further, 11 is a multiplier, and 13 is a data determiner.

First, the analog-to-digital converter 1 samples and quantizes an input signal at a frequency twice its clock frequency, ie, 2/Ty (Hz), and outputs the sampled signal.

The phase calculator 2 outputs a discrimination point detection signal Sv as 1'' when a zero crossing point, which is a discrimination point, occurs between two consecutive sampling points from the output of the analog-digital converter 1, and outputs the discrimination point detection signal Sv as 1'', as shown in FIG. The time of occurrence of the discrimination point is set to 1
80° As a reference phase, the phase value i at the sampling time is calculated by linear interpolation from the two sampling values using the following equation and output.

Here, since the sampling interval is half of the window width Tw, which is the data cycle, this sampling interval is considered to be 1800, which is half of one cycle of 3600, and the following equation is obtained. However, S2≧o, 51(o).

The subtracter 3 uses the discrimination point phase Φ1 and the reproduced clock phase Φr.
The phase error Φθ, which is the difference between the two, is calculated and output.

The switch 4 is turned on when the discrimination point detection signal Sv is 1'' and off when it is "o", and outputs a phase error Φe that becomes effective when the discrimination point is detected.

The low-pass filter 5 performs low-pass filtering on the output of the switch 4, multiplies it by an appropriate gain, and outputs the result. The adder 6 adds the output vp of the low-cut filter 6, the value corresponding to the phase value of 1800, and the reproduced clock phase Φr, and outputs a remainder that makes the modulus 360°,
Also, the change when taking the remainder from VALID, which is a carry signal, is (0°).

3 e o'), O''', 0° if the range is not exceeded.
Or, if the change exceeds 360°, it is output as °゛1''.However, the range symbol (x, y) indicates the range of people where X≦mukuy.This VALID is the data punching signal. and the processing clock frequency is 2/Tw[)IZ)
So, the value from VAL is approximately once every two clocks?
Take +113. Delay device 7 delays the output of adder 6 by one clock and outputs it as a recovered clock phase Φr. According to the above series of operations, the subtracter 3. Switch 4. Low-pass filter6. The adder 6 and the delay device 7 constitute a phase synchronization circuit, and as shown in FIG. 9, the instantaneous value of the reproduced clock phase is always obtained based on the discrimination point, which is the zero crossing point of the input signal.

A data determiner 13 is constituted by a delay device 9, a subtracter 10, a multiplier 11, and an adder 12, and the data is identified based on the VAL.
This is performed using the ID, the sampling values Sl and S2, and the reproduction clock value Φr.

The identification data DATA outputs "1" if the input signal is positive or zero when VALID becomes "1", and 10" if it is negative. Judgment of the input signal sign near the identification point is as follows:
The sign of the input signal at the punching time is calculated and output using the two consecutive sampling values S+, S2 and the reproduced clock phase Φr.

The sign calculation at this time is also calculated using the following equation by linear interpolation.

DATA = sgn (S2-(32-3t)XΦr×
-2) However, sgn() is when the sign in () is positive or 0'
ζ″, represents “O” when negative. As described above, a reproduced clock signal synchronized with the clock component of the input signal is obtained, and the obtained phase value can be used to identify the original data.

Problems to be Solved by the Invention However, in the recording/reproducing characteristics of magneto-optical disk devices, second-order distortion occurs in the reproduced signal due to the optical output during writing, and the amount of distortion can be quantitatively controlled. This has the disadvantage that the duty of the reproduced signal is unstable.For this reason, it is difficult to use a modulation method that imparts information in the width direction of the PGM code as in the conventional example, and it is difficult to use a modulation method such as 2/7 modulation. Using a modulation method in which the minimum inversion interval Tm1nC8θC] is larger than the window width Tw (sec:), recording and reproduction are performed with one recording bit corresponding to the code +111+, and the thickest point of the reproduced signal is detected. In the modulation method, the window width Tw [SθC] is 0.5T (sec'l) where the data inversion interval before modulation is T (sea).
However, the window width Ty(s
Since ec) is o, 5T(sec), 2/
The sampling frequency of Tw (Hz) is high.However, in the case of this modulation method, Tm1n=Ty
However, since Tm1n = 3 Tw, processing can be performed with a sampling interval of Ty(sθC).

That is, the sampling frequency and digital signal processing clock frequency are 1/Ty(az). In this case, data identification involves identification of maximum points, and the conventional method described above cannot be used.

In view of the above problems, the present invention realizes a method of identifying data using digital signal processing, and provides a highly stable data identification device.

Means for Solving the Problems To achieve this objective, the data identification device of the present invention comprises:
A PCM signal recorded and reproduced on a recording medium is used as an input signal,
An analog-to-digital converter samples and quantizes the sample using a sampling clock equal to the clock frequency, and outputs the quantized data, and the output of the analog-to-digital converter determines the time of the zero crossing point, maximum point, minimum point, etc. of the input signal. A phase calculator that calculates and outputs the discrimination point phase, which is a relative value to the sampling time, and a reproduced clock phase that represents the instantaneous phase of the input signal from the output of the phase calculator, and calculates the phase of the data at the processing clock. a phase synchronization circuit that outputs the number of punches, the reproduced clock phase, and a phase error that is the difference between the reproduced clock phase; and the most significant bit of the identification point phase, the number of punches, the most significant bit of the reproduced clock phase, and the most significant phase error. The configuration includes a data determiner that receives bits as input and outputs identification data based on a combination of these bits.

Effect of the Invention With the above configuration, the present invention inputs clock recovery of an analog-to-digital converted PCM signal, and performs data identification by a combination of the most significant bit of the identification point phase, the recovered clock phase, the phase error, and the punching number signal. By doing so, a data identification device can be realized with a simple configuration.

EXAMPLE An example of the present invention will be described below with reference to the drawings.

FIG. 1 shows the basic configuration of a data identification device in an embodiment of the present invention, FIG. 2 is a detailed view of the main part showing a data determiner of the data identification device, and FIGS. 3 and 4 are FIG. 5 is a phase characteristic diagram for explaining phase calculation, FIG. 5 is a waveform diagram for explaining data determination, and FIG. 6 is a waveform diagram of each part signal. In the following explanation of the drawings, the same components as those in FIG. 7 of the conventional example are designated by the same reference numerals and will be omitted.

First, in FIG. 1, an input signal which is a 2/7 modulated reproduced signal is sampled and quantized at a clock frequency of 1/T1y (Hz) and output.

Here, the identification point of the input signal is the maximum point. Phase calculator 1
4 outputs the detection signal Sv of the discrimination point, and at the same time, as shown in FIG. S2. From S3, it is calculated and output according to the following formula.

However, S5-S2<O, S2-51≧0.

Further, the adder 15 calculates the remainder by adding the output VIA (!: output of the delay device 7) of the low-cut filter 5 to make the modulus 3600, and outputs it as the recovered clock phase Φr.
If the change when taking the remainder as CARRY, which is a carry signal, is in the range of (0°, 360'), set '0''.
If the change exceeds the range, it outputs 1''. The adder 15 and the delay device 7 constitute a voltage controlled oscillator, and at this time, the punching information for this data is obtained from the voltage controlled oscillator. Input Since the sampling frequency of the signal is equal to its clock frequency, data is normally punched out once within one sampling interval, but it may be punched out 0 or 2 times due to time jitter associated with recording and reproduction. DOWn=”ff” for 0 times
, In the case of two times, Up = Ij 1++, and in the other cases, I)own and Up are both ``Q'''' and ``p +
If DOWn is expressed as a data punching number signal, Up
・I) Own is given by D□wl=Vp-CARRY Up=vp-CARRY.

As shown in FIG. 4, the discrimination point phase Φi is output every time a discrimination point occurs in the input signal, and the subtractor 3° switch 4.
Low-pass filter 5. Adder 15. The phase synchronization circuit 16 configured by the delay device 7 outputs the reproduced clock phase Φr, the phase error Φe, and the punching number signal I)own, typ.
is obtained. Data determination is based on detected identification points and trp
, I) by finding the correspondence with the punching clock given by own. Letting the most significant bits of the discrimination point phase (2), i-regenerated clock phase Φr, and phase error Φe obtained as above be φi, φr, and φe, respectively, the data determination formula is that the discrimination point is detected. If the case where the identification point corresponds to the punching clock with respect to the clock is represented by PRESENT, and the case where it corresponds to the punching clock one clock earlier is represented by PAST, the following equation is obtained.

PRESENT-φi・φr＋φ1・φr・φθ+φ1
・φr・φePAST =φ1・φr+φ1・φr・φ
The determination of θ+φi, φr, and φθ data is performed using the above PRESENT, PAST, and Up r Dow as shown in Figure 2.
The code interval accumulator 20 calculates the number of 10'' between adjacent codes ``1'' and 1'' in 2/7 modulation and outputs 3-bit parallel data INT3, lNT2, lNT1 and their output timing instruction signal TIMING are output.

According to the above series of operations, data can be identified by a combination of the most significant bit of each phase signal and the number of punching clocks, and can be realized with a simple circuit configuration.

Further, the processing clock in this case has a frequency equal to the clock frequency of the PCM signal, and the data identification device A can be realized by using a relatively low frequency.

Effects of the Invention The present invention provides a simple I? It is possible to realize an excellent data identification device in which the signal processing clock frequency is relatively low, and the output transfer rate is also relatively low because it is based on the output of the symbol interval. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a data identification device in an embodiment of the present invention, FIG. 2 is a detailed view of its main parts, FIGS. 3 and 4 are phase characteristic diagrams for explaining phase calculation, Fifth
The figure is a waveform diagram for explaining data identification, Figure 6 is a waveform diagram of various signals, Figure 7 is a block diagram showing the configuration of a conventional data identification device, and Figures 8 and 9 are explanations of phase calculation. FIG. 10 is a waveform diagram for explaining data determination, and FIG. 11 is a waveform diagram of the output signal. 1...Analog-digital converter, 2.14
... Phase calculator, 3, 10 ... Subtractor, 4 ... Switch, 5 ... Low pass filter, 6. "12.15... Adder, 7.9...
...delay device, 8.16 ... phase synchronized circuit, 1
1... Multiplier, 13. '17...Data judger-18...AND gate, 19...
...OR gate. Name of agent: Patent attorney Toshio Nakao and 1 other person76
-a-phase synchronous circuit Figure 2 Figure 3 Figure 4 σ=-- plan, n-type punched appearance at the identification point Figure 6 Figure 7::'': 8 Figure 11 7w -- X ;'i 9th ward

Claims (1)

[Claims] an analog-to-digital converter that takes a PCM signal recorded and reproduced on a recording medium as an input signal, samples it with a sampling clock equal to the clock frequency, quantizes it, and outputs it; and a zero crossing point of the input signal from the output of the analog-to-digital converter. Alternatively, a phase calculator that calculates and outputs a discrimination point phase that is a relative value between the time of a discrimination point such as a maximum point or a minimum point and the sampling time, and a phase calculator that calculates the instantaneous phase of the input signal from the output of the phase calculator. a phase synchronization circuit that calculates a reproduced clock phase to output the number of data punched out in the processing clock, the reproduced clock phase, and a phase error that is the difference between the reproduced clock phase; and the most significant bit of the discrimination point phase; A data identification device comprising: a data determiner that receives as input the number of punches, the most significant bit of the reproduced clock phase, and the most significant bit of the phase error and outputs identification data based on a combination thereof.