JPS63148469A - Clock reproducing device - Google Patents

Abstract

PURPOSE:To prevent the deterioration in resolution of the phase calculation by equalizing the PCM signal undergone the analog/digital conversion via a digital filter after differentiating them and furthermore shifting the bits of the PCM signals for compensation of the overflow to carry out the phase calcula tion. CONSTITUTION:A substrate 17 outputs the output difference between a coefficient means 15 and a delay means 13; while a subtractor 18 outputs the output difference between a coefficient means 16 and the subtractor 17. Thus a digital filter consists of the delay means 13 and 14, the coefficient means and 15 and 16 and the subtractors 17 and 18. This filter suppressed the fluctuation of the amplitude of output of a differential means caused by the difference of PCM code intervals. Then a bit shifter 19 shifts the output of the subtractor 18 so as to remove the second place bit and outputs the signals of low tone levels to a phase calculator 5. Furthermore the shifter 19 holds the bit-shifted output at the maximum or minimum level so that no disturbance is given to said output as a relevant code when the output amplitude of the digital filter is increased and the second place bit has meaning.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a device for recording and reproducing PCM signals, such as a reproduction data identification device in a magneto-optical disk device.

BACKGROUND OF THE INVENTION In recent years, magneto-optical disk devices have been actively developed as large-capacity data file devices capable of high-density recording and playback, and a clock regeneration device that regenerates a clock component in a playback signal is also used in a data identification device for a playback signal. being developed. A clock regeneration device using a digital phase synchronization circuit has been developed as a device having high-speed pull-in and highly stable synchronization characteristics.

Hereinafter, a conventional clock regeneration device as described above will be explained with reference to the drawings. FIG. 4 shows the configuration of a conventional clock regeneration device, and FIGS. 5 and 6 show waveform examples of a PCM signal, which is an input signal. The PCM signal recorded and reproduced here is 2/7 modulated (Special Publication No. 55-2
6494, etc.), and clock reproduction for the PCM reproduction signal, which is an input signal, is performed by detecting its maximum point. This PCM reproduction signal has a clock component that fluctuates as seen in all high-density recording and reproduction apparatuses, and has a low-pass filtered signal waveform.

In Figure 4, 1 is analog-digital (A/D)
Converter, 2 and 4 are delayers, 3 and 7 are subtracters, 5 is a phase calculator, 6 is an extremum determiner, 8 is a switch, 9 is a low-pass filter, 1o is an adder, 12 is the phase synchronization part.

First, the analog-to-digital converter 1 synchronizes a PCM input signal, which is a reproduction signal of a magneto-optical disk, which has undergone 2/7 modulation, with the signal processing clock of this apparatus, which has a fixed frequency equal to the clock frequency. It is sampled, quantized, and output in two's complement representation. The delay device 2 delays the output of the analog-to-digital converter 1 by one clock period and outputs it, and the subtracter 3 outputs the output from the analog-to-digital converter 1 by delaying it by one clock period.
The difference between the output of the delay device 2 and the output of the delay device 2 is output, and therefore the delay device 2 and the subtractor 3 constitute a difference device. The delay device 4 delays the output of the subtractor 3 by one clock period and outputs the delayed signal.

The phase calculator 6 usually consists of a read-only memory, and uses the output S1 of the subtracter 3 and the output S2 of the delay device 4 as memory address inputs to calculate the phase error signal φ1 using the following formula.
The extreme value determiner 6 determines whether the output of the subtractor 3 is positive or 0,
That is, if the most significant bit is "0" and the output of the delay device 4 is negative, that is, the most significant bit is "1'',
", and "O" in other cases. Therefore, when the thick point occurs, the output of the extreme value judger 6 is "1", and in other cases, it is "0".

Further, the subtracter 7 outputs the difference between the output of the phase calculator 6 and the output of the delay device 11. This output is the clock recovery phase that is the output of the device. Switch 8 is the extreme value judger e output.
1", the output of the subtractor 7 is output. Therefore, the output of the phase calculator 5 becomes valid when the output of the extreme value determiner 6 is "1". The output of switch 8 is amplified, low-pass filtered, and output.Adder 1o adds the low-pass filter 9 and subtracter 7 outputs and outputs the result, and delayer 11 further delays the output of adder 10. Therefore, the adder 1o and the delay device 11 constitute an integrator.The adder 7, the switch 8, the low-pass filter 9, the adder 10, and the delay device 11 constitute the phase synchronization section 12. , outputs a clock reproduction signal synchronized with the clock component of the input signal.This clock reproduction signal is the clock reproduction output of this data identification device.In the above series of operations, the phase of the thick point of the input signal is the PCM signal. Accordingly, even if the clock is input intermittently, its phase value is interpolated and output in all clock cycles in the clock reproduction output.

Moreover, this regenerated clock signal is obtained by low-pass filtering the fluctuation of the phase value calculated from the maximum point of the input signal.

As described above, a reproduced clock signal synchronized with the clock component of the input signal is obtained, and the obtained phase value is used to identify the original data.

Problems to be Solved by the Invention When recording and reproducing data in a magneto-optical disk device, a PCM signal is recorded and reproduced, but data identification of the reproduced signal relies on detection of its maximum point. It greatly depends on the accuracy of the pole phase calculation.

Therefore, the tracking characteristics of the PLL are highly dependent on the quantization resolution of the signal input to the phase calculator 6, and the read-only memory used in the phase calculator 6 has to be large in scale. Furthermore, if the scale of this memory is limited, the tracking characteristics of the phase synchronization section 12 inevitably become poor. For example, in the case of an input signal whose signal waveform is as shown in Fig. 6 and whose envelope fluctuation is shown in Fig. 6, the input signal novel quantizes the maximum input level of the analog-digital converter 1 to the entire signal waveform shown in Fig. 6. must be set up so that it can be done. In this case, the 2/2
As shown in the breakdown of the quantization resolution in Figure 7, the PCM signal section subjected to the 7-modulation is relatively /J't compared to the resolution of the output of the analog-to-digital converter 1, and is extremely low. There was a lot of waste.

In view of the above-mentioned problems, the present invention provides a clock regeneration device that performs highly stable operation with consistently accurate follow-up characteristics by realizing phase calculation with a small memory size required for the phase calculation and with little resolution deterioration of the phase calculation. It provides:

Means for Solving the Problems To achieve this objective, the clock recovery device of the invention samples a low-pass filtered PCM signal with a varying clock component with a tarot of a fixed frequency equal to its clock frequency. An analog-to-digital converter that quantizes and outputs the result, a differentiator that differentiates and outputs the output of the analog-to-digital converter, a digital filter that equalizes and outputs the output of the differentiator, and an output of the digital filter. a bit shifter that bit-shifts the bit shifter, a delay device that delays and outputs the bit shifter, and a phase that calculates and outputs the phase value when an extreme value occurs in the PCM signal from the output of the bit shifter and the output of the delay device. The configuration includes a calculator and a phase regenerator that performs low-pass filtering on the output of the M phase calculator and interpolates the clock phase of the PCM signal even when the extreme value does not occur.

Operation The present invention calculates the phase after performing a phase calculation after differentially converting the analog-to-digital converted PCM signal using a digital filter, further bit-shifting, and compensating for overflow, thereby increasing the resolution of the phase calculation. It is possible to prevent the deterioration of

EXAMPLE An example of the present invention will be described below with reference to the drawings.

FIG. 1 shows the basic configuration of a clock regeneration device according to an embodiment of the present invention, and FIGS. 2 and 3 show examples of signals at each part. In the following description, the same components as those in the conventional example shown in FIG. 4 are designated by the same numbers and omitted.

In FIG. 1, 13 and 14 are delay units, 15 and 16 are coefficient units, 17 and 18 are subtracters, and 1 bit shifter.

The operation of the clock regeneration device configured as described above will be described below.

First, as shown in FIG. 1 and FIG. 2, an input signal is sampled, quantized, and a difference is taken, resulting in a differentiator output which is the output of the subtracter 3. Delay units 13 and 14 are subtracter 3
output with a delay.

Coefficient units 16 and 16 multiply the outputs of subtracter 3 and delay unit 14 by specific coefficients, respectively, and output the result. The subtracter 17 outputs the difference between the outputs of the coefficient unit 16 and the delay unit 13, and the subtracter 18 outputs the difference between the outputs of the coefficient unit 16 and the subtracter 17. Therefore, delay units 13 and 14, coefficient units 16 and 16, and subtractor 1
7 and 18 constitute a digital filter, and by selecting appropriate coefficients, as shown in FIG. 2, fluctuations in the amplitude of the differentiator output due to the difference in the PCM symbol interval are suppressed.

Here, the resolution of the signal at the output of this digital filter is determined by the resolution of the analog-to-digital converter 10, and the resolution of the amplitude of 1,6T, which is the PCM code interval with the minimum amplitude, is the resolution of the signal in the conventional example. However, the maximum amplitude is comparable to the minimum amplitude. That is, when the value of the output of the digital filter changes, the second or third bit is approximately the same as the most significant bit, and is meaningless as information input to the phase calculator 6.

The bit shifter 19 bit-shifts the output of the subtracter 18 so as to remove the second-order bit, and outputs a signal with a small word length to the phase calculator 6. At the same time, the output amplitude of the digital filter increases and the bit shifter 19 uses the bit-shifted output as its sign and holds the maximum value to the minimum so that there is no problem, and outputs the signal. It is something to do.

As described above, according to this embodiment, by adding a digital filter, the signal level of the input PCM signal is made constant, the circuit scale required for phase calculation is reduced, and highly accurate phase calculation can be performed without deteriorating resolution. An O, Y replay device can be created.

Effects of the Invention The present invention suppresses fluctuations in signal amplitude during phase calculation by providing a digital filter, thereby preventing deterioration of phase calculation resolution. Furthermore, by compensating for overflow when performing bit shifting to improve resolution, an excellent clock regeneration device that can perform bit shifting with small errors can be realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a clock regeneration device according to an embodiment of the present invention, FIGS. 2 and 3 are waveform diagrams showing signals of each part in FIG. 1, and FIG. 4 is a conventional clock regeneration device. 6 is a waveform diagram of an input signal, and FIG. 7 is a quantization resolution distribution diagram of an input signal. 1...Analog-digital converter, 2,4゜11, 13.14...Delay unit, 3,7,10
゜17.18...Subtractor, 6...Phase calculator, 6...Extreme value judger, 8...Switch, 9... ...low-pass filter, 12...
Phase synchronization unit, 15.16...Coefficient unit, 19...
...Bit shifter. Figure 2 Figure 3

Claims (1)

[Claims] An analog-to-digital converter that samples and quantizes a low-pass filtered PCM signal whose clock component fluctuates with a clock having a fixed frequency equal to the clock frequency, and outputs the quantized signal; a digital filter that equalizes and outputs the output of the digital filter, a bit shifter that bit-shifts the output of the digital filter, a delay device that delays and outputs the bit shifter, and an output of the bit shifter. a phase calculator that calculates and outputs a phase value when an extreme value occurs in the PCM signal from the output of the delay device; and a phase calculator that low-pass filters the output of the phase calculator and when the extreme value does not occur; and a phase reproducing section for interpolating the clock phase of the PCM signal.