JPS6128124B2 - - Google Patents

Info

Publication number
JPS6128124B2
JPS6128124B2 JP55150468A JP15046880A JPS6128124B2 JP S6128124 B2 JPS6128124 B2 JP S6128124B2 JP 55150468 A JP55150468 A JP 55150468A JP 15046880 A JP15046880 A JP 15046880A JP S6128124 B2 JPS6128124 B2 JP S6128124B2
Authority
JP
Japan
Prior art keywords
memory
routine
memory module
signal
power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55150468A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5775307A (en
Inventor
Kenji Nishikido
Hideaki Nakamura
Kyoto Hirase
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Tateisi Electronics Co filed Critical Omron Tateisi Electronics Co
Priority to JP55150468A priority Critical patent/JPS5775307A/ja
Publication of JPS5775307A publication Critical patent/JPS5775307A/ja
Publication of JPS6128124B2 publication Critical patent/JPS6128124B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
    • G05B19/058—Safety, monitoring
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/11—Plc I-O input output
    • G05B2219/1188—Detection of inserted boards, inserting extra memory, availability of boards

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Programmable Controllers (AREA)
  • Safety Devices In Control Systems (AREA)
JP55150468A 1980-10-27 1980-10-27 Programmable logical controller Granted JPS5775307A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55150468A JPS5775307A (en) 1980-10-27 1980-10-27 Programmable logical controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55150468A JPS5775307A (en) 1980-10-27 1980-10-27 Programmable logical controller

Publications (2)

Publication Number Publication Date
JPS5775307A JPS5775307A (en) 1982-05-11
JPS6128124B2 true JPS6128124B2 (enrdf_load_stackoverflow) 1986-06-28

Family

ID=15497568

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55150468A Granted JPS5775307A (en) 1980-10-27 1980-10-27 Programmable logical controller

Country Status (1)

Country Link
JP (1) JPS5775307A (enrdf_load_stackoverflow)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01149107A (ja) * 1987-12-07 1989-06-12 Fanuc Ltd 数値制御装置
JPH01194001A (ja) * 1988-01-29 1989-08-04 Fanuc Ltd 修理時のメモリ内容の移管装置
JPH0230502U (enrdf_load_stackoverflow) * 1988-08-22 1990-02-27

Also Published As

Publication number Publication date
JPS5775307A (en) 1982-05-11

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