JPS61280675A - Complementary semiconductor device - Google Patents
Complementary semiconductor deviceInfo
- Publication number
- JPS61280675A JPS61280675A JP60122226A JP12222685A JPS61280675A JP S61280675 A JPS61280675 A JP S61280675A JP 60122226 A JP60122226 A JP 60122226A JP 12222685 A JP12222685 A JP 12222685A JP S61280675 A JPS61280675 A JP S61280675A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- layer
- semiconductor
- electrode
- electron affinity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 77
- 230000000295 complement effect Effects 0.000 title claims abstract description 14
- 239000012535 impurity Substances 0.000 claims abstract description 12
- 238000002347 injection Methods 0.000 claims description 15
- 239000007924 injection Substances 0.000 claims description 15
- 239000000758 substrate Substances 0.000 abstract description 9
- 238000005468 ion implantation Methods 0.000 abstract description 7
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 3
- 230000008020 evaporation Effects 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- 229910001427 strontium ion Inorganic materials 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 7
- 230000003321 amplification Effects 0.000 description 5
- 238000003199 nucleic acid amplification method Methods 0.000 description 5
- 239000000969 carrier Substances 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 125000005842 heteroatom Chemical group 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1066—Gate region of field-effect devices with PN junction gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/207—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds further characterised by the doping material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/432—Heterojunction gate for field effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Bipolar Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は高速動作の半導体装置、特に相補型の半導体装
置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high-speed operating semiconductor device, and particularly to a complementary semiconductor device.
近年、高速コンピュータ用素子として、超高速素子の研
究開発が盛んである。このような超高速素子の中で、大
きな電流駆動能力を有するものとして、バイポーラトラ
ンジスタが注目されている。In recent years, research and development of ultrahigh-speed devices as devices for high-speed computers has been active. Among such ultra-high-speed devices, bipolar transistors are attracting attention as they have a large current driving capability.
特にＧａＡｓ等化合物半導体を用いた高性能バイポーラ
トランジスタとして、エミッタにペースよりバンドギャ
ップの大きい半導体を用いた、いわゆるヘテロバイポー
ラトランジスタ（Ｉ（ＢＴ ）およびそのＩＣ化が研究
されている。例えば、１９８１年国際電子デバイス会議
（Ｉｎｔ’ｌ Ｅｌｅｃｔｒｏｎ Ｄｅｖｉｃｅｓ Ｍ
ｅｅｔｉｎｇ）ダイジェスト、６２９頁から６３２頁に
あるように、ペースにＧａＡａ″ｆ：、エミッタにＡｔ
ＧａＡｓを用いたｎｐｎ型が良く研究されている。In particular, as a high-performance bipolar transistor using a compound semiconductor such as GaAs, the so-called hetero-bipolar transistor (I(BT)), which uses a semiconductor with a larger band gap than PACE for the emitter, and its IC implementation are being researched.For example, in 1981 International Conference on Electronic Devices
GaAa″f: on the pace, At
The npn type using GaAs has been well studied.
しかしながら、ＨＢＴでは構造およびプロセスが極めて
複雑であり、高集積化には多くの問題点を残している。However, HBTs have extremely complex structures and processes, and many problems remain in achieving high integration.
また特にコレクターペース間容量が大きく、高速性も限
定されている。さらに高集積化［ｆｌ、相補型構成のメ
リットが大であるが、正孔をキャリアとするｐｎｐ型は
得られていないのが現状であり、まして相補型の装置を
得るのは困難な状況にある。In addition, the capacity between the collector paces is particularly large, and high speed performance is also limited. Furthermore, higher integration [fl, complementary type configuration has great advantages, but at present, a pnp type device that uses holes as carriers has not been obtained, and it is even more difficult to obtain a complementary type device. be.
本発明の目的は、電流駆動能力が大きく、かつ高速で、
構造の簡単な、超高速、高集積ＩＣに適した新規な相補
型半導体装置を提供することにある。The object of the present invention is to have large current drive capability, high speed,
The object of the present invention is to provide a novel complementary semiconductor device that has a simple structure, is suitable for ultra-high speed, and highly integrated ICs.
本発明は低不純物密度の第１の半導体層上に、該第１の
半導体よシ、電子親和力が小さく、かつ電子親和力とバ
ンドギヤングの和が大きい低不純物密度の第２の半導体
層金膜け、該第２の半導体層に正孔の注入電極と電子の
注入電極とを設は九ことを特徴とする相補型半導体装置
および、低不純物密度の第１の半導体層と、該第１の半
導体より電子親和力が小さく、かつ電子親和力とバンド
ギャップとの和が大きい低不純物密度の第２の半導体層
と、前記第１の半導体層に接して、該第２の半導体層の
反対側に設置した第１の半導体より、電子親和力が小さ
く、かつ電子親和力とバンドギャップとの和の大きい高
抵抗の第３の半導体層とを備え、前記第２の半導体層に
正孔の注入電極と、電子の注入電極とを設けたことを特
徴とする相補型半導体装置である。The present invention provides a first semiconductor layer with a low impurity density, and a second semiconductor layer gold film with a low impurity density, which has a smaller electron affinity than the first semiconductor and a larger sum of the electron affinity and the bandgyan. a complementary semiconductor device, characterized in that the second semiconductor layer is provided with a hole injection electrode and an electron injection electrode; a first semiconductor layer with a low impurity density; a second semiconductor layer with a low impurity density that has a smaller electron affinity than the semiconductor and a larger sum of the electron affinity and the band gap; and a second semiconductor layer that is in contact with the first semiconductor layer and placed on the opposite side of the second semiconductor layer. a high-resistance third semiconductor layer having a lower electron affinity and a higher sum of electron affinity and band gap than the first semiconductor layer, and a hole injection electrode and an electron injection electrode in the second semiconductor layer. This is a complementary semiconductor device characterized by being provided with an injection electrode.
第１図は、本発明による半導体装置の基本構造を示すも
のである。ここで１１は高抵抗基板、１２は低不純物密
度の第１の半導体層、例えばアンドープＩｎＧａＡｓ層
、１３は第１の半導体より電子親和力が小さく、かつ電
子親和力とバンドギャップの和の大きい低不純物密度の
第２の半導体層、例えばＩｎＡｔＡａ層、１４はｐ＋領
領域１５はｎ 領域、１６ 、１７ｆ′ｉ電子チヤネル
にオーム性の一対の電極で、例えばｎ” −ＩｎＧａＡ
ｓ領域１６ｍ 、 １７ｍと、Ａｕ−Ｇａオーム性電極
１６ｂ 、 １７ｂとよりなる電極、１８ 、１９は正
孔チャネルにオーム性の一対の電極で、例えばｐ＋−Ｉ
ｎＧａＡｓ領域１８ｍ 、 １９ａとＡｕ −Ｚｎオー
ム電極１８ｂ。FIG. 1 shows the basic structure of a semiconductor device according to the present invention. Here, 11 is a high resistance substrate, 12 is a first semiconductor layer with low impurity density, for example, an undoped InGaAs layer, and 13 is a low impurity density layer that has a lower electron affinity than the first semiconductor and a larger sum of electron affinity and band gap. 14 is a p+ region, 15 is an n region, and 16, 17f'i is a pair of ohmic electrodes for the electron channel, for example, an n''-InGaA layer.
Electrodes 18 and 19 consist of s regions 16m and 17m and Au-Ga ohmic electrodes 16b and 17b, and electrodes 18 and 19 are a pair of ohmic electrodes for the hole channel, for example, p
nGaAs regions 18m, 19a and Au-Zn ohmic electrode 18b.
１９ｂとよりなる電極、２０はｐ領域１４へのオーム性
電極、２１はｎ＋領域１５へのオーム性電極で、ｐ＋領
域１４および電極２０とで正孔の注入電極を成し、ｎ
領域１５と電極２１とで電子の注入電極を成す。第２図
および第３図は電極２０下におけるバンドダイヤグラム
２示すもので、それぞれ熱平衡状態および電極２０に正
電圧を印加して正孔を注入した場合を示す。また第４図
および第５図は電極２１下におけるバンドダイヤグラム
を示すもので、それぞれ熱平衡状態および電極２１に負
電圧全印加して電子を注入した場合を示す。ここでＥＣ
＊ ＥＦ 、 ＥＶはそれぞれ伝導帯下端、フェルミレ
ベル、価電子帯上端のエネルギーレベルを表わす。20 is an ohmic electrode to the p region 14; 21 is an ohmic electrode to the n+ region 15; the p+ region 14 and the electrode 20 form a hole injection electrode;
The region 15 and the electrode 21 form an electron injection electrode. 2 and 3 show band diagrams 2 below the electrode 20, respectively, showing a thermal equilibrium state and a case where a positive voltage is applied to the electrode 20 and holes are injected. Further, FIGS. 4 and 5 show band diagrams under the electrode 21, respectively, showing a thermal equilibrium state and a case where a full negative voltage is applied to the electrode 21 and electrons are injected. EC here
*EF and EV represent the energy levels of the lower end of the conduction band, the Fermi level, and the upper end of the valence band, respectively.
さて第３図のように、第２の半導体層１３から、第１の
半導体層１２にかけて正孔を矢印のように注入すると、
電荷中性となる様に電子が誘起されるが、第２の半導体
層１３のほうが第１の半導体層１２より電子親和力が小
さいため、この電子はエネルギー的に低い、該第１と第
２の半導体層１２ 、１３のへテロ界面の第１の半導体
層側に蓄積され電子チャネルを形成する。この量は正孔
の注入量？増すほど増加し、導電性が極めて増大される
。一方第５図に示すように、電子を注入した場合も同様
に正孔が誘起される。この場合も第２の半導体層１３の
ほうが、第１の半導体層１２より、電子親和力とバンド
ギャップとの和が大きいため、この正孔もエネルギー的
に低い該第１と第２の半導体層１２ 、１３のへテロ界
面の第１の半導体層１２側に蓄積される。この鎗はやは
り電子の注入量を増すほど増加し、導電性が極めて増大
される。すなわち、同一の半導体へテロ接合界面に高導
電度の電子チャネルおよび正孔チャネルが形成されるこ
とが解る。Now, as shown in FIG. 3, when holes are injected from the second semiconductor layer 13 to the first semiconductor layer 12 in the direction of the arrow,
Electrons are induced to be charge neutral, but since the second semiconductor layer 13 has a lower electron affinity than the first semiconductor layer 12, these electrons are lower in energy than the first and second semiconductor layers. The electrons are accumulated on the first semiconductor layer side of the hetero interface between the semiconductor layers 12 and 13, forming an electron channel. Is this amount the amount of holes injected? The higher the value, the more the conductivity increases. On the other hand, as shown in FIG. 5, holes are similarly induced when electrons are injected. In this case as well, since the second semiconductor layer 13 has a larger sum of electron affinity and band gap than the first semiconductor layer 12, these holes are also lower in energy than the first and second semiconductor layers 12. , 13 on the first semiconductor layer 12 side. This spear also increases as the amount of electron injection increases, and the conductivity increases significantly. That is, it can be seen that highly conductive electron channels and hole channels are formed at the same semiconductor heterojunction interface.
ここで、これら電子チャネルおよび正孔チャネルを用い
る相補型インバータを構成し、電源電圧全印加した場合
を第６図に示す。ここで、電極１９ｂは正の電源に、電
極１６ｂは接地される。また３１はインバータの入力、
３２はインバータの出力である。ここでは注入されたキ
ャリアとチャネルのキャリアとの動きを矢印で示す。ま
ず入力３１に正電圧（Ｈレベル）が印加された場合を考
える。FIG. 6 shows a case where a complementary inverter using these electron channels and hole channels is constructed and the full power supply voltage is applied. Here, electrode 19b is connected to a positive power source, and electrode 16b is grounded. Also, 31 is the input of the inverter,
32 is the output of the inverter. Here, the movement of the injected carriers and the channel carriers is shown by arrows. First, consider the case where a positive voltage (H level) is applied to the input 31.
この時、電極２０からは正孔が電極１６のほうに向かっ
て注入され、電子チャネルが第１の半導体層１２中に形
成される。この電子はｎ型の電極１６と１７との間の電
界で電極１７の方へ加速され、電極１６と１７間は大電
流が流れ、オン状態となる。一方電極２１からは電子は
注入されず、電極１８と１９間には正孔チャネルは形成
されず、オフ状態である。すなわちインバータの出力は
零電位付近でＬレベルとなる。次に入力３１が零電位（
Ｌレベル）になった時には、以上とは逆に電極２１から
電子が電極１９の方に向かって注入され、正孔チャネル
が、第１の半導体層１２中に形成される。この正孔は、
ｐ型の電極１８と１９との間の電界で電極１８の方へ加
速され、電極１８と１９間は大電流が流れてオン状態と
なる。一方電極２０からは正孔は注入されず、電極１６
と１７間には電子チャネルは形成されず、オフ状態であ
る。すなわちインバータの出力は電源電圧付近でＨレベ
ルとなる。以上により良好なインバータ動作が実現され
る。At this time, holes are injected from the electrode 20 toward the electrode 16, and an electron channel is formed in the first semiconductor layer 12. These electrons are accelerated toward electrode 17 by the electric field between n-type electrodes 16 and 17, and a large current flows between electrodes 16 and 17, resulting in an on state. On the other hand, no electrons are injected from the electrode 21, no hole channel is formed between the electrodes 18 and 19, and the electrode 21 is in an off state. That is, the output of the inverter becomes L level near zero potential. Next, the input 31 is at zero potential (
(L level), contrary to the above, electrons are injected from the electrode 21 toward the electrode 19, and a hole channel is formed in the first semiconductor layer 12. This hole is
It is accelerated toward electrode 18 by the electric field between p-type electrodes 18 and 19, and a large current flows between electrodes 18 and 19, turning it on. On the other hand, no holes are injected from the electrode 20, and the electrode 16
An electron channel is not formed between and 17 and is in an off state. That is, the output of the inverter becomes H level near the power supply voltage. As described above, good inverter operation is realized.
さて、かかる動作状態において、電流の変調モードは、
正孔あるいは電子の注入による反対キャリアの誘起によ
る導電度変調であるが、チャネルは電界効果トランジス
タ（ＦＥＴ ）的である。すなわち、チャネルはへテロ
接合界面のバリアを利用した２次元的チャネルであシ、
しかもチャネルの第１の半導体層１２が低不純物密度で
あるため、正孔チャネルであってもチャネルは極めて高
速である。しかも構造はＦＥＴとほぼ同様なプレーナ型
である。また電極２０と電極１７問および電極２１と電
極１８間の第２の半導体層１３はＦＥＴと同様に空乏化
しており、従ってこれら電極間の帰還容量は小さい、す
なわち本装置によシ、２次元チャネルを有するＦＩＴと
同様な構造の簡単さ、高速性、小さな寄生抵抗および寄
生容量上さらに、バイポーラトランジスタ並の大電流駆
動能力を、電子チャネル素子および正孔チャネル素子と
も有し、高性能な相補型集積回路を実現するものである
。Now, in such an operating state, the current modulation mode is
The conductivity is modulated by inducing opposite carriers by injection of holes or electrons, but the channel is similar to a field effect transistor (FET). In other words, the channel is a two-dimensional channel that utilizes the barrier of the heterojunction interface.
Moreover, since the first semiconductor layer 12 of the channel has a low impurity density, the channel has extremely high speed even if it is a hole channel. Furthermore, the structure is a planar type that is almost similar to an FET. Further, the second semiconductor layer 13 between the electrode 20 and the electrode 17 and between the electrode 21 and the electrode 18 is depleted similarly to the FET, and therefore the feedback capacitance between these electrodes is small. In addition to having the same simple structure, high speed, and small parasitic resistance and capacitance as FITs with channels, they also have high current drive capability similar to that of bipolar transistors, as well as electron channel elements and hole channel elements, making them highly efficient complementary devices. It realizes a type integrated circuit.
ここで各チャネルの電流増幅率は、チャネルが高速であ
る程および、注入された電子あるいは正孔のチャネル域
からの流出が少い程大きくなる。Here, the current amplification factor of each channel increases as the channel speed increases and as the flow of injected electrons or holes from the channel region decreases.
このため、電流増幅率を改善する方法として、第７図の
ように、チャネルの第１の半導体層１２に接して、第２
の半導体層１３０反対側に、第１の半導体より、電子親
和力が小さく、かつ電子親和力とバンドギャップの和の
大きい高抵抗の第３の半導体層４１、例えばアンドープ
ＩｎＡｔＡｓを設けることが有効である。この場合の正
孔を注入した場合と、゛電子を注入し九場合とのバンド
ダイヤグラムをそれぞれ、第８図と第９図に示す。この
場合は注入正孔あるいは注入電子は第３の半導体層４１
によるバリアのために、結晶の奥の方（基板側）へ流出
することがない。さらに電子チャネルおよび正孔チャネ
ルも第３の半導体層４１によるバリアによって拡がるこ
とがなく、高速性が増し、電流増幅率が改善される。ま
たこの時出力抵抗も大きくなる効果もある。Therefore, as a method of improving the current amplification factor, as shown in FIG.
It is effective to provide a high-resistance third semiconductor layer 41, such as undoped InAtAs, which has a lower electron affinity and a larger sum of electron affinity and band gap than the first semiconductor, on the opposite side of the semiconductor layer 130. Band diagrams for the case in which holes are injected and the case in which electrons are injected are shown in FIGS. 8 and 9, respectively. In this case, the injected holes or injected electrons are transferred to the third semiconductor layer 41.
Because of the barrier caused by this, it does not leak to the back of the crystal (toward the substrate side). Further, the electron channel and hole channel are also prevented from spreading due to the barrier formed by the third semiconductor layer 41, increasing high speed and improving current amplification factor. Moreover, at this time, there is also the effect of increasing the output resistance.
以下に本発明の笑施例七示す。 Seven embodiments of the present invention are shown below.
（実施例１）
第１図において、基板１１としてＦｅ−ドープ半絶縁性
ＩｎＰ基板を用い、ＭＢＥ法にて第１の半導体層１２と
してキャリア密度ｌＸ１０１５ｃｆｎ−３厚さ３０００
Ｘのアンドープｎ″″−ＩｎＯ，ｇ Ｇａ０．４７Ａｓ
層、第２の半導体層１３として、キャリア密度Ｉ Ｘ
１０１５３−３、厚さ１０００ＸのアンドープＩｎ（１
，５２Ｇａ０．４６Ａｓ層を成長する。ｓｔのイオン注
入によｐ ｎ＋−ＩｎＧａＡｓ領域１６＆。(Example 1) In FIG. 1, an Fe-doped semi-insulating InP substrate is used as the substrate 11, and the first semiconductor layer 12 is formed by MBE with a carrier density of lX1015cfn-3 and a thickness of 3000.
X undoped n″″-InO,g Ga0.47As
layer, as the second semiconductor layer 13, the carrier density I
10153-3, undoped In(1
, 52Ga0.46As layer is grown. p n+ -InGaAs region 16 & by ion implantation of st.
１７ａ ｆ、またＺｎのイオン注入によｐ ｐ＋−Ｉｎ
ＧａＡａ領域１８ｍ 、 １９ａ ｆ形成する。さらに
Ｃｄの低エネルギーイオン注入によ＃） ｐ＋−ＩｎＡ
ｔＡｓ １４ ｔ−１Ｓｎの低エネルギーイオン注入に
よシｎ” −ＩｎＡｔＡ１１５を表面から７００１の深
さまで形成する。次いで電極１６ｂ 、 １７ｂ 、
１８ｂ 、 １９ｂ 、 ２０ 、２１をＡｕＧａ／ｐ
ｔを蒸着して形成する。以上のように製作した相補型
トランジスタを用いて、第６図のように形成したインバ
ータ回路は％Ｈレベル＋ＩＶ、Ｌレベル０．Ｉ Ｖで良
好に動作し、また各トランジスタの相互コンダクタンス
は電極幅当り２０００ｍ５／ｒｙｕｎ以上の高′亀流駆
動能力があった。17a f, and p p+-In by Zn ion implantation
GaAa regions 18m and 19af are formed. Furthermore, by low energy ion implantation of Cd, p+-InA
By low-energy ion implantation of tAs 14 t-1Sn, n''-InAtA 115 is formed to a depth of 7001 mm from the surface. Next, electrodes 16b, 17b,
18b, 19b, 20, 21 with AuGa/p
t is formed by vapor deposition. Using the complementary transistors manufactured as described above, an inverter circuit formed as shown in FIG. 6 has a %H level +IV and an L level 0. It operated well under IV voltage, and the mutual conductance of each transistor had a high current drive capability of 2000 m5/ryun or more per electrode width.
（実施例２）
第７図において、本実施例では実施例１に用いた、第１
の半導体層１２のＩ ｎＧａＡａ層Ｑ ２００Ｘと薄く
し、これを第３の半導体層４１として、キャリア密度５
Ｘ １０１０ｌ４’以上、抵抗率１０４Ω・譚以上の
高抵抗ｘｎｃＬ５２Ａｔｏ、４ａＡａ層２５０００Ｘの
基板１１側に入れたものである。これにより、実施例１
の構造に較べて電流増幅率、相互コンダクタンス、出力
抵抗が向上し次。(Example 2) In FIG. 7, in this example, the first
The InGaAa layer Q of the semiconductor layer 12 is made as thin as 200X, and this is used as the third semiconductor layer 41, and the carrier density is
The high resistance xncL52Ato, 4aAa layer 25000X with a resistivity of 1010l4' or more and a resistivity of 104Ω/tan or more is placed on the substrate 11 side. As a result, Example 1
The current amplification factor, mutual conductance, and output resistance are improved compared to the following structure.
以上の様に本発明によれば、ＦＥＴと同様な簡単な構造
で、高電流動作可能な相補型半導体装置が実現され高速
、高集積、低消費電力の高性能工Ｃｔ−実現できる効果
を有するものである。As described above, according to the present invention, a complementary semiconductor device capable of high current operation is realized with a simple structure similar to that of an FET, and has the effect of realizing a high-performance design with high speed, high integration, and low power consumption. It is something.
第１図は本発明による半導体装置の基本構造を示す断面
図、第２図、第３図は第１図の半導体装置の電極２０下
におけるバンドダイヤグラムを示す図、第４図、第５図
は第１図の半導体装置の電極２１下におけるバンドダイ
ヤグラムを示す図、第６図は第１図の半導体装置に電源
電圧を印加した場合の断面図、第７図は電流増幅率を改
善した場合の半導体装置の構造を示す断面図、第８図、
第９図は、第７図の半導体装置に正孔を注入した場合と
、電子を注入した場合とのバンドダイヤグラムをそれぞ
れ示す図である。
１１：高抵抗基板、１２：第１の半導体層、１３：第２
の半導体層、１４ ： ｐ”−領域、’ １５ ： ｎ
＋−領域、！６ 、１７ ： ｎ型オーム性電極、１８
、１９ ： ｐ型オーム性電極、２０：正孔注入用電
極、２１：電子注入用電極、３１：インバータ入力、３
２：インバータ出力、４１：第３の半導体層。FIG. 1 is a sectional view showing the basic structure of a semiconductor device according to the present invention, FIGS. 2 and 3 are band diagrams below the electrode 20 of the semiconductor device in FIG. 1, and FIGS. Figure 6 shows a band diagram under the electrode 21 of the semiconductor device shown in Figure 1, Figure 6 is a cross-sectional view when a power supply voltage is applied to the semiconductor device shown in Figure 1, and Figure 7 shows the case where the current amplification factor is improved. A cross-sectional view showing the structure of a semiconductor device, FIG.
FIG. 9 is a diagram showing band diagrams when holes are injected into the semiconductor device of FIG. 7 and when electrons are injected, respectively. 11: High resistance substrate, 12: First semiconductor layer, 13: Second
semiconductor layer, 14: p''-region, '15: n
+- area,! 6, 17: n-type ohmic electrode, 18
, 19: p-type ohmic electrode, 20: hole injection electrode, 21: electron injection electrode, 31: inverter input, 3
2: inverter output, 41: third semiconductor layer.
Claims (2)
体より電子親和力が小さく、かつ電子親和力とバンドギ
ャップとの和が大きい低不純物密度の第２の半導体層を
設け、該第２の半導体層に、正孔の注入電極と、電子の
注入電極とを設けたことを特徴とする相補型半導体装置
。(1) A first semiconductor layer with a low impurity density is provided with a second semiconductor layer with a low impurity density that has a smaller electron affinity than the first semiconductor and a larger sum of the electron affinity and the band gap, and A complementary semiconductor device characterized in that a hole injection electrode and an electron injection electrode are provided in the second semiconductor layer.
体より電子親和力が小さく、かつ電子親和力とバンドギ
ャップとの和が大きい低不純物密度の第２の半導体層と
、前記第１の半導体層に接して、該第２の半導体層の反
対側に設置した第１の半導体より、電子親和力が小さく
、かつ電子親和力とバンドギャップとの和の大きい高抵
抗の第３の半導体層とを備え、前記第２の半導体層に正
孔の注入電極と、電子の注入電極とを設けたことを特徴
とする相補型半導体装置。(2) a first semiconductor layer with a low impurity density, a second semiconductor layer with a low impurity density that has a lower electron affinity than the first semiconductor and a larger sum of the electron affinity and the band gap; a high-resistance third semiconductor layer having a lower electron affinity and a larger sum of electron affinity and band gap than the first semiconductor layer, which is in contact with the semiconductor layer and is placed on the opposite side of the second semiconductor layer; A complementary semiconductor device comprising: a hole injection electrode and an electron injection electrode provided in the second semiconductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60122226A JPH0758760B2 (en) | 1985-06-05 | 1985-06-05 | Complementary semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60122226A JPH0758760B2 (en) | 1985-06-05 | 1985-06-05 | Complementary semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61280675A true JPS61280675A (en) | 1986-12-11 |
| JPH0758760B2 JPH0758760B2 (en) | 1995-06-21 |
Family
ID=14830686
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60122226A Expired - Fee Related JPH0758760B2 (en) | 1985-06-05 | 1985-06-05 | Complementary semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0758760B2 (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5893380A (en) * | 1981-11-30 | 1983-06-03 | Fujitsu Ltd | Semiconductor device |
| JPS58130574A (en) * | 1982-01-29 | 1983-08-04 | Hitachi Ltd | Semiconductor device |
| JPS58147169A (en) * | 1982-02-26 | 1983-09-01 | Fujitsu Ltd | High electron mobility transistor |
-
1985
- 1985-06-05 JP JP60122226A patent/JPH0758760B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5893380A (en) * | 1981-11-30 | 1983-06-03 | Fujitsu Ltd | Semiconductor device |
| JPS58130574A (en) * | 1982-01-29 | 1983-08-04 | Hitachi Ltd | Semiconductor device |
| JPS58147169A (en) * | 1982-02-26 | 1983-09-01 | Fujitsu Ltd | High electron mobility transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0758760B2 (en) | 1995-06-21 |
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