JPS61277068A - Voltage detection circuit - Google Patents

Voltage detection circuit

Info

Publication number
JPS61277068A
JPS61277068A JP11850885A JP11850885A JPS61277068A JP S61277068 A JPS61277068 A JP S61277068A JP 11850885 A JP11850885 A JP 11850885A JP 11850885 A JP11850885 A JP 11850885A JP S61277068 A JPS61277068 A JP S61277068A
Authority
JP
Japan
Prior art keywords
voltage
constant current
gate
current source
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11850885A
Other languages
Japanese (ja)
Inventor
Jiro Koide
二郎 小出
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP11850885A priority Critical patent/JPS61277068A/en
Publication of JPS61277068A publication Critical patent/JPS61277068A/en
Pending legal-status Critical Current

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  • Measurement Of Current Or Voltage (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To widen an operation voltage range and to dispense with a circuit for generating reference voltage, by determining the magnitude of voltage by utilizing that the logical threshold voltage of a logical NOT gate is dependent on the voltage of a power source. CONSTITUTION:An integrating circuit 1' is held to an OFF-state during a period when a signal 100 is at a 'H' level and a transistor switch 8 is turned ON. In this state, the logical NOT gate input in a judge circuit 2' is fixed to a 'L' level and judge output 4' does not change. When the signal 100 comes to the '1' level, the transistor switch 8 is turned OFF and, at the same time, a constant current source control transistor 5 is turned ON and, therefore, the voltage with definite inclination determined by a constant current source 6 and the capacity value of a capacitor 7 is applied to the logical gate input in the judge circuit 2'. When a logical NOT gate logical threshold voltage level exceeds the terminal voltage of the capacitor 7, the logical gate output of the judge circuit 2' is reversed and a state is written in a D-latch 1.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はMO8半導体集積回路分野に於ける電圧検出回
路に関゛する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a voltage detection circuit in the field of MO8 semiconductor integrated circuits.

〔従来の技術〕[Conventional technology]

従来より電圧検出を目的とする回路はあった。 Conventionally, there have been circuits for the purpose of voltage detection.

しかし、それらの大半は基準電圧回路、検出電圧用分割
抵抗、比較器をもって構成される故に、回路規模が大き
くなったり、動作電源電圧が低くできない、回路が複雑
等の雑煮があった。
However, since most of them are configured with a reference voltage circuit, a detection voltage dividing resistor, and a comparator, there are problems such as an increase in circuit scale, an inability to lower the operating power supply voltage, and a complicated circuit.

さらに今日では電子機器全てか低消費電力化傾向にある
中で、少しでも消費電流が少ないものか好まれるのに対
し、従来方式ではその低消費電力化にも限度がある。
Furthermore, today there is a trend toward lower power consumption in all electronic devices, and while devices with as little current consumption as possible are preferred, there are limits to how low power consumption can be achieved with conventional methods.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

本発明は、上記従来技術に於ける諸問題のうち特に回路
の複雑化、動作電圧の制約の二点に関し解決をねらうも
のである。
The present invention aims to solve two of the problems of the above-mentioned prior art, particularly the complication of the circuit and the restriction of the operating voltage.

〔問題点を解決するための手段〕[Means for solving problems]

論理否定ゲート、空乏制御形MOSFET単体構成によ
る定電流源、及びコンデンサの3要素を有し、該MO8
IFI!!T単体構成定電流源のオン・オフ動作制御ト
ランジスタを、電源と該定電流源の一端との間へ直列接
続し、該定電流源の他端を一端接地され九該コンデンサ
の他端へ接続し、該コンデンサならびに該定1!光源と
の接続点に該論理否定ゲートの入力端を接続すると共に
、該論理否定ゲート入力端と接地間へ該コンデンサの放
電を目的とするトランジスタスイッチteけ、動作時に
は、該定電流源制御トランジスタをオンさせ同時に該コ
ンデンサ放電用トランジスタスイッチをオフさせること
により、初期電荷ゼロの該コンデンサが該定電流源に充
電され、一定時間経過の後、該コンデンサの端子電圧が
該論理否定ゲートの論理一値電圧を超すか超さないかで
、該論理否定ゲート出力を決定し、非動作期間中は該コ
ンデンサ放電用トランジスタスイッチをオンし、充電電
圧を放出させると同時に該定電流源制御トランジスタを
オフさせて該論理否定ゲート出力を強制的に一方向へ決
定させる構成をとり、該論理否定ゲートの論理一値電圧
が電源電圧に依存することを利用して電圧の大小を決定
することを特徴とする。
It has three elements: a logic inversion gate, a constant current source composed of a single depletion controlled MOSFET, and a capacitor, and the MO8
IFI! ! A transistor for controlling the on/off operation of a single constant current source is connected in series between a power supply and one end of the constant current source, and the other end of the constant current source is grounded at one end and connected to the other end of the capacitor. Then, the capacitor and the constant 1! The input end of the logic NOT gate is connected to the connection point with the light source, and a transistor switch for the purpose of discharging the capacitor is connected between the logic NOT gate input end and the ground, and when in operation, the constant current source control transistor By turning on the capacitor discharging transistor switch and turning off the capacitor discharging transistor switch at the same time, the capacitor with an initial charge of zero is charged by the constant current source, and after a certain period of time, the terminal voltage of the capacitor reaches the logic level of the logic NOT gate. The logical NOT gate output is determined by whether it exceeds the value voltage or not, and the capacitor discharging transistor switch is turned on during the non-operating period, and the constant current source control transistor is turned off at the same time as the charging voltage is discharged. The output of the logical NOT gate is forcibly determined in one direction, and the magnitude of the voltage is determined by utilizing the fact that the logical single value voltage of the logical NOT gate depends on the power supply voltage. do.

〔作用・実施例〕[Function/Example]

本発明の基本概念を第1図に示す。図中1は積分回路、
2は判定回路、5は制御回路、4は出力端子である。以
下本発明を具体的実施例に基づき詳細に説明する。
The basic concept of the present invention is shown in FIG. 1 in the figure is an integral circuit,
2 is a determination circuit, 5 is a control circuit, and 4 is an output terminal. The present invention will be described in detail below based on specific examples.

第2図は本発明の具体的実施例である。図中1′は積分
回路であシ、6が空乏制御形MOSFET定電流源、5
は60オン・オフ制御用トランジスタ、7はコンデンサ
である。2′は判定回路であり、9はPチャネルMOS
FET、10はNチャネルMO8IFKTで、論理否定
ゲートを構輯する。8は9,10で構成するゲート入力
を”0″レベルにすると共に、7のコンデンサ充電電荷
を放電させる役割をもつ、放電用トランジスタスイッチ
である。11はDラッチ、4′は判定出力端子である。
FIG. 2 shows a specific embodiment of the present invention. In the figure, 1' is an integrating circuit, 6 is a depletion-controlled MOSFET constant current source, and 5 is a depletion-controlled MOSFET constant current source.
60 is an on/off control transistor, and 7 is a capacitor. 2' is a judgment circuit, 9 is a P channel MOS
FET 10 is an N-channel MO8IFKT and constitutes a logic NOT gate. Reference numeral 8 denotes a discharging transistor switch which has the role of setting the gate input constituted by 9 and 10 to the "0" level and discharging the charge charged in the capacitor 7. 11 is a D latch, and 4' is a judgment output terminal.

3′は本システム動作に要する制御信号発生部、即ち制
御回路である。
Reference numeral 3' denotes a control signal generating section required for the operation of this system, that is, a control circuit.

次に実施例に基づき、各部の動作を説明する。Next, the operation of each part will be explained based on an embodiment.

図中φム〜φDはデジタル信号入力である。ここでは−
例としてφムwIHz、φBx512H2,φ0=2K
Hz、φD!4KHzの場合で説明する。
In the figure, φM to φD are digital signal inputs. Here -
For example, φmuwIHz, φBx512H2, φ0=2K
Hz,φD! The case of 4KHz will be explained.

各信号によって得られる各信号100〜104の関係を
第S図に示す。
The relationship between the signals 100 to 104 obtained by each signal is shown in FIG.

1′の積分回路は信号100が“R”レベルになってい
る期間オフ状態にあり、8のトランジスタスイッチがオ
ンしている。これより2′の判足回路内輪理否定ゲート
入力はL”レベルに固定され判定出力4′は変化しない
The integrating circuit 1' is in an off state while the signal 100 is at the "R" level, and the transistor switch 8 is on. From this, the input to the logic negation gate in the foot circuit 2' is fixed at the L'' level, and the judgment output 4' does not change.

ところが信号100が“L”レベルになると、8のトラ
ンジスタスイッチがオフし、と同時に5の定電流源制御
トランジスタがオンするゆえ、判定回路2′内の論理ゲ
ート入力は6の定電流源、7のコンデンサ容量値で決定
される一定傾斜の電圧V (t) =工・t / C・
・・・・・・・・(11が印加される。ここでIは定電
流源6の出力電流tは信号100がL″になっている時
間、Cはコンデンサ7の容量値である。6の定電流源出
力電aU、Il′1!!Tl1iil値電圧をv?8.
形状電流係数をβ;とすれば 工;β8(VT F’ )”/ 2  ・−・−・・−
・+2)で与えられ、電源電圧に全く依存しない。よ、
って(1)式のV (t)は次式のように書き表わせる
However, when the signal 100 goes to the "L" level, the transistor switch 8 turns off and at the same time the constant current source control transistor 5 turns on. A voltage with a constant slope determined by the capacitance value of the capacitor V (t) = t / C
(11 is applied. Here, I is the output current t of the constant current source 6 is the time during which the signal 100 is L'', and C is the capacitance value of the capacitor 7.6 The constant current source output voltage aU, Il'1!!Tl1iil value voltage is v?8.
If the shape current coefficient is β;
・+2) and does not depend on the power supply voltage at all. Yo,
Therefore, V (t) in equation (1) can be written as the following equation.

一方、2′の判定回路内輪理否足ゲートの論理一値電圧
vbは、トランジスタ9,10の各FETパラメータを
V’rP、 、βP11 e vT’10 p /”1
0 と定めれば式で与えられる。ここでVDDは、電源
電圧を表わす。(3)式から明らかなように、論理1l
llIlt電圧vbは電源電圧VDDの値によシ変化す
る。
On the other hand, the logical single-value voltage vb of the internal logic/failure gate in the judgment circuit 2' is expressed as V'rP, , βP11 e vT'10 p/"1
If it is set to 0, it can be given by the formula. Here, VDD represents the power supply voltage. As is clear from equation (3), logic 1l
The llIlt voltage vb changes depending on the value of the power supply voltage VDD.

従って、2′の判定回路が検出動作をする必須条件は 
V (t)≦vb・・・・・・・・・+4+・・・・(
4)   で与えられる。
Therefore, the essential condition for the judgment circuit 2' to perform the detection operation is
V (t)≦vb・・・・・・・・・+4+・・・(
4) is given by.

この時の状態変化は第5図中の信号t02,105゜1
06及び105のようになる。図中102は2Iの判定
回路へ伝達される1′の積分回路出力波形、106は(
3)式で表わされる論理否定ゲート論理一値電圧レベル
、105は(2)式に対応するコンデンサ7の端子電圧
変化である。105が106のレベルを超すと、判定回
路2′の論理ゲート出力は信号105のよう九反転し、
反転後のクロック(信号101〕によってDラッチ11
へ状態が書き込まれる。
The state change at this time is the signal t02, 105°1 in Fig. 5.
06 and 105. In the figure, 102 is the output waveform of the 1' integration circuit that is transmitted to the 2I judgment circuit, and 106 is (
3) The logical NOT gate logic single value voltage level expressed by the equation (2), 105 is the change in the terminal voltage of the capacitor 7 corresponding to the equation (2). When 105 exceeds the level of 106, the logic gate output of the judgment circuit 2' is inverted by nine as signal 105,
The D latch 11 is activated by the inverted clock (signal 101).
The status is written to.

以上が本発明の実施例に於ける各部の動作である。The above is the operation of each part in the embodiment of the present invention.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、次のような利点を生ずる。 According to the present invention, the following advantages are produced.

+11 6作電圧範囲が広くなる。特に論理回路で基本
構成を行なう故、0M08回路に於いてはPチャネルM
OSFET、1!チャネルMO8IPI!:’rのゲー
ト閾値電圧の和以上の電源電圧範囲で動作させ得る。
+11 6 The operating voltage range becomes wider. In particular, since the basic configuration is made of logic circuits, in the 0M08 circuit, P channel M
OSFET, 1! Channel MO8IPI! : Can be operated in a power supply voltage range that is greater than the sum of the gate threshold voltages of 'r.

(2)基準電圧発生のための回路が不要になる。(2) A circuit for generating a reference voltage becomes unnecessary.

実際には極めて電圧変動の影響が小さな基準電圧回路を
構成する方がよい事もある。しかしそのための回路構成
は複雑化し、尚かつ低い電圧でも動作可能となればさら
に煩雑化しがちである。本発明では極力簡素な電圧基準
を得るために、定電流値と動作期間の積と、コンデンサ
容量だけで決定できる方式とした。これにより非常に簡
略化され、また動作時間を変えるだけで検出電圧を変更
できるという利点をも同時に備えている。
In reality, it may be better to configure a reference voltage circuit that is extremely less affected by voltage fluctuations. However, the circuit configuration for this purpose becomes complicated, and if it becomes possible to operate at a low voltage, it tends to become even more complicated. In the present invention, in order to obtain a voltage reference that is as simple as possible, a method is adopted in which it can be determined only by the product of the constant current value and the operating period, and the capacitor capacity. This greatly simplifies the process, and also has the advantage that the detection voltage can be changed simply by changing the operating time.

製造過程でのゲート閾値電圧さえ管理されていれば、定
電流値、コンデンサ等、構成素子の形状寸法のみでアナ
ログ的動作部分の定数が決定されることも、重要な意未
をもつ。さらに定電流源用FETをPチャネル形にする
ことにより、判定用論理否定ゲートのPチャネル側?]
!!Tのゲート閾値電圧のバラツキが相殺される利点も
有している。
It is also important to note that as long as the gate threshold voltage is controlled during the manufacturing process, the constants of analog operating parts can be determined only by the constant current value, the shape and dimensions of the constituent elements such as capacitors, etc. Furthermore, by making the constant current source FET into a P-channel type, the P-channel side of the logic NOT gate for judgment? ]
! ! It also has the advantage that variations in the gate threshold voltage of T are canceled out.

(3)  回路占有面積、レイアウトの自由度により集
積化する場合に有利になる。
(3) It is advantageous for integration due to the circuit occupation area and freedom in layout.

従来方式の電圧検出回路では、検出用の分割抵抗を不純
物拡散等で形成していた。しかし抵抗の分割比を正確に
保つためにはできる限り直腺に配置して曲げ部分を減ら
す工夫を必要とした。それに加え、電流低減の為には抵
抗イ直そのものを大きくする必要があり、形状による制
約上不利になりがちであった。
In conventional voltage detection circuits, dividing resistors for detection are formed by impurity diffusion or the like. However, in order to keep the resistance division ratio accurate, it was necessary to arrange it as straight as possible and reduce the number of bent parts. In addition, in order to reduce the current, it is necessary to increase the resistance value itself, which tends to be disadvantageous due to constraints due to the shape.

これに対し本発明を用いれば、コンデンサが面積的に大
きめになるが、形状の制約゛を受けないため、回路自体
を1つのコンパクトなブロックとして扱うことができる
。よって集積化を図る場合、他の回路とバランスよくレ
イアウトする事が可能となる。
On the other hand, if the present invention is used, although the capacitor becomes larger in area, it is not subject to any shape restrictions, so the circuit itself can be treated as one compact block. Therefore, when integrating the circuit, it is possible to layout the circuit in a well-balanced manner with other circuits.

以上に記したような本発明の利点は、例えば電子時計へ
応用できる。特に電源電圧が絶えず増減するような太陽
電池式時計の電圧検出回路へ利用すれば、1回路により
多数の電圧検出゛レベルを設定でき、電池電圧表示等へ
幅広く対応できる。
The advantages of the present invention as described above can be applied to electronic watches, for example. In particular, if it is used in a voltage detection circuit for a solar-powered watch where the power supply voltage constantly increases or decreases, a single circuit can set a large number of voltage detection levels and can be used in a wide range of ways, such as displaying battery voltage.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の基本概念図、第2図は具体的実施例を
示す図、ggs図は谷部の動作寛圧決形図である。 1.1′・・・積分回路 2.2′・・・判定回路 3.5/・・・II御回路 4.4′・・・判定出力端子 以   上
FIG. 1 is a basic conceptual diagram of the present invention, FIG. 2 is a diagram showing a specific embodiment, and the ggs diagram is a diagram showing the operation relaxation pressure of the valley. 1.1'...Integrator circuit 2.2'...Judgment circuit 3.5/...II control circuit 4.4'...Judgment output terminal or higher

Claims (1)

【特許請求の範囲】[Claims] 論理否定ゲート、空乏制御形MOSFET単体構成によ
る定電流源、及びコンデンサの3要素を有し、該MOS
FET単体構成定電流源のオン・オフ動作制御トランジ
スタを、電源と該定電流源の一端との間へ直列接続し、
該定電流源の他端を一端接地された該コンデンサの他端
へ接続し、該コンデンサならびに該定電流源との接続点
に該論理否定ゲートの入力端を接続すると共に、該論理
否定ゲート入力端と接地間へ該コンデンサの放電を目的
とするトランジスタスイッチを設け、動作時には、該定
電流源制御トランジスタをオンさせ同時に該コンデンサ
放電用トランジスタスイッチをオフさせることにより、
初期電荷ゼロの該コンデンサが該定電流源に充電され、
一定時間経過の後、該コンデンサの端子電圧が該論理否
定ゲートの論理閾値電圧を超すか超さないかで、該論理
否定ゲート出力を決定し、非動作期間中は該コンデンサ
放電用トランジスタスイッチをオンし、充電電圧を放出
させると同時に該定電流源制御トランジスタをオフさせ
て該論理否定ゲート出力を強制的に一方向へ決定させる
構成をとり、該論理否定ゲートの論理一値電圧が電源電
圧に依存することを利用して電圧の大小を決定すること
を特徴とする電圧検出回路。
It has three elements: a logic negative gate, a constant current source composed of a single depletion controlled MOSFET, and a capacitor, and the MOS
An on/off operation control transistor of a constant current source composed of a single FET is connected in series between a power source and one end of the constant current source,
The other end of the constant current source is connected to the other end of the capacitor which is grounded, and the input end of the logic NOT gate is connected to the connection point between the capacitor and the constant current source, and the logic NOT gate input A transistor switch for the purpose of discharging the capacitor is provided between the end and ground, and during operation, the constant current source control transistor is turned on and the capacitor discharging transistor switch is turned off at the same time.
the capacitor with an initial charge of zero is charged by the constant current source;
After a certain period of time has elapsed, the logic NOT gate output is determined depending on whether the terminal voltage of the capacitor exceeds or does not exceed the logic threshold voltage of the logic NOT gate, and the capacitor discharging transistor switch is turned off during the non-operating period. The configuration is such that the constant current source control transistor is turned off and the constant current source control transistor is turned off to force the output of the logic NOT gate to go in one direction, and the logic single value voltage of the logic NOT gate is set to the power supply voltage. A voltage detection circuit characterized in that the magnitude of a voltage is determined by utilizing the dependence on the voltage.
JP11850885A 1985-05-31 1985-05-31 Voltage detection circuit Pending JPS61277068A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11850885A JPS61277068A (en) 1985-05-31 1985-05-31 Voltage detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11850885A JPS61277068A (en) 1985-05-31 1985-05-31 Voltage detection circuit

Publications (1)

Publication Number Publication Date
JPS61277068A true JPS61277068A (en) 1986-12-08

Family

ID=14738381

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11850885A Pending JPS61277068A (en) 1985-05-31 1985-05-31 Voltage detection circuit

Country Status (1)

Country Link
JP (1) JPS61277068A (en)

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