JPS6127671A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make the distance between source drain regions and channel stopper regions long enough as well as to make small the chip of a integrated circuit device, by a method wherein channel regions, source regions and drain regions are formed at low density regions which are provided at a semiconductor base plate. CONSTITUTION:Windows are opened by forming silicon oxide films 10 on the surface of an N type silicon base plate 1, and P type inpurities are injected. P type inpurities are diffused by high temperature heat treating, and inpurities regions 11 are deeply formed lower than the base plate 1. The surface of the regions 11 are covered with silicon oxide films 101, and windows are opened on films 101 and P type inpurities are diffused, and source regions 2 and drain regions 3 are formed, and windows are covered with silicon oxide films 10. Gate insulating films 4 are formed, and a MOS electrical field effect transistor is obtained providing gate electrodes 5, source electrodes 6 and drain electrodes 7. A channel stopper becomes a A part of the base plate 1, and sufficiently narrow width of it can be obtained, and the integrated density of the transistor can be made high.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device equipped with an MO8 field effect transistor, and particularly relates to a semiconductor device equipped with an MO8 field effect transistor, and in particular, an M
O8 field effect transistors and conventional MO field effect transistors consist of a source region and a drain region formed near the surface of a semiconductor substrate, and a gate insulating film formed on the surface of the semiconductor substrate over the source region and drain region. Further, metal electrodes are formed on the gate insulating film and in the source region and drain region, respectively. Furthermore, in the MO8 field effect transistor and its integrated circuit device tK used at high power supply, the surroundings of the source and drain and the MO8 field effect transistor are
A channel stopper is provided between the eight field effect transistors. In many cases, this channel stopper is a region having the same conductivity type as the semiconductor substrate and having a higher impurity concentration than the substrate.

Also, integrated circuit devices in which enhancement type and depletion type MO8 field effect transistors are formed on the same substrate are manufactured by several methods. For example, a method can be obtained by changing the type and thickness of the gate insulating film. There is a method of changing the conductivity type and impurity concentration of the semiconductor substrate under the gate insulating film using a doped oxide film or ion implantation technology.

Next, these conventional MO8 field effect transistors and their assembly S[rjJ path device will be explained with reference to the drawings.

First, as shown in FIG. 1(a), a source axis region 2 and a drain region 3 are formed near the surface of a semiconductor substrate 1.

Next, as shown in FIG. 141 (1), a channel stopper 8 is formed with a higher impurity concentration than the semiconductor substrate 1 at a required distance from the source region 2 and drain region 3.

As shown in Figure 1 (C), the dirt insulating film 4. Lease electrode5. Drain electricity @6. After forming the gate electrode 7, the MO
8 field effect transistors are obtained. Further, after the step shown in FIG. 1(b), a gate insulating film 4 is formed on the surface of the semiconductor substrate 1 spanning the source region 2 and drain region 3, as shown in FIG. 2(a).

As shown in Figure 2 (b), the required MO8 field effect transistor except the gate insulating film 4 is covered with a photosensitive resin 20, and the entire surface of the semiconductor substrate 1 is implanted with ion implantation to form a conductor opposite to that of the semiconductor substrate 1. Impurities that provide a type are implanted to invert the type of conductivity in the vicinity of the surface of the semiconductor substrate 9 under the gate insulating film 4. After that, as shown in FIG. 2(C), by considering the electrodes, an integrated circuit device having an enhancement type MO8 field effect transistor and a depression type MO8 field effect transistor on the same substrate is obtained. In the M08 field effect transistor having such a value, when forming the source region 2 and drain region 3 and the channel stopper 8 by the diffusion method, the source region 2 and the drain region 3 are formed in advance.
It is necessary to widen the distance between each of the channels and the channel stopper. That is, in the case shown in FIG. 3(a), the distance between the source region 2 or drain region 3 and the channel stopper 8 is shorter than the distance between the respective windows forming this distance.

It is approximately 50-90% of general VC/HL. Therefore, to obtain the distance l of 15r, 1 of e-tLfl/
I have to make it 0-100X longer. On the other hand, it is not possible to narrow fIms of the channel stopper 8 in advance because there is a Fi limit in the technology using a photosensitive resin film. Therefore, the distance between each of the source region 2 and drain region 3 and the channel stopper 8 is set to be long, −<
, 7 RU KEK M08% Field Effect - Transistors and their collections have the disadvantage of increasing the size of the chip of the circuit device. In an integrated circuit device, a line between two MO8O8 field effect transistors is formed on an insulating film on a semiconductor substrate, but if a channel stopper is provided under the wiring, the insulating film on the channel stopper must be made thicker by the same amount. For example, in the case of an integrated circuit device using a silicon substrate, there are many cases in which the channel stopper is formed by the diffusion method. Forming a film on the channel stopper requires thermal oxidation at high temperatures and for a long time. However, in this case, the channel stopper is further diffused and becomes wider.

As a result, there is the disadvantage that the chip of the integrated circuit device becomes larger.

This invention was made in order to eliminate the above-mentioned defects,
The I# feature is that it is possible to make the distance *' between the source region or drain region of the FiMO8 field effect transistor and the channel stopper sufficiently long, and it is also impossible to form a channel stopper with the required amplitude.
B field effect transistors and integrated circuit devices thereof can be made small in size, and an integrated circuit device having MO8 field effect transistors of the type MO8 and del John type can be easily manufactured on the same substrate.

The present invention 94 will be explained in detail below using the drawings.

As shown in FIG. 4(a), a silicon oxide film 10e is formed on the surface of a KN-type semiconductor substrate, for example, a silicon substrate l, and a window t is formed in a part of the silicon oxide layer on one part of the surface of the semiconductor substrate l. Have the section published.

Next, as shown in FIG. 4(b) Ic, an impurity is implanted using, for example, an ion implantation method to give a conductivity type opposite to that of the semiconductor substrate 1, that is, P type. The implanted impurity concentration is made higher than the impurity concentration of the N-type semiconductor substrate l. Next is 11! I;, 4
A heat treatment is performed to diffuse the impurity into the P-type semiconductor substrate 1, thereby forming a region 11 with impurity concentration lower than that of the N-type semiconductor substrate 1.

If the atmosphere is, for example, oxygen or water vapor during the 7ih thermal treatment, the surface of the low impurity concentration region 110 will be covered with silicon oxide@101. Next, as shown in FIG. 4(d) K, a window is opened in the silicon oxide film on the surface of the low impurity concentration region 11, and an impurity which gives the semiconductor base the opposite conductivity type, that is, the P type, is diffused. Then, a source region 2 and a drain region 3 are formed.

Cover the mackerel with a silicon oxide film 10. Next, as shown in FIG. 4(e), a gate insulating film 4 is formed by removing the silicon oxide film 10 on the semiconductor substrate 1 over the opening between the source region 2 and the drain layer 3. Then, as shown in FIG. As shown in FIG. 4(f), the gate electrode 5, the north electrode 6 and the drain electrode 7 are connected to -14''= on the gate electrode 1&layer 4 and on the source region 2 and drain region 3, respectively. A MO8 voltage boosting effect transistor can be obtained by providing .

In the MO8 field effect transistor obtained by the present invention as described above, the width of the channel stopper does not increase unnecessarily, and gK can be suppressed with a narrow hair cut.

The thickness of the silicon plated film on the chip size tube and channel stopper of MO8 field effect transistors and their integrated circuit devices.

It can be easily made thicker than other parts such as the drain region.

Furthermore, an integrated circuit device having enhancement type and depletion type eMMO8 field effect transistors on the same substrate can be easily obtained.

Next, examples of the present invention will be described.

In Figure 4(a), it is N type and the impurity concentration is lXl015.
A silicon oxide film 10 with a thickness of 5,000 to 15,000
It is formed by thermal oxidation, vapor phase growth, etc. to a thickness of A, and a window is opened by removing the silicon oxide film of the required area.

Next, when heat treatment is performed for 5 to 20 hours in an oxygen atmosphere at a high temperature of 1100 to 1200°0 as shown in Figure 4(b), the surface impurity concentration decreases to 5x10~ as shown in Figure 4(C).
5X1016tM-3, depth from the semiconductor substrate surface is 2
An N-type or P-type low impurity concentration region 11 of ~15 μm is obtained. In this case, the impurity concentration and conductivity type of the low impurity concentration region 11 can be selected depending on the ion implantation conditions, heat treatment conditions, etc. In this example, the N-type low impurity concentration region 117 with a depth of 4 to 8 μm is formed on the surface of the low impurity concentration Ii'1iPfi region 1 by high temperature heat treatment in oxygen.
Covered with OOA silicon oxide film. Next, Figure 4(d)
As shown in K, a window is opened in silicon oxide Jlu 101 and boron is diffused to form source region 2 and drain region 3.
form. After that, the windows opened for forming the source region and the drain region are covered with a silicon oxide film 101 by thermal oxidation.
Source region with a depth of 1.5-2.0μ2. A drain region 3 is obtained.

Thereafter, a gate insulating film 4 as shown in FIG. 4(e), for example, a silicon oxide film having a thickness of 1000 to 1 sooX is formed. Next, as shown in FIG. 4(f), the gate electrode 5. Source electrode 6
．． A MO8 field effect transistor is obtained by forming the train electrode 7 with A/. In this embodiment, the channel stopper is formed to maintain a minimum distance of 2 μ from each of the source region 2 and drain region 3. In the MO8 field effect transistor having this structure, the required threshold voltage can be obtained by the low impurity 11m region 11.

The breakdown voltage between each of the master source and drain and the channel stopper can also be obtained in the range of 10 to 50V.

In the above embodiment, the low impurity #1 degree region 9 was made of N type conductivity type, so that an MO8 field effect transistor with enhancement a was obtained; however, in other embodiments, the conditions for forming the low impurity concentration region 11 are A depletion type MO8 field effect transistor having a 92 is obtained.

Next, as another example, an MOi9 field effect transistor was manufactured under the same conditions as shown in FIGS. 4(a) to (f) using the same integrated circuit device Vc for forming a plurality of MO8 field effect transistors on the same substrate. An adjacent MO8 field effect transistor is shown in FIG.

In this figure, the channel stopper that blocks the MO8 field effect transistor next to it is As of the semiconductor substrate l, and a sufficiently narrow i width of 1 to 5μ, for example, can be obtained, and the integration density of the MO8 field effect transistor * 1-The conventional structure ha can also be increased.

Next, as shown in FIG. 7(a), another example is shown in which a silicon substrate of N type with an impurity concentration of 1 x 10"cm-" is used.
Silicon oxide film 10 on the surface of 30000~1500
Figure 7 (1) 0th order formed by thermal oxidation etc. by a thickness of 0X
), a plurality of windows are opened in the silicon oxide layer, and boron is implanted in an amount of 1 to 5×10 by ion implantation. Next, as shown in FIG. 7(c) 4C, all but one 6"J window is covered with a photosensitive resin film 20.

Boron is implanted in an amount of 5 to 10×IO3 by ion implantation. After that, remove the photosensitive resin for $20t and heat it at 1200°.
When heat treatment is performed for 10 to 20 hours in an oxygen atmosphere at a high temperature of 0, the result is as shown in FIG. 7(d). As shown in this figure, it is N type and has surface impurities of 1 to 5xlOcrn.
The area 11 and the surface impurities are 1 to 5×lOc! n
A P type region 91 and an N type region 92 are formed. After that, when fabricated under the same conditions as the steps shown in FIG. 4 (d3 to (f)), the enhancement type and depletion type M Os, wit, as shown in FIG. 7(e), are produced.
``An integrated circuit device having an r field effect transistor can be obtained.In this case too, the conventional manufacturing method
8 To form a field effect transistor, the following analogy is taken:
After forming the gate insulating film, the impurities and conductivity of the semiconductor substrate under the gate insulating film are removed by ion implantation. L! There is a method to obtain it by changing 1lff, but since the gate insulator M is removed in several steps, there is a risk that dirt may be mixed in. −
In the Rikiki invention, since the gate electrode can be formed in a short process after the gate insulating film is formed, contamination of the gate insulating film can be prevented with minimal aa.

In the MO8 field effect transistor and its integrated circuit device according to the present invention as described above, a channel stopper can be easily formed at any position with a minimum number of steps, and MO8 field effect transistors of conductivity types of enhancement type and depletion type can be formed. Whether singular or plural,
It has a special gIL that can be formed with high integration density. In addition to the above-mentioned power concentration example, the present invention also applies to MO8t, t'F effect transistor circuits, P-channel, N-channel type MOti-', d-field transistors and complementary transistors using P-type semiconductor substrates. Needless to say, it can be used for ff1MO8 field effect transistors, etc.

[Brief explanation of the drawing]

Figure 1 (a), (b) and (C), Figure 2 (a),
(b) and (C) A cross-sectional view of a conventional Fi MO8 field effect transistor during the manufacturing process. b), (C),
(d), (e) and <n are cross-sectional views during the 11th manufacturing process of the MO8 field effect transistor of the present invention. d) and (e)H are cross-sectional views of each example, and l is a semiconductor substrate. 2.2J), 2B is a source region, 3.3D, 311 drain region, 4.4D, 4Eh gate insulating film. 5.51), 5E is a gate electrode, 6. fi'D,6EF
i source electrode, 7, 7D, 7BFi drain electrode, 8 is a channel stopper, 9, 91, 92. ti is an inversion region, 10,101Fi silicon oxidation conversion, 11J- is a low impurity concentration region, and 20 is a photosensitive resin film, a region that acts as a channel stopper in the AFi semiconductor substrate.

Claims (1)

[Claims] a semiconductor substrate of one conductivity type, a low concentration region of the one conductivity type formed on the semiconductor substrate, and a channel region, a source region, and a drain region of another conductivity type formed on a surface portion of the low concentration region; A semiconductor device comprising a depletion type MOS field effect transistor having a gate electrode existing on the surface of the channel region between the source region and the drain region with an insulating film interposed therebetween.