JPS61276318A - Manufacture of compound semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a high heat-resistant electrode by interposing a thin layer doped with metal for suppressing surface level in high density between a compound semiconductor layer readily forming a surface level and an ohmic electrode made of high melting point metal or silicide when providing the electrode on the layer. CONSTITUTION:An N<+> type GaAs layer 2, an N-type GaAs layer 3, a P<+> type GaAs layer 4, an N-type AlGaAs layer 5 and an N<+> type GaAs layer 6 are sequentially laminated and grown by a molecular beam crystal growing method on a semi-insulating GaAs substrate 1. An Si is used for the N-type impurity element, a Be is used for the P-type impurity element, and the impurity densities of the layers 2, 3, 4, 5, 6 are respectively 1X10<19>, 3X10<16>, 5X10<18>, 5X10<17>, 1X10<19>/cm<3>. Then, an InGaAs layer 7 forming the feature of this method is adhered to the thickness of monomolecular layer on the layer 6 in density of 1X10<14>, and an emitter electrode 8 is formed of Mo, Au, WSi, etc. thereon. Thus, the electrode 8 having neither characteristic deterioration nor degradation of quality is obtained.

Description

[Detailed Description of the Invention] [Summary] Lattice defects are achieved by forming a monoatomic layer of a semiconductor layer that suppresses the formation of surface states using a molecular beam crystal growth method on the surface of a semiconductor where surface states are likely to be formed. A method of manufacturing an ohmic electrode without causing matching.

(Industrial Field of Application) The present invention relates to a method for manufacturing an ohmic electrode that is not affected by high temperature treatment during the manufacturing process.

In semiconductor devices, it is necessary to form ohmic electrodes, but since semiconductors and metals have different work functions,
In many cases, contact as it is causes a potential barrier, a so-called Schottky barrier, which exhibits rectifying properties.

Further, among various semiconductor materials, compound semiconductors are susceptible to surface levels, and therefore it is difficult to form ohmic electrodes.

In particular, it is difficult to form an ohmic electrode with gallium arsenide (GaAs) because its surface level exists at a high concentration in the middle of the forbidden band.

Various ohmic connection methods have been proposed to overcome this problem, but if there is high temperature treatment in the manufacturing process, the ohmic connection may be destroyed or the element characteristics may deteriorate, resulting in poor heat resistance. Excellent ohmic connections have not yet been put into practical use.

[Conventional technology]

Various configurations have been used to form ohmic electrodes.

The following is an explanation using GaAs, which is the most difficult ohmic connection, as an example.

■Precipitating a metal with a small difference in work function from the semiconductor material,
Alloyed by heat treatment.

For example, gold/germanium (A
(u-Ge) alloy is formed into a film by a vacuum evaporation method, Au is further vacuum evaporated thereon, and alloyed by heat treatment at about 450° C. for 30 seconds.

■Introducing impurity elements into the surface of the semiconductor layer to create a semiconductor layer with a high impurity content, thereby reducing the thickness of the Schottky barrier and creating an ohmic connection using a so-called tunneling current.

For example, Ga
A so-called non-alloy ohmic connection is realized by forming n+ GaAs1i heavily doped with tin (Sn) on an As semiconductor material, and then forming an electrode metal on top of this.

2) Connections without potential barriers are formed by continuously changing the surface composition of the semiconductor layer using the MBE method.

For example, using the MB2 method, InXGa is deposited on the surface of GaAs.
, -xAs (where X changes from O to 1) and indium (In) are created in a layer in which the concentration changes continuously, and an ohmic connection is achieved by bringing the electrode metal into contact with this top layer of InAsJi. .

However, these methods have the disadvantage that if high-temperature heat treatment is performed in the element manufacturing process after forming the ohmic electrodes, the electrode portions will deteriorate or change in quality.

In other words, alloying may progress too far and reach internal junctions (for example, p-n junctions), causing device failure, or highly doped impurity elements may diffuse and deteriorate characteristics, or lattice mismatch may occur. Misfit transition occurs due to this, and the characteristics deteriorate.

Specifically, in the manufacturing process of forming a petrojunction bipolar transistor (abbreviated as HBT) using a GaAs compound semiconductor, the base region is However, this requires annealing at 900°C.

However, there is a problem in that conventionally, there is no high heat-resistant ohmic electrode that can withstand this high temperature treatment, so it has not been put into practical use.

[Problem that the invention seeks to solve]

As explained above, the problem is that there is no highly heat-resistant ohmic electrode that does not cause deterioration or alteration of characteristics in the high-temperature treatment performed after forming the ohmic electrode.

[Means for solving problems]

The above problem is that surface states are easily formed, making it difficult to form ohmic electrodes.After forming an atomic layer doped with a metal for suppressing surface states at a high concentration on the surface of the semiconductor layer, a layer of electrode metal is formed. This problem can be solved by a method for manufacturing a highly heat-resistant ohmic electrode characterized by the following.

[Effect]

The present invention suppresses the formation of surface states on a semiconductor substrate and eliminates the effects of lattice mismatch by forming a semiconductor material on the substrate to be processed as thin as a single molecule. It is.

For example, if InGaAs is grown to a thickness of about a single molecule by the MB2 method on a substrate made of GaAs, G
The surface state density of aAs is suppressed, and there is a gap of about 7
% lattice mismatch, but the InGaAs layer is too thin to cause misfit transitions in the GaAs layer.

Specifically, in the case of GaAs, the surface state density is approximately 1013
cm-2, but as a method of suppressing this, GaAs (
Since the areal density of trivalent Ga ion sites on the 100) plane is 6.5 x 10 ``cm''''2, MB
IX 1014c In ion in As atmosphere by method 2
If InGaAs of a single molecule size is made by precipitating about m-2, the surface level becomes 0.3 eV or less, and ohmic connection becomes possible. In addition, InGaAs is thermally stable and can withstand heat treatment at about 900℃. can withstand it well.

〔Example〕

FIG. 1 is a cross-sectional view showing the stacked state of semiconductor layers when forming a GaAs HBT (heterojunction bipolar transistor), and FIG. 2 is a cross-sectional structural view of the HBT.

The manufacturing process of GaAs HBT according to the present invention will be explained as follows.

Set the semi-insulating GaAs substrate 1 on the MBE device and perform MBE.
By the method, the n'' GaAs layer 2, nGaAs
Layer 3. p”GaAs layer 4 + n AlGaAs layer 5
．． n'' GaAs layer 6 is formed, and an I layer according to the present invention is formed thereon.
The nGaAs layer 7 is formed to approximately a monomolecular layer.

Here, the n-type semiconductor contains silicon (Si) as an impurity element.
The p-type is formed by adding beryllium (B).
e).

Specifically, the impurity concentration of the n'' GaAs layer 2 is lX1.
0+9CI11-3, thickness l pm, nGaA
The s-layer 3 has an impurity concentration of 3X10'εcm-3 and a thickness of 3
000+p” GaAs layer 4 has an impurity concentration of 5 XIO
The impurity concentration of the nAlGaAs layer 5 is 5 x 10 cm-3 and the thickness is 2.
500 people, the impurity concentration of the n'' GaAs layer 6 is I x 1
0"cm-3 and thickness is formed under the condition of 2500 people.

In addition, the In concentration in InGaAsJii 7 is I
It is 1014 cm-2.

Next, an emitter electrode is formed on the InGaAs layer 7 thus formed using a high melting point metal or high melting point metal silicide such as molybdenum gold (Mo.Au) or tungsten silicide (WSi) as shown in FIG. form 8.

Next, after partially removing the InGaAs layer 7 and the n'' GaAs layer 6 by etching, magnesium (Mg) ions were implanted using the emitter electrode 8 as a mask until reaching the p'' GaAs layer 24, and then at 950°C.

Lamp annealing is performed for 5 seconds to activate the implanted Mg ions and form p+ region 9.

Note that the semiconductor layer up to the collector forming electrode position is n” Ga.
The As layer 2 is excluded.

In this state, gold-zinc (Au-Zn) alloy or the like is deposited on p+ region 9 to form base electrode 10.

Further, on the n'' GaAs layer 2, gold/germanium (A
After forming the collector electrode 11 by vapor depositing u-Ge) and Au, a heat treatment is performed at 450° C. for about 30 seconds to form an alloy. .

Although the HBT is formed in this way, the ohmic connection of the emitter electrode 8 is not affected by the heat treatment described above, and in this example, the contact resistance is 2X.
10-' Ωcm-2, and the high-speed performance of HBT can be fully demonstrated.

〔Effect of the invention〕

As described above, by carrying out the present invention, it becomes possible to form an ohmic electrode with high heat resistance, thereby contributing to the advancement of semiconductor devices.

[Brief explanation of the drawing]

Figure 1 is a semiconductor layer conductor layer structure diagram for GaAs flBT,
Figure 2 is a cross-sectional structural diagram of the HBT. In the figure, 1 is a semi-insulating GaAs substrate, 2 is an n'' GaAs layer, and 3 is a semi-insulating GaAs substrate.
is n GaAs layer, 4 is p” GaAs layer
layer, 5 is n AlGaAs layer, 6 is n''G
7 is an InGaAs layer; 8 is an emitter electrode; 9 is a p+ region; 10 is a base electrode; and 11 is a collector electrode.

Claims (1)

[Claims] A thin layer doped with a metal for suppressing surface states at a high concentration is formed on the compound semiconductor layer, an electrode made of a high melting point metal or its silicide is formed on the thin layer, and then heat treatment is performed. A method for manufacturing a compound semiconductor device.