JPS61273630A - Arithmetic processor - Google Patents

Abstract

PURPOSE:To decrease the hardware quantity by providing a normalized shifter which inputs the data obtained by connecting the outputs of plural registers and supplies the data output to one or plural registers. CONSTITUTION:When the result of an arithmetic part 11 is normalized, the result obtained from the part 11 is held by a register 13 with the data the extension accuracy less than a desired level. Then the shift degree is controlled to 0 by a shift degree control part 16, and the output supplied from a normalized shifter 15, i.e., the contents of the register 13 are held by a register 14. The shift degree needed for normalization is controlled by the part 16 based on the contents of the register 14. Then the output of the shifter 15, i.e., the data obtained after normalization are held by one or both or registers 13 and 14. The outputs of the registers 13 and 14 are sent to the next stage. When the data has the extension accuracy equal to a desired level, the upper and lower parts of the output data of the shifter 15 are held by the register 13 and one or both of registers 13 and 14 respectively. Then the outputs of both registers 13 and 14 are sent to the next stage. An arithmetic part 12 also receives the same procedure as that of the part 11.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a floating-point arithmetic processing device, and particularly to post-normalization.

[Conventional technology]

Conventionally, this type of arithmetic processing device, as shown in FIG.
A register 2 that holds intermediate results from the calculation unit 1, a register 3 that holds the output of register 2, and registers 2 and 3.
a normalization shifter 4 to which data concatenated with the outputs of the normalization shifter 4 is input, a register 5 that holds the output of the normalization shifter 4, and a shift amount control section that controls the shift amount of the normalization shifter 4 based on the contents of the registers 2 and 3. It was composed of 6.

The intermediate result from the calculation unit 1 before normalization is held in a register 2.3 or only in the register 3 depending on the data length, and the shift amount necessary for normalization is controlled by the shift control unit 6 according to the contents of the register. The normalized data from the normalization shifter 4 was held in the register 5, and its output was sent to the next stage.

[Problem that the invention seeks to solve]

The conventional arithmetic processing device described above does not include only one normalization device after arithmetic operations, but currently has multiple units for each of several arithmetic units in order to speed up arithmetic processing. There is a problem that the amount of hardware increases.

Furthermore, register 3 exists because of extended precision normalization, and does not operate independently.

Means for Solving Problem c] In order to solve such problems, the present invention provides a plurality of registers for holding intermediate results before normalization for each calculation unit,
There is a normalization shifter that receives data that is the concatenation of the outputs of multiple registers, and whose output is input to one register or multiple registers, and a normalization shifter that inputs the data that is the concatenation of the outputs of multiple registers, and the The shift amount of the normalization thick can be determined by selecting either the shift amount, the shift amount required to normalize the contents of one register, or any externally specified shift amount and sending it to the normalization thick. A shift amount control section for controlling the shift amount is provided.

[Effect]

In the present invention, the amount of hardware can be reduced by combining two or more normalization devices, which were conventionally required, into one.

〔Example〕

An embodiment of an arithmetic processing device according to the present invention is shown in FIG. In FIG. 1, 11.12 is a separate arithmetic unit, 13.14 is a long-precision register that holds the intermediate results of the arithmetic unit 11.12, and 15 is input data that is the concatenation of the outputs of registers 13.14. and the output is in register 13.1
a normalization shifter input to one or both of 4; 16;
is the amount of shift required to normalize the concatenated data of multiple register contents, the amount of shift required to normalize the contents of one register, or any shift amount specified externally. This is a shift amount control unit that controls the shift amount of the normalization shifter by selecting one of the following and sending it to the normalization shifter.

Next, the operation of the device configured as described above will be explained. When normalizing the result of the calculation unit 11, if the data is less than long precision, the result obtained from the calculation unit 11 is held in the register 13, and the shift amount normalization unit 16 controls the shift amount to “0”. Then, the output from the normalization shifter 15, that is, the contents of the register 13, is held in the register 14. The shift amount necessary for normalization is controlled by the shift amount control unit 16 according to the contents of the register 14, and the output of the normalization shifter 15, that is, the data after normalization, is held in one or both of the registers 13 and 14, The output of that register is sent to the next stage.

In the case of extended precision data, the lower part of the data is first held in register 13, and the contents are held in register 14 as in the case of data with long precision or less, and the lower part of the data is held in register 13.
3 holds the upper part of the data. and register 13.
14, the shift amount necessary for normalization is controlled by the shift amount control unit 16, and the output of the normalization shifter 15, that is, the upper part of the data after normalization, is held in the register 13, and the output is transmitted to the next stage. Furthermore, the shift amount control section 16 increases the shift amount by the data width of the register 13 from the previous time, and the output of the normalization shifter 15, that is, the lower order of the normalized data is held in one or both of the registers 13 and 14. and sends the output to the next stage.

In addition, when normalizing the result of the arithmetic unit 12, the result of the arithmetic unit 12 is held in the register 14 when the data is less than the long precision width, and in the registers 13 and 14 when the data is extended precision, and normalization is performed in the same way. .

〔Effect of the invention〕

As explained above, the present invention has a plurality of registers that hold intermediate results before normalization for each calculation unit, and data in which the outputs of the plurality of registers are connected are input, and the output is sent to one register or to a plurality of registers. The normalization shifter input to the register, the amount of shift required to normalize data that is a concatenation of multiple contents of this register, the amount of shift required to normalize the contents of one register, and the amount of shift required to normalize the contents of one register, specified externally. By providing a shift amount control unit that controls the shift amount of the normalization shifter by selecting one of the arbitrary shift amounts and sending it to the normalization thick, the normalization that conventionally required two or more This has the effect that the converting devices can be combined into one, and the amount of hardware is reduced. Another effect is that what has traditionally been an auxiliary register can be used more effectively. Furthermore, in addition to the normalization operation, it is also possible to perform operations such as data transfer between registers and transfer after shifting the required bit width.

[Brief explanation of drawings]

FIG. 1 is a system diagram showing an embodiment of an arithmetic processing device according to the present invention, and FIG. 2 is a system diagram showing a conventional arithmetic processing device. 11.12... Arithmetic unit, 13.14... Register, 15... Normalization thick, 16... Shift amount control unit.

Claims (1)

[Claims] In an arithmetic processing unit that has multiple arithmetic units for data represented by an exponent and a mantissa, multiple registers hold intermediate results before normalization for each arithmetic unit, and data concatenated with the outputs of these multiple registers. a normalization shifter, the output of which is input to one or more of the registers;
Which of the following: the amount of shift required to normalize data that is a combination of the contents of multiple registers, the amount of shift required to normalize the contents of one register, or any arbitrary shift amount specified from an external source. and a shift amount control unit that controls the shift amount of the normalization shifter by selecting and sending the selected data to the normalization shifter.