JPS61272953A - Cap for semiconductor device - Google Patents
Cap for semiconductor deviceInfo
- Publication number
- JPS61272953A JPS61272953A JP60114508A JP11450885A JPS61272953A JP S61272953 A JPS61272953 A JP S61272953A JP 60114508 A JP60114508 A JP 60114508A JP 11450885 A JP11450885 A JP 11450885A JP S61272953 A JPS61272953 A JP S61272953A
- Authority
- JP
- Japan
- Prior art keywords
- sealing
- semiconductor device
- cap
- glass
- sealing glass
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置用キャップに関し、１ｒ７ｆに低融
点の封着ガラスにより気密封止されるセラミックチップ
キャリア（ＬＣＣ）のキャップＫｌａする。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a cap for a semiconductor device, and relates to a cap for a ceramic chip carrier (LCC) that is hermetically sealed with a sealing glass having a low melting point.
従来、この種のキャップには、セラミックケースのシー
ルパス部と気密封止する為の封着ガラスがスクリーン印
刷法によルキャップの封止部に印刷され、その後作業温
度以下で焼成されてグレージングされている。このキャ
ップは、セラミックケースの外縁と同一、若しくは一回
シ小さい平板状のセラミック材が用いられている。Conventionally, for this type of cap, a sealing glass for airtight sealing with the seal pass part of the ceramic case is printed on the sealing part of the cap using a screen printing method, and then is fired and glazed at a temperature below the working temperature. ing. This cap is made of a flat ceramic material that is the same as or one size smaller than the outer edge of the ceramic case.
しかしながら、このようなキャップを使って半導体装置
を封止する際、下記の様な欠点が生じる。However, when such a cap is used to seal a semiconductor device, the following drawbacks occur.
これを第３図の従来の半導体装置の断面図を用いて説明
すると、一般に、この種のキャップを封止する際にはベ
ルト炉等を使用し、まずｌａ）図の加熱封止前の状態に
示すように％半導体素子１を固着しボンディングワイヤ
２を接続したセラミックケース３に、封着ガラス４をグ
レージングしたセラミックキャップ５を載置し、その上
からクリップで加重して徐々に加熱する。この様にして
、封着ガラス４の温度が封着ガラスの作業温度以上にな
ると、（ｂ）図に示すように、封着ガラスは溶融して４
′の状態になシ、半導体装置は正常に気密封止される。To explain this using the cross-sectional view of a conventional semiconductor device shown in FIG. As shown in the figure, a ceramic cap 5 with a sealing glass 4 glazed is placed on a ceramic case 3 to which a semiconductor element 1 is fixed and bonding wires 2 are connected, and the ceramic cap 5 is gradually heated by applying weight with a clip from above. In this way, when the temperature of the sealing glass 4 becomes higher than the working temperature of the sealing glass, the sealing glass 4 melts as shown in figure (b).
′, the semiconductor device is normally hermetically sealed.
この時、半導体装置内は、加重及び作業温度よシさらに
高いベルト炉の最高温度により、内圧が高くなる。さら
に粘度が低くカフた封着ガラスは、半導体装置内の気圧
により外に向けて流動し、（Ｃ）図に示すような従来の
欠点である４＃の状態となって引き下が）部（ボイド）
７を形成し、さらに内部の圧力が高い場合には、気体が
封着ガラス内部を通シ抜けて半導体装置外に逃げるため
、封着ガラス内に貫通孔を作る。この貫通孔拡、半導体
装置がベルト炉通過中に再び閉孔されるため、半導体装
置の気密性は維持される。しかし封着によるシールパス
部６は極所的に小盲〈なシ、半導体装置の封着強度の劣
化をもたらす原因となっている。At this time, the internal pressure inside the semiconductor device becomes high due to the load, the working temperature, and the higher maximum temperature of the belt furnace. Furthermore, the cuffed sealing glass, which has a low viscosity, flows outward due to the atmospheric pressure inside the semiconductor device, resulting in a 4# state, which is a drawback of the conventional method, as shown in Figure (C). void)
7, and when the internal pressure is high, a through hole is formed in the sealing glass so that gas can pass through the sealing glass and escape to the outside of the semiconductor device. Since the through hole is enlarged and then closed again while the semiconductor device passes through the belt furnace, the airtightness of the semiconductor device is maintained. However, the seal pass portion 6 caused by sealing is partially blind, which causes deterioration of the sealing strength of the semiconductor device.
上記の欠点は、半導体素子にポリイミド等の高分子樹脂
をコーティングした場合には顕著となる。The above-mentioned drawbacks become more noticeable when a semiconductor element is coated with a polymer resin such as polyimide.
これは、封着の除のベルト炉の加熱によ〕、高分子樹脂
からガスが発生する為である。あらかじめ樹脂は加熱さ
れキ具アされているが、これが年子１ｔ
公表場合には、樹脂の重合が封着の際に再軸行する。こ
うして発生したガスによル、半導体装置内の内圧は増加
し、前記欠点は一層顕著となる。This is because gas is generated from the polymer resin due to heating in the belt furnace during sealing. The resin is heated and sealed in advance, but if this is the case, the polymerization of the resin will re-axis during sealing. Due to the gas generated in this way, the internal pressure within the semiconductor device increases, and the above-mentioned drawback becomes even more noticeable.
本発明の半導体装置用キャップ扛、低融点封着カラスの
グレージング箇所あるいはグレージング箇所のわずか内
側Ｉ／ｃ％少なくとも１つ以上の貫通孔を有するもので
ある。The cap for a semiconductor device according to the present invention has at least one through hole at the glazing portion of the low melting point sealing glass or slightly inside the glazing portion I/c%.
第１図（ａ） 、 （ｂ）はそれぞれ本発明のキャップ
の実施例を示す断面図である。まずｌａ）図において、
セラミックキャップ５には、半導体装置内の気体を排出
する貫通孔８が、セラミックケースのシールパス部に対
応する箇所に少なくとも１個以上設けられ、この箇所を
含めたキャップ片面に１低融点の封着ガラス４がリング
状にグレージングされている。FIGS. 1(a) and 1(b) are sectional views showing embodiments of the cap of the present invention, respectively. First, in figure la),
The ceramic cap 5 is provided with at least one through hole 8 for discharging gas inside the semiconductor device at a location corresponding to the seal path portion of the ceramic case, and one side of the cap including this location is sealed with a low melting point. Glass 4 is glazed in a ring shape.
この貫通孔８は、気密性を損なわない程度の０．１〜０
．３■φの大きさが望ましく、セラミックケースのシー
ルバス部内に入るように配置する必要がある。また、封
着ガラスが溶融、流動する量が多い場合には、この流動
の範囲内に貫通孔８′が来るように、（ｂ）図の如く、
グレージングした封着ガラス４のわずか内側に設置すれ
ば良い。その位置は、封着ガラスの流動によ〕貫通孔８
′が閉孔される範囲であシ、シールパス部に接近してい
る必要がある。This through hole 8 has a diameter of 0.1 to 0.
．． A size of 3 mm is desirable, and it is necessary to arrange it so that it fits inside the seal bath part of the ceramic case. In addition, if the sealing glass melts and flows in a large amount, the through hole 8' should be placed within the range of this flow, as shown in Figure (b).
It may be installed slightly inside the glazed sealing glass 4. Its position is determined by the flow of the sealing glass] through hole 8
' must be within the range where the hole is closed, and must be close to the seal path.
第２図は本発明のキャップを用いた半導体装置の断面図
である。すなわち、セラミックキャップ５とセラミック
ケース３を（ａ１図のように封止前の状態に重ね合わせ
、ベルト炉を通過させると、封着ガラス４は封着作業温
度以上になった時点で溶融が始まる。その後、ベルト炉
の最高温度若しくはポリイミド等によル発生したガスに
よって半導体装置内の気圧は上昇し、ここで（ｂ）図に
示すように加熱板封止状態となシ、気体は溶融した封着
ガ −ラス４を押しのけて進み、通シ抜けＫよる引き
下が）部９を形成し、シールパス部６に対応する箇所に
設けられた貫通孔８により、半導体装置外へ排出される
。その後、温度上昇に伴う気体の排出が続くが、気体の
内外圧力差が緩和されれば、クリップに、にる加重によ
、り （ｃ）図に示すように封着ガラス４はシールパス
部６を一様に封着し、貫通孔８をも封止して気密封止が
完成する。FIG. 2 is a sectional view of a semiconductor device using the cap of the present invention. That is, when the ceramic cap 5 and the ceramic case 3 are overlapped in the state before sealing (as shown in Figure A1) and passed through a belt furnace, the sealing glass 4 begins to melt when the temperature reaches the sealing operation temperature or higher. After that, the pressure inside the semiconductor device increases due to the maximum temperature of the belt furnace or gas generated by polyimide, etc., and the heating plate is sealed as shown in Figure (b), and the gas melts. The sealing glass 4 is pushed aside, the sealing glass 4 is pushed aside, and the sealing glass 4 is pulled down by the through-hole K to form a section 9, which is discharged to the outside of the semiconductor device through a through hole 8 provided at a location corresponding to the sealing pass section 6. Thereafter, the gas continues to be discharged as the temperature rises, but once the pressure difference between the inside and outside of the gas is alleviated, the sealing glass 4 is moved to the seal pass portion 6 as shown in the figure (c). are uniformly sealed, and the through hole 8 is also sealed to complete hermetic sealing.
以上説明したように１本発明は半導体装置用キャップ低
融点ガラス封着部に貫通孔を設けるととＫよシ、半導体
装置内の気圧を抑制し、半導体装置内の気圧上昇に伴う
シールパス部の封着ガラスの引き下がシを回避すること
ができるので封着強度の安定した半導体装置を得ること
ができる。As explained above, one aspect of the present invention is that by providing a through hole in the low melting point glass sealing part of a cap for a semiconductor device, the air pressure inside the semiconductor device can be suppressed, and the seal pass part can be reduced as the air pressure inside the semiconductor device increases. Since pulling down of the sealing glass can be avoided, a semiconductor device with stable sealing strength can be obtained.
さらに本発明はＬＣＣのキャップに限らず、セラミック
キャップを用いてカラス封着するパッケージ全般に適用
できることはもちろんである。Furthermore, it goes without saying that the present invention is applicable not only to LCC caps but also to any package that is glass-sealed using a ceramic cap.
＃！１図（ａ） 、 （ｂ）はそれぞれ本発明の半導体
装置用キャップの実施例を示す部分断面図、第２図は本
発明の半導体装置用キャップを用いた半導体装置の断面
図で、（ａ）が加熱封止前、（ｂ）が加熱板封止中、（
ｃ）が気密封止完成の状態をそれぞれ示す、第３図は従
来の半導体装置用キャップを用いた半導体装置の断面図
で、（ａ）が加熱封止前、（ｂ）が正常な気密封止状態
、（ｃ）が欠点を示す図である。
１・・・・・・半導体素子、２・・・・・・ボンディン
グワイヤ、３・・・・・・セラミックケース、４・・・
・・・封着ガラス、５・・・・・・セラミックキャップ
、６・・・・・・シールパス部、７・・・・・・封着ガ
ラス引き下が）部（ボイド）、８・・・・・・貫通孔、
９・・・・・・気体の通シ抜けＫよる引き下がシ部。
葛ｆ図
第２図#! 1(a) and 1(b) are partial cross-sectional views showing embodiments of the semiconductor device cap of the present invention, and FIG. 2 is a cross-sectional view of a semiconductor device using the semiconductor device cap of the present invention. ) before heat sealing, (b) during heating plate sealing, (
c) shows the completed state of hermetic sealing, and Figure 3 is a cross-sectional view of a semiconductor device using a conventional cap for semiconductor devices, where (a) is before heat sealing and (b) is normal hermetic sealing. It is a figure which shows a defect in a stopped state and (c). 1... Semiconductor element, 2... Bonding wire, 3... Ceramic case, 4...
...Sealing glass, 5...Ceramic cap, 6...Seal pass section, 7...Sealing glass pull down part (void), 8... ...through hole,
9...The part that is pulled down due to the passage of gas K. Kuzu f figure 2
Claims (1)
置に用いるキャップにおいて、封着ガラスのグレージン
グされた箇所に少なくとも１つ以上の貫通孔が設けられ
ていることを特徴とする半導体装置用キャップ。 ２、封着ガラスのグレージングされた箇所よりわずか内
側に貫通孔が設けられていることを特徴とする特許請求
の範囲第１項記載の半導体装置用キャップ。[Claims] 1. In a cap used for a semiconductor device hermetically sealed with a low melting point sealing glass, at least one through hole is provided in a glazed area of the sealing glass. Features of caps for semiconductor devices. 2. The cap for a semiconductor device according to claim 1, wherein a through hole is provided slightly inside the glazed portion of the sealing glass.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60114508A JPS61272953A (en) | 1985-05-28 | 1985-05-28 | Cap for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60114508A JPS61272953A (en) | 1985-05-28 | 1985-05-28 | Cap for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61272953A true JPS61272953A (en) | 1986-12-03 |
Family
ID=14639512
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60114508A Pending JPS61272953A (en) | 1985-05-28 | 1985-05-28 | Cap for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61272953A (en) |
-
1985
- 1985-05-28 JP JP60114508A patent/JPS61272953A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS61272953A (en) | Cap for semiconductor device | |
| CN110707199A (en) | Deep ultraviolet LED device and packaging method thereof | |
| JPH04271146A (en) | Airtight microchip package and its sealing method | |
| CN210743971U (en) | Deep ultraviolet LED device | |
| JP2564104Y2 (en) | Cap for semiconductor device sealing | |
| JP2823063B2 (en) | Method for manufacturing semiconductor device | |
| JP2731156B2 (en) | Glass sealing method for lead wire | |
| JPS61256656A (en) | Semiconductor device | |
| JPH05314906A (en) | Display tube | |
| CN214032262U (en) | Composite sealing glass device | |
| JPH09199623A (en) | Lid substrate for electronic part package | |
| JPS6329555A (en) | Sealed electronic device | |
| JPH04171966A (en) | Manufacture of semiconductor device | |
| JPS60241236A (en) | Semiconductor device | |
| US5237206A (en) | Low-melting point glass sealed semiconductor device and method of manufacturing the same | |
| JPS6169152A (en) | Semiconductor device | |
| JPS5998538A (en) | Manufacture of semiconductor device | |
| JPH01319970A (en) | Vessel for sealing semiconductor device | |
| JPS5852855A (en) | Cap bonding | |
| JPH02125640A (en) | Hollow package | |
| JPH02144942A (en) | Manufacture of semiconductor device | |
| JPH0455332B2 (en) | ||
| JPH01130548A (en) | Semiconductor device | |
| JPS6020445A (en) | Lamp | |
| JPH01176625A (en) | Manufacture of lamp |