JPS61271847A - Electronic device - Google Patents
Electronic deviceInfo
- Publication number
- JPS61271847A JPS61271847A JP60113166A JP11316685A JPS61271847A JP S61271847 A JPS61271847 A JP S61271847A JP 60113166 A JP60113166 A JP 60113166A JP 11316685 A JP11316685 A JP 11316685A JP S61271847 A JPS61271847 A JP S61271847A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- substrate
- chip
- resin
- reliability
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、集積回路を搭載した電子装置に係り、特に、
接続部の信頼性の高い電子装置に関する。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an electronic device equipped with an integrated circuit, and in particular,
This invention relates to electronic devices with highly reliable connections.
近年、集積回路の大規模化が進み、チップの大型化、接
続点数の増大が進んでおり、このエラな集積回路の信頼
性に、接続部の信頼性が大きな影響を及ぼす様になった
。また、機器の小形、軽量化が進められており、チップ
搭載電子装置のスペース縮少がもう一つの重要課題とな
っている。In recent years, the scale of integrated circuits has been increasing, chips have become larger, and the number of connection points has increased, and the reliability of the connection parts has come to have a great influence on the reliability of these faulty integrated circuits. Furthermore, as devices are becoming smaller and lighter, reducing the space for chip-mounted electronic devices has become another important issue.
集積回路が形成されたチップを、接続用電極が形成され
た基板ＶＣｔ気的接続を行って作る電子装置の場合、ス
ペースファクター金考慮して、直接チップを基板上に接
続する方法がとられる。In the case of an electronic device in which a chip on which an integrated circuit is formed is electrically connected to a substrate VCt on which connection electrodes are formed, a method is used in which the chip is directly connected to the substrate, taking into consideration the space factor.
この場合、第５図及び第４図のように、導線を用いて接
続するワイヤボンデング法と、第５図及び第６図のよう
に低融点金属（ハンダ）で直接接続する方法と７５ｉ、
ｆｉる。しかして、第５図及びＷｃ５図は前記従来例の
平面図であり、第４図及び第６図はそれぞれ相当する縦
断面図でろる。In this case, as shown in FIGS. 5 and 4, there is a wire bonding method for connecting using conductor wires, a method for directly connecting using a low melting point metal (solder) as shown in FIGS. 5 and 6, and 75i.
Firu. 5 and 5 are plan views of the conventional example, and FIGS. 4 and 6 are corresponding longitudinal sectional views, respectively.
各図において、符号１は集積回路形成チップ、２は配線
基板、５はハンダ接続部、４は電極端子、５け導電線材
、６は接合部材を意味する。In each figure, reference numeral 1 indicates an integrated circuit forming chip, 2 indicates a wiring board, 5 indicates a solder joint, 4 indicates an electrode terminal, 5 conductive wires, and 6 indicates a joining member.
ワイヤボンデング法がよく用いられているが接続点数が
端子数の２倍となり、しかも一括作業とはならないため
、大規模な集積回路では、接続工程に時間がかかること
になる。その上、接続個所が多い分だけ接続部の信頼性
確保が難しくなる。その点で、一括接続の技術が確立さ
れている（ ＣＣＢ法）後者では、スペースファクター
も小さく、数多くの特長を有している。しかしながら、
まだ十分実用化されていない。これは、長期に亘る冷熱
サイクルによるハンダ接続部の信頼性低下が大きな理由
である。Wire bonding is often used, but since the number of connection points is twice the number of terminals and it cannot be done all at once, the connection process takes time in large-scale integrated circuits. Furthermore, the more connections there are, the more difficult it becomes to ensure the reliability of the connections. In this respect, the latter method, which has an established batch connection technology (CCB method), has a small space factor and has many advantages. however,
It has not been fully put into practical use yet. The main reason for this is that the reliability of the soldered joints decreases due to long-term cooling and heating cycles.
従来、ＣＣＢ接続の信頼性全向上させることは難しく、
防湿などを目的として、樹脂被覆を行う場合にも、でき
るだけ、ハンダ接続部の冷熱サイクル寿命を低下させな
いような工夫がなされてきた。例えば、特開昭５８−２
０４５４６号、同５７−２０８１４９号、同５８−１３
４４４９号各公報４どに開示されているＬうに、第７図
及び第８図に示したごとく、ＬＳＩチップと基板が作る
間隙に樹脂を充てんしない構造がとられた。当然、特開
昭５７−２０８１４９号、実開昭５８−１８！５４８号
各公報に見られるように、従来技術として間＊’を充て
んする形の構造が開示されているが、用いる樹脂の物性
に対する特定がなされておらず接続部の断ａｔ加速する
ものと′され、第７図及び第８図のごとき改良案が出さ
れたものである（特開昭５７−２０８１４９号公報）。Conventionally, it has been difficult to fully improve the reliability of CCB connections,
Even when resin coating is applied for the purpose of moisture proofing, efforts have been made to minimize the reduction in the thermal cycle life of the solder joints. For example, JP-A-58-2
No. 04546, No. 57-208149, No. 58-13
As shown in FIGS. 7 and 8, as disclosed in each publication of No. 4449, a structure was adopted in which the gap formed between the LSI chip and the substrate was not filled with resin. Naturally, as seen in Japanese Patent Application Laid-Open No. 57-208149 and Japanese Utility Model Application No. 58-18! However, it was assumed that this would accelerate the disconnection of the connection, and an improvement plan as shown in FIGS. 7 and 8 was proposed (Japanese Patent Laid-Open No. 57-208149).
また、実開昭５８−１８５４８号公報では、樹脂の物性
に対する特定がないだけでなく、充てんをスムーズに行
うため、ガラス基板に孔を明けて、そこから充てんする
という考案であるが、このような構造では、冷熱サイク
ルのストレスにニジ、ガラスに明けられた孔周辺圧クラ
ックが発生することは明らかであり、実用性に問題があ
る。In addition, in Japanese Utility Model Application Publication No. 58-18548, not only is there no specification regarding the physical properties of the resin, but the idea is to make a hole in the glass substrate and fill it from there in order to fill it smoothly. With such a structure, it is clear that pressure cracks around the holes in the glass will occur due to the stress of the cooling and heating cycles, which poses a problem in practicality.
特開昭５８−１０５１４５号公報にも同様の技術が開示
されているが、やはり、用いる樹脂の物性ｔ−％定して
いないので、ハンダ接続の信頼性向上を保証し得るもの
ではない。A similar technique is disclosed in Japanese Patent Application Laid-Open No. 58-105145, but since the physical properties of the resin used in t-% are not determined, improvement in reliability of solder connection cannot be guaranteed.
ところで、第７図（平面図）及び第８図（縦断面図）の
ような改良案では、ハンダ接続部の冷熱サイクル信頼性
は、低下させないかも知れないが、加湿試験を行うと、
空隙部に、水分が堆積し、接続部の腐食を引起すため、
民生用など気密封止せずに使われる電子装置としては不
十分である。By the way, in the improvement plans as shown in Fig. 7 (plan view) and Fig. 8 (longitudinal cross-sectional view), the cooling and heating cycle reliability of the soldered joint may not deteriorate, but when a humidification test is performed,
Moisture accumulates in the voids, causing corrosion of the connections.
This is insufficient for electronic devices used without hermetically sealing, such as for consumer use.
その点を、改善する提案と思われるのが特開昭５８−１
０８４１号公報に見られるもので、間隙部に軟質の樹脂
を充てんする構造である。JP-A-58-1 seems to be a proposal to improve this point.
This is seen in Japanese Patent No. 0841, and has a structure in which the gap is filled with a soft resin.
しかしこの方法は従来技術と同様、ハンダ接続部の冷熱
サイクル寿命を低下させる。これは、軟質樹脂が一般に
熱膨脹係数が非常に大きいことによる。However, this method, like the prior art, reduces the thermal cycle life of the solder joint. This is because soft resins generally have a very large coefficient of thermal expansion.
以上のように、ＣＯＢ法により実装されたＬＳＩチップ
を搭載した電子装置については、種々、信頼性向上のた
めの提案がなされているにもかかわらず、その効果は不
十分であるか、あるいは実用性に乏しい構造にとどまっ
ていた。As mentioned above, although various proposals have been made to improve the reliability of electronic devices equipped with LSI chips mounted using the COB method, their effects are insufficient or are not practical. It remained in a structure lacking in gender.
本発明は、こういった情勢にかんがみて、Ｃ！ＯＢ接続
実装について、従来欠点とされてきた長期信頼性を保証
し得る構造をもつ装置ｔを提供することを目的としたも
のである。In view of these circumstances, the present invention provides C! The purpose of this invention is to provide a device t having a structure that can guarantee long-term reliability, which has been considered a drawback in the past with regard to OB connection mounting.
本発明全概説すれば、本発明は電子装置に関する発明で
あって、複数個のハンダバンプを備え電子回路が形成さ
れてなるＬＳＩチップと、配線を形成している基板とか
らなり、該ＬＳＩチップと該基板とが該ハンダバンプを
介してハンダ接合されてなる電子装置において、該ＬＳ
Ｉチップと該基板とが作る間隙が、せん断弾性率が該ハ
ンダのそれ工りも大きい硬質の有機高分子材料により接
着光てんされていること全特徴とする。To summarize the present invention, the present invention relates to an electronic device, which comprises an LSI chip including a plurality of solder bumps and on which an electronic circuit is formed, and a substrate on which wiring is formed. In an electronic device in which the substrate is solder-bonded via the solder bump, the LS
A complete feature is that the gap formed between the I-chip and the substrate is bonded with a hard organic polymer material whose shear modulus is greater than that of the solder.
る。Ru.
ＯＣ８接続法が冷熱サイクルに工って破壊されるメカニ
ズムについて、実験及び解析を進めた結果、チップと、
電極基板との熱膨脹係数差による熱応力をハンダ層が受
け、接続部界面に繰返しのせん断応力が加わることによ
り、界面近傍でハンダ層のせん断疲労破壊が起り、断線
に至ることが判り、本発明に到つ九ものである。As a result of conducting experiments and analysis on the mechanism by which the OC8 connection method is destroyed due to cooling and heating cycles, we found that the chip and
It was found that the solder layer receives thermal stress due to the difference in coefficient of thermal expansion with the electrode substrate, and repeated shear stress is applied to the connection interface, causing shear fatigue failure of the solder layer near the interface, leading to wire breakage. There are nine things that reach .
最も単純な解決法は、チップと電極基板の熱膨脹係数を
合せることでめるが、実用的に考えると電極基板が限ら
れたものとなり、現実性に乏しい。The simplest solution is to match the coefficients of thermal expansion of the chip and the electrode substrate, but from a practical standpoint, the number of electrode substrates is limited and this is impractical.
両者の熟Ｊｌｌｌｌ係数差全容認した上で、信頼性を向
上嘔せるためには、ハンダの疲労限界強度金高くするこ
とが考えられるが、これも一般的なハンダの物性から考
えると現実性がない。In order to improve reliability, it is possible to increase the fatigue limit strength of the solder while accepting the full difference in the coefficient of aging between the two, but this is also not realistic considering the physical properties of general solder. do not have.
そこで、上記制約をすべて容認した上で、信頼性全向上
させる方法を講する必要かめる訳で、本発明は、その手
段全見出した結果生れたものである。Therefore, it is necessary to take a method to completely improve reliability while accepting all of the above-mentioned restrictions, and the present invention was created as a result of finding all the means to do so.
ハンダのせん断疲労による破断全抑えるためには、ハン
ダの受けるせん断変形ｔｔ−小さくすれば良いことは明
らかでめる。せん断変形を受けなければ疲労することは
ないからでおる。それを達成するには、チップと基板と
が作る！２！隙をせん断弾性率がハンダよりも大きい硬
質の絶縁材料で、充てんし、かつ、それがチップ及び基
板と接着している状ｇを作れば良いことが判った。すな
わち第１図（平面図）及び第２図（縦断面図）の構造で
ある。各図において、符号１〜５は第５図と同義であり
、７は樹脂材料を意味する。このエラな構造を作る罠は
、チップを接続後、流動性のある合成ｍｍｔ−間！ｉＫ
導入し、所定の温度で硬化して、硬質の樹脂層とする方
法がとられる。この構造は樹脂光てんによって、実装ス
ペースが増大することを防止できる点でも、従来ニジ優
れた構造である。こりすることによって、関１！ｉ＃全
体のせん断変形量は、樹脂層の変形量に支配されること
になり、樹脂が充てんされていない場合に比べて、その
値は著しく小さくできることになる。一方、特開昭５８
−１０８４１号公報に開示されているぶつな軟質の樹脂
層では、この工うｌ効果は期待できないことは容易に想
偉できる。少なくともハンダのせん断弾性率（約５００
ｋ＆ｆ／＋ａ＋” ）よりも大きいことが望ましい。It is clear that in order to completely suppress the solder from breaking due to shear fatigue, the shear deformation (tt) to which the solder is subjected should be reduced. This is because fatigue does not occur unless it is subjected to shear deformation. To achieve that, make a chip and a board! 2! It has been found that it is sufficient to fill the gap with a hard insulating material whose shear modulus is higher than that of the solder, and to create a state in which the material is bonded to the chip and the substrate. That is, the structure is shown in FIG. 1 (plan view) and FIG. 2 (longitudinal sectional view). In each figure, numerals 1 to 5 have the same meaning as in FIG. 5, and 7 means a resin material. The trap of creating this erratic structure is that after connecting the chips, there is a fluid synthetic mmt-mt! iK
A method is adopted in which the resin is introduced and cured at a predetermined temperature to form a hard resin layer. This structure is superior to conventional structures in that it prevents the mounting space from increasing due to the use of resin optical fibers. By stiffening, Seki 1! The amount of shear deformation of the entire i# will be controlled by the amount of deformation of the resin layer, and its value can be made significantly smaller than when it is not filled with resin. On the other hand, JP-A-58
It is easy to imagine that this effect cannot be expected with the rough and soft resin layer disclosed in Japanese Patent No. 10841. At least the shear modulus of solder (approximately 500
k&f/+a+'') is desirable.
更に、樹脂層としては、熱膨脹係数が、ハンダのそれに
等しいか、それシシ小さいことが、本発明の目的を高度
に達成するために望ましいことである。これは、基板あ
るいはチーラグ面圧対して法線方向の熱的膨張、収縮に
よるハンダ接続部の破断を防止するためである。樹脂層
の方が熱膨脹係数が小さければ、ハンダの膨張、収縮が
ある程度抑えられることが期待できる。Further, in order to achieve the object of the present invention to a high degree, it is desirable that the resin layer has a coefficient of thermal expansion equal to or much smaller than that of solder. This is to prevent the solder joints from breaking due to thermal expansion and contraction in the normal direction to the substrate or the cheek-lug surface pressure. If the resin layer has a smaller coefficient of thermal expansion, it can be expected that the expansion and contraction of the solder can be suppressed to some extent.
逆に膨腰係数の大きい樹脂層を作ると、ハンダに余分な
引張シ応力が加わり、樹脂層がない時は起り得ない引張
り疲労破断に至る可能性が高くなる。On the other hand, if a resin layer with a large expansion coefficient is created, extra tensile stress will be applied to the solder, increasing the possibility of tensile fatigue failure, which would not occur in the absence of the resin layer.
以上のような対策は、ＣＯＢ法によるハンダ接続部の冷
熱サイクルによる破断のメカニズム金初めて明らかにし
た結果生れたもので、従来は、この工うな方法での対策
は不可能と考えられていたものである。スペースファク
ターの点で多くの利点を有しながら、ＣＯＢ接続法が本
格的に実用化されなかったのも、実にこの問題のためで
おり、その点で本発明は画期的である。The above countermeasures were created as a result of the first clarification of the mechanism of fracture due to cooling and heating cycles of soldered joints using the COB method, and previously it was thought that countermeasures using this method were impossible. It is. Although it has many advantages in terms of space factor, it is precisely because of this problem that the COB connection method has not been put into practical use, and the present invention is groundbreaking in this respect.
本発明で用いられるチップは、シリコンウェハーから切
り出されたものが重要であるが、ＴＰＴが形成されたサ
ファイアなど絶縁基板を用いてもよい。更にはＧａＡａ
などの化合物結晶からなるチップを用いても↓い。It is important that the chip used in the present invention is cut out from a silicon wafer, but an insulating substrate such as sapphire on which TPT is formed may also be used. Furthermore, GaAa
You can also use a chip made of compound crystals such as .
電極が形成された基板としては、セラミックス、ガラス
、ガラス繊維強化プラスチックなど通常用いられている
配線基板材料が用いられる。As the substrate on which the electrodes are formed, commonly used wiring board materials such as ceramics, glass, and glass fiber reinforced plastics are used.
ガラスの場合には、特にシリコンチップとの膨張係数差
が大きいソーダガラスでも十分な接続信頼性が得られる
ので非常に安価な電子装置を作ることができる。In the case of glass, even soda glass, which has a large expansion coefficient difference from that of a silicon chip, can provide sufficient connection reliability, making it possible to manufacture very inexpensive electronic devices.
ハンダ材としては、汎用されている低融点金属の全ての
組成のものが用いられる。一般的には９５ Ｐｂ−５８
ｎ ハンダ、４０ ｐｂ −６０８ｎ ／％ンダがよく
用いられる。これらは、熱膨脹係数がほぼ２０Ｘ１０−
・〜２８ Ｘ １０−’ ａｎ／ ’Ｃである。As the solder material, all compositions of commonly used low melting point metals can be used. Generally 95Pb-58
n solder, 40 pb-608n/% solder is often used. These have a coefficient of thermal expansion of approximately 20X10-
・~28 X 10-'an/'C.
チップ及び配線基板の構成は、それぞれ当該分野で通常
行われるプロセスで作られる。ノ％ンダ接続部には、１
徨又はそれ以上の金属層からなるパッドが設けられ、表
面にはメッキなどで作られたハンダ層が設けられる。The structure of the chip and the wiring board are each made by a process commonly performed in the field. 1% for the connector connection.
A pad made of one or more metal layers is provided, and a solder layer made by plating or the like is provided on the surface.
チップと配線基板を、パッド部を対向させ、ハンダを加
熱溶融させることによってＯＯＢ接続が行われる。チッ
プと配線基板の間隙は５０〜１００μｍ８度である。OOB connection is performed by placing the chip and the wiring board so that their pads face each other and heating and melting the solder. The gap between the chip and the wiring board is 50 to 100 μm and 8 degrees.
そのあと、上記間隙部に流動性の樹脂ｔ−流し込み、硬
化させる。Thereafter, a fluid resin is poured into the gap and cured.
用いられる樹脂類としては、熱硬化性の多くの高分子材
料が対象となる。間隙を効率良く充てんし、しかもチッ
プ及び配線基板に対する接着性の高いものが望ましいた
め、一般には、無溶剤で流動性のめる樹脂類が好ましい
。その代表的な例がエポキシ樹脂を主成分とする一連の
材料である。The resins used include many thermosetting polymer materials. In general, resins that are solvent-free and fluid are preferred because they are desirable to fill gaps efficiently and have high adhesion to chips and wiring boards. A typical example is a series of materials whose main component is epoxy resin.
エポキシ樹脂と硬化剤を必須成分とし、更に可とう性付
与剤、硬化促進剤、充てん剤などが適宜用いられる。充
てん剤は硬化物の熱膨脹係数を調整するために不可欠で
あり、相当量配合される。可とう性付与剤は、樹脂層の
クラック発生防止に有効であり、ブタジェンゴム系材料
などが用いられる。この材料は、せん断弾性率を低くし
ない範囲で配合される。適正な配合量は重量でエポキシ
樹脂主剤１００部に対して最大２０部でめる。The epoxy resin and the curing agent are essential components, and further a flexibility imparting agent, a curing accelerator, a filler, etc. are used as appropriate. The filler is essential for adjusting the coefficient of thermal expansion of the cured product, and is added in a considerable amount. The flexibility imparting agent is effective in preventing the occurrence of cracks in the resin layer, and a butadiene rubber-based material or the like is used. This material is blended within a range that does not lower the shear modulus. The appropriate amount to be blended is a maximum of 20 parts by weight per 100 parts of the epoxy resin base resin.
以下、本発明の効果を具体的に説明するためいくつかの
実施例を挙げる。Hereinafter, some examples will be given to specifically explain the effects of the present invention.
（試料の作製方法）
１、材料
（１） シリコンチップ
板厚：α５■、寸法：５Ｘ５ｍ、周辺部罠１辺当シ１４
点、全部で５６点のハンダ接続部金膜け、隣り合った２
点間音導体で内部接続したモデルチップを作る。ハンダ
接続部にはマスク蒸着法により９５ Ｐｂ−５Ｓｎ／％
ンダ又は６０Ｐｂ−４０８ｎハンダが供給され高さ１２
０±１５μｍのバングが形成される。バング直径はほぼ
１５０μｍである。(Specimen preparation method) 1. Materials (1) Silicon chip plate thickness: α5■, dimensions: 5 x 5 m, peripheral trap 1 side contact size 14
56 points in total, gold film on solder connections, 2 adjacent points.
Create a model chip with internal connections using point-to-point sound conductors. 95Pb-5Sn/% is applied to the solder joints by mask evaporation method.
Supplied with solder or 60Pb-408n solder, height 12
A bang of 0±15 μm is formed. The bang diameter is approximately 150 μm.
（２） ソーダガラス（配線基板１）板厚２．０１１
１１ ％寸法２０■Ｘ ２０ ｍ１ｍ ｓ中央部にチッ
プを搭載するため、チップに設けられたバンプと対応す
る位置Ｋ ／％ンダ接続用ペデスタルを有する導体配線
が基板端部まで延在している基板である。導体はｃｒを
０１μｍ下地膜として形成しその上にＣｕ１２μｍ、い
ずれも蒸着に工って形成し、エツチングに工ってパター
ン形成したものである。(2) Soda glass (wiring board 1) board thickness 2.011
11% Dimensions: 20 x 20 m1m s In order to mount a chip in the center, a conductor wiring with a pedestal for connection to the bump provided on the chip and a pedestal for connecting the chip extends to the edge of the board. It is. The conductor was formed by forming a base film of Cr with a thickness of 01 .mu.m, on which a layer of Cu with a thickness of 12 .mu.m was formed by vapor deposition, and a pattern was formed by etching.
ペデスタル部以外は更にハンダレジストとしてＯｒをα
１μｍ蒸着しである。なお、ペデスタル上には、ハンダ
は供給されていない。Other than the pedestal part, add α as a solder resist.
It is evaporated to a thickness of 1 μm. Note that no solder is supplied on the pedestal.
（３） アルミナ（配線基板■］
板板厚１．０１１１１甘
上には配線基板Ｉと同様の配線パターンが形成されてい
る。導体は、Ｃｕのみで形成され、ハンダレジストとし
てｃｒ膜が形成される。(3) Alumina (wiring board ■) A wiring pattern similar to that of wiring board I is formed on the board with a thickness of 1.01111 mm.The conductor is made of Cu only, and a Cr film is formed as a solder resist. Ru.
（４） ガラス繊維強化エポキシ樹脂（配線基板板厚
：１．５ｍ，寸法２０箇×２０−１配線基板１と同様の
配線パターンがＯｕ箔全全エツチングて作られている。(4) Glass fiber-reinforced epoxy resin (wiring board board thickness: 1.5 m, dimensions 20 pieces x 20-1 A wiring pattern similar to that of wiring board 1 was made by etching the entire Ou foil.
更に導体上にＡｕ がメッキによって形成された上、有
機高分子系のハンダレジストがコーティングされている
。Further, Au is formed on the conductor by plating, and an organic polymer solder resist is coated on the conductor.
（５ン エポキシ樹脂組成物（ポツティング材目下記
組成の組成物。（重量部）
エピコート８２８
（シェル化学社製） １００部ＣＴＢ
ＮＩ ３００Ｘ１ ５
（Ｂ，Ｆ．グツドリッチ、ケミカル社製）
１５部ジシアンジアミド 工３部
シリカ粉末 ０〜２４２部カーボン粉
末 ［ｌＬ８部ボッティング材とし
て用いる場合の硬化条件は１５０℃で１時間でおる。(5 epoxy resin composition (potting material composition with the following composition. (parts by weight) Epicoat 828 (manufactured by Shell Chemical Co., Ltd.) 100 parts CTB
NI 300X1 5 (manufactured by B, F. Gutdrich, Chemical Company)
15 parts dicyandiamide 3 parts silica powder 0 to 242 parts carbon powder [lL 8 parts When used as a botting material, the curing conditions are 150° C. for 1 hour.
（６） シＩＪコーンゲル（ポツティング材■）トー
レシリコーン社製８１１８７１を用いた。硬化条件は１
５０℃で１時間。(6) SiIJ cone gel (potting material ■) 811871 manufactured by Toray Silicone Co., Ltd. was used. Curing conditions are 1
1 hour at 50℃.
以上の材料の記号と主な物性値は第１表に示したとおり
である。The symbols and main physical properties of the above materials are shown in Table 1.
２ チップの搭載
チップを配線基板に接続搭載するには、赤外線加熱法を
用いる６９５Ｐｂ−５８ｎハンダの場合は、最高到達温
度５５０℃、基板予熱温度１００℃である。また４ ０
Ｐｂ −６０８ｎハンダの場合は、最高到達源［２６
０℃である。いずれも適当なフラックスが用いられる。Mounting of 2 Chips In order to connect and mount a chip on a wiring board, in the case of 695Pb-58n solder using an infrared heating method, the maximum temperature reached is 550°C, and the board preheating temperature is 100°C. 40 again
For Pb-608n solder, the highest reaching source [26
It is 0°C. In either case, an appropriate flux is used.
接続後のバング高さは１５０〜１５０μｍの範囲である
。The bang height after connection is in the range of 150-150 μm.
五 ポツティング処理
前項で作成し、接続をチェックした後、ポツティング材
を用いて、ボッティング処理を行う。間隙を充てんする
場合は、間隙端部にボッティング材を所定量載置し、表
面張力の効果で間隙全光てんした上で、所定の条件で硬
化させる。5. Potting process After creating the material in the previous section and checking the connections, perform the potting process using the potting material. When filling a gap, a predetermined amount of botting material is placed at the end of the gap, the entire gap is filled with light due to the effect of surface tension, and the material is cured under predetermined conditions.
充てんをしない場合は、チヅプ上に所定量ボッティング
材を載置し、所定条件で硬化させる。When not filling, a predetermined amount of botting material is placed on the chip and cured under predetermined conditions.
４、 ？Ｉ？Ｉ熱サイクル試験
一り０℃／２時間←＋８５℃／２時間、４時間で１サイ
クルの冷熱サイクル試験をチップ搭載基板に対して実施
する。適宜、接続状態をチェックし、チップに断線個所
が発見されたサイクル数をサイクル寿命と判定する。4.? I? I Thermal Cycle Test One cycle of thermal cycle test is carried out on the chip-mounted board: 0°C/2 hours←+85°C/2 hours, 4 hours. The connection state is checked as appropriate, and the number of cycles in which a disconnection point is found on the chip is determined to be the cycle life.
同一条件で１０サンプル作り、サイクル試験を行う。Make 10 samples under the same conditions and perform a cycle test.
実施例１〜７及び比較例１〜６
Ｉ！２表に示す構成の電子装置を上述した処方に従って
１０個ずつ作製した。その後でポツティング処理を行い
、冷熱サイクル試験に供した。Examples 1 to 7 and Comparative Examples 1 to 6 I! Ten electronic devices each having the configuration shown in Table 2 were manufactured according to the above-mentioned recipe. Thereafter, a potting treatment was performed, and the sample was subjected to a thermal cycle test.
断線チェックを行い冷熱サイクル寿命全測定した。その
結果は第２１１！に示し九とおりである。We checked for disconnections and measured the entire cooling and heating cycle life. The result is number 211! The following is as shown in 9.
比較例１〜６との対比から、本発明になる電子装置が冷
熱サイクル寿命が著しく向上していることが明らかであ
る。From comparison with Comparative Examples 1 to 6, it is clear that the electronic device according to the present invention has significantly improved thermal cycle life.
ここに示した実施例は、数多くの電子装置構成のうち、
わずかの例にすぎないが、いずれも典型的な例であり、
本発明の効果を最も良く現わしている。The embodiments shown here are of a number of electronic device configurations.
These are just a few examples, but they are all typical examples.
This best demonstrates the effects of the present invention.
応用例１
集積回路の防湿を高度に達成することを目的として第１
崗及び第２図のような電子装置の外側に更に樹脂被覆を
行うことも本発明の効果を損わずに可能である。例えば
、第９図（平面図）及び第１０図（縦断面図ンのごとき
構造である。Application example 1 The first example is to achieve a high level of moisture resistance for integrated circuits.
It is also possible to further coat the outside of the electronic device as shown in FIG. 2 with a resin without impairing the effects of the present invention. For example, the structure is as shown in FIG. 9 (plan view) and FIG. 10 (longitudinal sectional view).
外側を被覆する樹脂も充てん層と同等のものが望ましい
ことはもちろんのことである。なお、スペースファクタ
ー、あるいは基板に対するストレスを考慮すると第９図
及び第１０図（示したような円筒状被覆が好ましい。It goes without saying that it is desirable that the resin covering the outside is the same as that of the filling layer. Note that in consideration of the space factor or the stress on the substrate, a cylindrical coating as shown in FIGS. 9 and 10 is preferable.
以上の説明は、配線基板とチップとを接続した電子装置
構成のみに限っているが、配線基板が液晶表示素子など
他の装置の一部となっている場合、めるいは、上述した
構成Ｗ！累が更に他の基板上に複数個配設されたモジュ
ール装置となる場合でも、本発明の効果は十分に発揮さ
れる。The above explanation is limited to the configuration of an electronic device in which a wiring board and a chip are connected, but if the wiring board is part of another device such as a liquid crystal display element, the above-mentioned configuration W ! Even in the case where a plurality of module devices are arranged on other substrates, the effects of the present invention can be fully exerted.
更に、Ｌ８Ｉの工うな集積度の高い部品だけですく、コ
ンデンサモジュール、抵抗モジュールのような部品にお
いても、実装密度を上げる九め、ＯＯＢ接合構造をとる
ことが考えられるが、その場合にも本発明に記載された
信頼性向上策は活かされる。Furthermore, it is possible to use only highly integrated components such as the L8I, and to increase the packaging density for components such as capacitor modules and resistor modules, it is possible to adopt an OOB bonding structure, but this also applies to this case. The reliability improvement measures described in the invention are utilized.
以上説明した１９に、本発明の電子装置に工れば、ＯＯ
Ｂ接合の実用化が可能となり、信頼性が格段に向上した
ことに伴い、実装密度の大幅な向上を実現することがで
きるという顕著な効果が奏せられる。If 19 explained above is applied to the electronic device of the present invention, OO
B-junction has become practical, and its reliability has been significantly improved, resulting in the remarkable effect that it is possible to realize a significant improvement in packaging density.
第１図及び第２図は本発明の構成例であって、第１図は
その平面図、第２図は相当する縦断面図、第３図〜第８
図は比較例あるいは従来例を示す構成例であって、＄Ｓ
図、第５図及び第７図はその平面図、第４図、第６図及
び第８図は相当する縦断面図、第９図及び第１０図は本
発明の応用例でおって、第９図はその平面図、第１０図
は相当する縦断面図でおる。
１：集積回路形成チップ、２：配線基板、３：ハンダ接
続部、４：１１極端子、５：導電線材、６：接合部材、
７：樹脂材料1 and 2 are configuration examples of the present invention, in which FIG. 1 is a plan view thereof, FIG. 2 is a corresponding vertical sectional view, and FIGS. 3 to 8.
The figure shows a configuration example showing a comparative example or a conventional example, and $S
5 and 7 are plan views thereof, FIGS. 4, 6 and 8 are corresponding longitudinal sectional views, and FIGS. 9 and 10 are examples of application of the present invention. 9 is a plan view thereof, and FIG. 10 is a corresponding longitudinal sectional view. 1: integrated circuit forming chip, 2: wiring board, 3: solder connection part, 4: 11-pole terminal, 5: conductive wire material, 6: bonding member,
7: Resin material
Claims (1)
なるＬＳＩチップと、配線を形成している基板とからな
り、該ＬＳＩチップと該基板とが該ハンダバンプを介し
てハンダ接合されてなる電子装置において、該ＬＳＩチ
ップと該基板とが作る間隙が、せん断弾性率が該ハング
のそれよりも大きい硬質の有機高分子材料により接着充
てんされていることを特徴とする電子装置。 ２、該有機高分子材料の熱膨脹係数が、接合に用いたハ
ンダの熱膨脹係数にほぼ等しいか、それよりも小さい特
許請求の範囲第１項記載の電子装置。 ３、該基板が、ソーダガラスである特許請求の範囲第１
項記載の電子装置。[Claims] 1. Consisting of an LSI chip having a plurality of solder bumps and on which an electronic circuit is formed, and a substrate on which wiring is formed, the LSI chip and the substrate are connected to each other by soldering via the solder bumps. An electronic device formed by joining the LSI chip and the substrate, wherein a gap formed between the LSI chip and the substrate is adhesively filled with a hard organic polymer material having a shear modulus greater than that of the hang. . 2. The electronic device according to claim 1, wherein the organic polymer material has a coefficient of thermal expansion that is approximately equal to or smaller than a coefficient of thermal expansion of the solder used for bonding. 3. Claim 1, wherein the substrate is soda glass.
Electronic devices as described in Section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60113166A JPS61271847A (en) | 1985-05-28 | 1985-05-28 | Electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60113166A JPS61271847A (en) | 1985-05-28 | 1985-05-28 | Electronic device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61271847A true JPS61271847A (en) | 1986-12-02 |
| JPH0451057B2 JPH0451057B2 (en) | 1992-08-18 |
Family
ID=14605222
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60113166A Granted JPS61271847A (en) | 1985-05-28 | 1985-05-28 | Electronic device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61271847A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6094354A (en) * | 1996-12-03 | 2000-07-25 | Nec Corporation | Chip component mounting board, chip component mounting structure, and method of manufacturing chip component mounting board |
-
1985
- 1985-05-28 JP JP60113166A patent/JPS61271847A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6094354A (en) * | 1996-12-03 | 2000-07-25 | Nec Corporation | Chip component mounting board, chip component mounting structure, and method of manufacturing chip component mounting board |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0451057B2 (en) | 1992-08-18 |
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