JPS61271834A - Formation of resist pattern - Google Patents

Formation of resist pattern

Info

Publication number
JPS61271834A
JPS61271834A JP11365685A JP11365685A JPS61271834A JP S61271834 A JPS61271834 A JP S61271834A JP 11365685 A JP11365685 A JP 11365685A JP 11365685 A JP11365685 A JP 11365685A JP S61271834 A JPS61271834 A JP S61271834A
Authority
JP
Japan
Prior art keywords
resist pattern
resist
post
temperature
baking
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11365685A
Other languages
Japanese (ja)
Inventor
Hidetsuna Hashimoto
橋本　英綱
Chiharu Kato
千晴 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP11365685A priority Critical patent/JPS61271834A/en
Publication of JPS61271834A publication Critical patent/JPS61271834A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Abstract

PURPOSE:To obtain a resist pattern having improved resistance to etching without causing deterioration in its dimensional accuracy, by performing the post-baking procedure in two seperate steps. CONSTITUTION:Resist is applied on a substrate to form a resist film and it is exposed and developed. When the resist film is post-baked to form a resist pattern, the post-baking is performed in two seperate steps: a low-temperature baking step and a high-temperature step. For example, the resist pattern is first baked at a low temperature of 110 deg.E for two minutes and then baked at a high temperature of 120-160 deg.C for four minutes. The resist pattern formed according to this method is allowed to have improved resistance to etching without causing the resist to sag and the dimensions thereof can be easily controlled. Consequently, a resist pattern usable as a mask for producing a fine semiconductor device with high precision can be obtained.

Description

【発明の詳細な説明】 （発明の技術分野） 本発明は、レジストパターンの形成方法に関し、特にポ
ストベーク工程を改良したレジストパターンの形成方法
に係わる。DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a method for forming a resist pattern, and particularly to a method for forming a resist pattern with an improved post-bake step.

（Ｆａ明の技術的背景〕 従来より、半導体基板等の基板上に所望形状のレジスト
パターンを形成するには、該基板上にレジスト膜を塗布
し、露光、現像処理を施した後、基板とレジストとの密
着性の向上及びエツチングに対するレジストの耐性を向
上する目的で熱板や対流型オーブンを用いて一定濃度、
一定時間ポストベークする方法が採用されている。(Technical background of Fa Ming) Conventionally, in order to form a resist pattern of a desired shape on a substrate such as a semiconductor substrate, a resist film is applied on the substrate, exposed and developed, and then the substrate and the like are coated. In order to improve the adhesion with the resist and the resistance of the resist to etching, a hot plate or convection oven is used to
A method of post-baking for a certain period of time is used.

〔背景技術の問題点〕[Problems with background technology]

前述したポストベークは、レジストと基板との密着性及
びエツチングに対する耐性を向上させる観点から、可能
な限り高温、長時間行なうことが望ましい。しかしなが
ら、あまり高温、長時間のポストベークを行なうと、レ
ジストが熱分解したり、ダレを生じたりして寸法精度の
高いレジストパターンの形成が困難となる。従って、通
常はレジストにダレの生じる温度より少し低い温度でポ
ストベークを行なっている。その結果、レジストパター
ンの耐エツチング性を充分に向上することができなかっ
た。The above-mentioned post-baking is desirably carried out at as high a temperature as possible for a long time from the viewpoint of improving the adhesion between the resist and the substrate and the resistance to etching. However, if post-baking is performed at too high a temperature and for a long time, the resist may thermally decompose or sag, making it difficult to form a resist pattern with high dimensional accuracy. Therefore, post-baking is usually performed at a temperature slightly lower than the temperature at which the resist sag. As a result, the etching resistance of the resist pattern could not be sufficiently improved.

〔発明の目的〕[Purpose of the invention]

本発明は、寸法精度の低下を招くことなく、耐エツチン
グ性の優れたレジストパターンを形成し得る方法を提供
しようとするものである。The present invention aims to provide a method for forming a resist pattern with excellent etching resistance without causing a decrease in dimensional accuracy.

〔発明の概要〕[Summary of the invention]

本発明は、基板上にレジスト膜を塗布し、露光、Ｉ！像
処理を施し、更にポストベークを行なってレジストパタ
ーンを形成するにあたり、前記ポストベークを低温と高
温の２段階に分けて行なうことを特徴とするものである
。かかる本発明によれば、既述の如く寸法精度の低下を
招くことなく、耐エツチング性の優れたレジストパター
ンを形成できる。In the present invention, a resist film is applied onto a substrate, exposed to light, and I! When performing image processing and further post-baking to form a resist pattern, the post-baking is performed in two stages: low temperature and high temperature. According to the present invention, a resist pattern with excellent etching resistance can be formed without causing a decrease in dimensional accuracy as described above.

（発明の実施例） 以下、本発明の実施例を詳細に説明する。(Example of the invention) Examples of the present invention will be described in detail below.

まず、基板上にポジ型レジスト（東京応化社性商品名；
０ＦＰＲ−５０００＞を塗布した後、プリベーク、露光
、現ｉＩＩ処理を施して３μｍの抜き部を有するレジス
トパターンを形成した。First, a positive resist (trade name manufactured by Tokyo Ohka Publishing Co., Ltd.) is applied on the substrate.
After applying 0FPR-5000>, prebaking, exposure, and current III processing were performed to form a resist pattern having a 3 μm punched portion.

次いで、前記レジストパターンを１１０℃で２分間の低
温ベークを施した後、１２０〜１６０℃の濃度範囲で４
分間の高温ベークを施した。Next, the resist pattern was subjected to low-temperature baking at 110°C for 2 minutes, and then baked at a concentration range of 120 to 160°C for 4 minutes.
A high temperature bake was performed for 1 minute.

しかして、前記２段ベーク後のレジストパターンについ
て、現像直後のレジストパターンの扱き部に対する寸法
変化量を調べたところ、図に示す特性図を得た。なお、
図中のＡは本実施例の特性線である。図中の８は、前記
レジストパターンを１２０〜１６０℃の温度範囲で４分
間ポストベークを行なった従来例における特性線である
。この図より明かなように１回のみのポストベークを行
なった従来例では、ベータ温度が高くなるに伴って急激
に寸法変化量が増大する。これに対し、本実施例では従
来例のような急激な寸法変化がなく、その変化量も少な
い。このため、ポストベーク温度を高温にすることが可
能となり、耐エツチング性の優れたレジストパターンを
形成できる。このように、２段目のベーク温度を高くで
きるのは、１段目の低温ベークによりレジストパターン
の表面に保護膜が形成されるため、レジストパターンの
寸法変化量が大きくなることなく２段目のべ−り温度を
高くできるものと考えられる。For the resist pattern after the two-stage baking, the amount of dimensional change in the treated portion of the resist pattern immediately after development was investigated, and the characteristic diagram shown in the figure was obtained. In addition,
A in the figure is a characteristic line of this example. 8 in the figure is a characteristic line in a conventional example in which the resist pattern was post-baked for 4 minutes in a temperature range of 120 to 160°C. As is clear from this figure, in the conventional example in which post-baking was performed only once, the amount of dimensional change increases rapidly as the beta temperature increases. On the other hand, in this example, there is no sudden dimensional change unlike in the conventional example, and the amount of change is small. Therefore, it is possible to increase the post-bake temperature to a high temperature, and a resist pattern with excellent etching resistance can be formed. In this way, the second-stage baking temperature can be increased because a protective film is formed on the surface of the resist pattern by the first-stage low-temperature baking. It is thought that the melting temperature can be increased.

〔発明の効果〕〔Effect of the invention〕

以上詳述した如く、本発明によればレジストのダレ等を
抑制した状態で耐エツチング性を向上でき、更に寸法１
１Ｊｔｌｌが容易となり、ひいては微細かつ高精度の半
導体装置の製造等に好適なマスクとして利用し得るレジ
ストバーンの形成方法を提供できる。As described in detail above, according to the present invention, it is possible to improve etching resistance while suppressing sagging of the resist, and further improve the etching resistance with a dimension of 1
It is possible to provide a method for forming a resist burn, which facilitates the formation of resist burns of 1 Jtll, and which can be used as a mask suitable for manufacturing fine and highly accurate semiconductor devices.

【図面の簡単な説明】[Brief explanation of drawings]

図面は、本実施例及び従来例のポストベーク時における
レジストパターンの寸法変化量を示す特性図である。The drawing is a characteristic diagram showing the amount of dimensional change of the resist pattern during post-baking in this embodiment and the conventional example.

Claims (1)

【特許請求の範囲】[Claims] 基板上にレジスト膜を塗布し、露光、現像処理を施し、
更にポストベークを行なつてレジストパターンを形成す
るにあたり、前記ポストベークを低温と高温の２段階に
分けて行なうことを特徴とするレジストパターンの形成
方法。A resist film is applied onto the substrate, exposed and developed,
A method for forming a resist pattern, characterized in that, in forming a resist pattern by further performing post-baking, the post-baking is performed in two stages: low temperature and high temperature.
JP11365685A 1985-05-27 1985-05-27 Formation of resist pattern Pending JPS61271834A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11365685A JPS61271834A (en) 1985-05-27 1985-05-27 Formation of resist pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11365685A JPS61271834A (en) 1985-05-27 1985-05-27 Formation of resist pattern

Publications (1)

Publication Number Publication Date
JPS61271834A true JPS61271834A (en) 1986-12-02

Family

ID=14617804

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11365685A Pending JPS61271834A (en) 1985-05-27 1985-05-27 Formation of resist pattern

Country Status (1)

Country Link
JP (1) JPS61271834A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5151871A (en) * 1989-06-16 1992-09-29 Tokyo Electron Limited Method for heat-processing semiconductor device and apparatus for the same
JPH05265223A (en) * 1992-03-17 1993-10-15 Sharp Corp Resist pattern forming method
JP2010225616A (en) * 2009-03-19 2010-10-07 Consortium For Advanced Semiconductor Materials & Related Technologies Pattern forming method
CN102978621A (en) * 2012-11-28 2013-03-20 北京中讯四方科技股份有限公司 Wet etching method for aluminum film in surface acoustic wave device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5448485A (en) * 1977-09-26 1979-04-17 Hitachi Ltd Photo etching method
JPS5742126A (en) * 1980-08-26 1982-03-09 Nec Kyushu Ltd Manufacture of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5448485A (en) * 1977-09-26 1979-04-17 Hitachi Ltd Photo etching method
JPS5742126A (en) * 1980-08-26 1982-03-09 Nec Kyushu Ltd Manufacture of semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5151871A (en) * 1989-06-16 1992-09-29 Tokyo Electron Limited Method for heat-processing semiconductor device and apparatus for the same
JPH05265223A (en) * 1992-03-17 1993-10-15 Sharp Corp Resist pattern forming method
JP2010225616A (en) * 2009-03-19 2010-10-07 Consortium For Advanced Semiconductor Materials & Related Technologies Pattern forming method
CN102978621A (en) * 2012-11-28 2013-03-20 北京中讯四方科技股份有限公司 Wet etching method for aluminum film in surface acoustic wave device

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