JP2010225616A - Pattern forming method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology for enabling accurate microfabrication by suppressing the LER of a resist without causing a significant increase in dielectric constant and drastic deterioration in insulation properties. <P>SOLUTION: A pattern forming method is configured to process a resist into a prescribed pattern by post-baking after exposure and development. The post-baking includes first post-baking and second post-baking executed after the first post-baking. The temperature of the second post-baking is higher than that of the first post-baking. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a pattern formation technique used for fine processing. For example, the present invention relates to an insulating film processing technique used for wiring formation in a semiconductor device.

  Large scale integrated circuits are becoming increasingly integrated. Then, semiconductor elements such as transistors constituting the integrated circuit are being reduced in size. This miniaturization improves the operating speed of the semiconductor element. However, the amount of wiring increases as the degree of integration increases. For this reason, the delay time due to the wiring has come to determine the operation speed of the large-scale integrated circuit. This delay time depends on the wiring resistance and the wiring capacitance. Therefore, reduction of wiring resistance and wiring capacity is required. Reduction of wiring resistance is realized by changing the wiring material from Al to Cu. A material having a resistance lower than that of Cu has not yet been proposed.

  By the way, when the degree of integration is increased and the number of semiconductor elements mounted on one semiconductor chip is increased, not only signal wiring for transmitting signals but also power is supplied to connect and operate these many semiconductor elements. The power supply wiring for this is also increased significantly. That is, the total number of wirings increases rapidly. That is, with the progress of miniaturization and higher density, the wiring capacity is increasing.

  Now, in order to shorten the delay time due to wiring and ensure desired performance, reduction of wiring capacity has been demanded. For this reason, it is necessary to use a material having a low relative dielectric constant for the insulating film. From this point of view, development of low dielectric constant insulating film materials (low-k film materials) is being promoted.

  By the way, the wiring formation process of a semiconductor device is generally as follows. First, a wiring groove is formed in the insulating film. Thereafter, the groove is filled with Cu. A plating method is used for filling the Cu. Since Cu is filled so as to exceed the groove, this excess Cu is removed. A CMP (Chemical Mechanical Polishing) method is employed for removal and planarization. That is, a so-called damascene method has been proposed. In particular, the dual damascene method, in which vias connecting upper and lower wirings and upper wiring grooves are simultaneously processed, is widespread from the viewpoint of simplifying the process and reducing the resistance of vias. In particular, since the influence of the overlay error of the lithography process on the via resistance fluctuation is small, even in the dual damascene method, the via first dual damascene wiring formation method (via connecting the upper wiring layer and the lower wiring layer on the lower wiring) The method of processing the upper layer wiring after processing) is widely used.

  Now, in wiring formation, the following has started to become a problem. That is, LER (Line Edge Roughness) of the resist has been pointed out as a problem. This LER means the roughness of the side wall surface of the resist pattern. Usually, when viewed from the top, the longitudinal direction is observed as a line, but the roughness in the depth direction is also important. This is because the LER of the resist pattern is finally transferred to the lower part to be processed. Therefore, various inconveniences occur in the next process. These inconveniences are manifested as variations in the electrical characteristics of the semiconductor device.

  After pattern formation by lithography, primary electrons are focused by an electromagnetic lens and irradiated onto the pattern. Secondary electrons and reflected electrons emitted from the irradiated surface are collected, a pattern edge is detected from the line profile, and a pattern dimension is measured. This pattern dimension value is defined as Critical Dimension (CD value). A small CD value variation is an important requirement. However, from the viewpoint of the electrical characteristics of the semiconductor device, it is important to reduce LER, which is a local variation in the dimension of the line pattern, in addition to controlling the CD value variation. For example, if the LER variation is 5% or more with respect to a limit dimension value in a specific L / S (Line / Space), the characteristics of the semiconductor device are surely changed. And a yield falls reliably. Therefore, it is important to reduce LER when forming a fine pattern.

  FIG. 1 is a general process diagram for forming a resist pattern. In FIG. 1, 1 is a resist, 2 is a BARC (Bottom Anti-Reflection Coating), 3 is a metal insulating film (low-k film), and 4 is a Si substrate. For pattern formation, first, a resist 1 is applied. After application, pre-baking (heating) is performed. After pre-baking, exposure is performed. After exposure, PEB (Post Exposure Bake: heating) is performed. Development is performed after PEB. After the development, post baking (heating) is performed. After the post-baking, the metal insulating film (Low-k film) 3 is etched.

  By the way, in order to suppress LER, post-processing such as DUV light irradiation and ion irradiation has been proposed after lithography. However, the conventionally proposed method causes deterioration of the resist pattern (tilt and excessive shrinkage). In addition, the dielectric constant of the fragile insulating film (Low-k film) is increased and the insulating property is deteriorated. For example, in order to obtain an effect by DUV light irradiation or ion irradiation, the resist pattern must be heated by irradiation for several minutes. However, if it does so, temperature will become high and a resist pattern will deform | transform (reflow). Irradiation that does not cause deformation of the resist pattern has a poor LER suppression effect. Furthermore, since the insulating film (Low-k film) 3 is exposed to ultraviolet rays and ions that have passed through the resist, the dielectric constant of the insulating film (Low-k film) 3 is increased and the insulation is deteriorated. And the characteristic of a device falls and manufacturing yield deteriorates.

  In particular, the adverse effect of LER has become prominent in consideration of adaptation to the ultrafine wiring forming process such as 65 nm, 45 nm, and 32 nm. And it has become difficult to cope with the conventional methods.

  In addition, development of resist materials for LER reduction has been underway. This is because the quality at the time of forming the resist pattern strongly depends on the material. FIG. 2 is for explaining the LER and the generation of the LER. The LER is the so-called material / process and is the fluctuation of the plane dimension of the line edge. This fluctuation includes not only the longitudinal direction of the edge but also the thickness direction. So-called so-called irregularities on the edge plane of the processed resist. This LER can be measured using a CD-SEM. First, the edge (x mark) of the line pattern is measured from the Cd-SEM image. Next, an average value of the edge positions is calculated. The deviation (variation) 3σ from the average value of each edge position is defined as LER.

JP 2001-332484 A JP 2005-535936 A JP 2001-358061 A JP-A-6-275510

  Japanese Patent Laid-Open No. 2001-332484 proposes a technique for curing a resist material by light irradiation as a LER suppression technique.

  Patent Document 2 (Japanese Patent Publication No. 2005-535936) proposes a technique for curing a photoresist material with plasma containing bromine as a LER suppression technique.

  Patent Document 3 (Japanese Patent Laid-Open No. 2001-358061) proposes a technique for curing a photoresist material by implanting Ar ions into a resist mask patterned by lithography as a LER suppression technique.

  Patent Document 4 (Japanese Patent Application Laid-Open No. 6-275510) proposes a technique for performing heat treatment after resist coating under reduced pressure (in a vacuum) as a LER suppression technique.

  By the way, according to the techniques of Patent Documents 1, 2, 3, and 4, the LER suppression effect is obtained.

  However, when these methods were implemented, the degree of deterioration of the fragile insulating film (Low-k film) was large. For example, when the technique of Patent Document 1 is adopted, characteristic deterioration of the insulating film (Low-k film) is unavoidable due to the irradiated ultraviolet light. When the technique of Patent Document 2 is adopted, the structure of the resist film changes due to the reducing action of the plasma, pattern deformation occurs, and the pattern size deviates from the design value. When the technique of Patent Document 3 is adopted, the pattern dimension (line width) is reduced by ion implantation, and if the line is finished thicker in anticipation of the pattern dimension becoming thinner, the exposure margin is reduced. When the technique of Patent Document 4 is adopted, the throughput is lowered because the heat treatment after the resist coating is performed in a vacuum apparatus.

  Therefore, the problem to be solved by the present invention is to solve the above problems. In particular, it is to provide a technique capable of suppressing the LER of a resist and enabling accurate fine processing without causing a significant increase in dielectric constant or a significant deterioration in insulation.

  Research to solve the above problems has been conducted with eagerness. As a result, it is imagined that the major cause of LER generation is that when the resist in the exposed area is dissolved in the developing solution in the developing process, the resist surface layer in the unexposed area is dissolved in the developing solution unevenly. It came. That is, it has been considered that the line end of the resist pattern is not finished in a straight line due to non-uniformity when dissolved in the developer, and swell (LER) is generated. Although this LER is as small as several nm, as the L / S becomes finer to 90 nm, 65 nm, and 45 nm, even LER on the order of several nm cannot be ignored. And with the progress of miniaturization, there is no limit to the reduction of LER just by improving the resist material.

  By the way, after the pattern formation, it is important that the resist material is hardened and the etching resistance is improved. Therefore, it was considered that the etching resistance would be improved by baking at a higher temperature than at the temperature recommended by the resist material manufacturer (about 100 to 130 ° C.). Therefore, the relationship between the post-baking temperature and CD, LER was examined. FIG. 3 is a graph in which the temperature during post-baking of the resist is plotted on the horizontal axis, and the CD value and LER value (CD value and LER value at 90 nm L / S) are plotted on the vertical axis. According to this, there is little dimensional variation until the post-bake temperature is about 150 ° C. The LER value is larger than 5 nm although it gradually decreases. When the post-bake temperature is about 160 ° C., the LER value is small (4.6 nm), but the dimensional variation is large as 5 nm or more. When the post bake temperature was 170 ° C., the entire pattern was reflowed. In other words, the pattern could not be formed (not resolved). Therefore, the upper limit of the post-baking temperature of this resist has been considered to be 150 ° C. Incidentally, when the post-bake temperature was 160 ° C., the dimensional variation ratio with respect to 90 nm L / S was 6%. And in this variation, the adverse effect of dimensional accuracy was too great. Therefore, although it was imagined that a higher post-baking temperature would be preferable from the etching resistance, it was found that post-baking at a high temperature is not preferable. Even when post-baking was performed at 110 ° C. (low temperature recommended by the resist material manufacturer), the LER value was not small.

  Further research has been carried out by the inventor in earnest. In other words, investigations have been made on what causes the fluidity of the resist in which pattern deformation has occurred. As a result, it has been imagined that the solvent contained (residual) in the resist film may be a major factor. Then, after the solvent was sufficiently removed, it was thought that reflow or the like would not occur even if post-baking was performed at a high temperature. Therefore, after the post-baking at a low temperature, that is, after the solvent remaining in the resist film is sufficiently removed, the problem is solved if the post-baking at a high temperature is performed. Then it came to be considered.

  Therefore, first, post-baking at 110 ° C. was performed for 45 seconds. Since this temperature is low-temperature baking, problems such as reflow of the resist film did not occur. And the solvent was removed sufficiently. This was followed by a post-bake at a higher temperature. The result is shown in FIG. The graph of FIG. 4 is plotted with the temperature at the post-baking stage (high temperature post-baking) in the subsequent stage on the horizontal axis and the CD value and the LER value (CD value and LER value at 90 nm L / S) on the vertical axis. It is a graph. 4A and 4B, the leftmost (1) is the high temperature post-baking temperature of 120 ° C, the middle (2) is the high-temperature post-baking temperature of 160 ° C, and the rightmost (3) is the high-temperature post-baking. This is for a baking temperature of 170 ° C. According to FIG. 4, it can be seen that there is little dimensional variation and LER is small even when post-baking at a high temperature of 160 ° C.

  From such knowledge, if the post-baking is initially performed at a low temperature and then at a high temperature, the LER of the resist is not caused without causing a significant increase in dielectric constant or a significant deterioration in insulation. As a result, a revelation was made that accurate microfabrication would be possible.

  Further experiments were continued based on the above findings. As a result, an initial post-bake was performed at a temperature range where the solvent remaining in the resist film was removed, and then a subsequent post-bake was performed at a high temperature range to improve etching resistance. It was. For example, the initial post-baking is performed at a temperature 10-20 ° C. lower than the boiling point of the solvent remaining in the resist film, and the late post-baking is performed at a temperature 10-20 ° C. higher than the boiling point of the solvent, Favorable results have been obtained. That is, no significant increase in dielectric constant or significant deterioration in insulation was caused. And LER was suppressed significantly. And accurate microfabrication became possible. For example, when the electrical characteristics of the manufactured semiconductor device were examined, no great variation in pattern dimensions was observed. In addition, LER (an index of variation in local line pattern dimensions) was greatly reduced. Furthermore, it was confirmed that there was no significant characteristic deterioration of the insulating film (Low-k film).

  The present invention has been achieved based on the above findings.

The above-mentioned problem is a pattern forming method in which a resist is processed into a predetermined pattern by post-baking after exposure and development.
The post-bake comprises a first post-bake and a second post-bake performed after the first post-bake,
The temperature of the second post-bake is higher than the temperature of the first post-bake, which is solved by the pattern forming method.

In particular, in a pattern forming method for processing a resist into a predetermined pattern by post-baking after exposure and development,
The post-bake comprises a first post-bake and a second post-bake performed after the first post-bake,
The temperature of the first post-bake is 5 to 50 ° C. lower than the boiling point of the solvent contained in the resist,
The temperature of the second post-baking is solved by the pattern forming method, which is 5 to 50 ° C. higher than the boiling point of the solvent contained in the resist.

Further, in the above pattern forming method,
The temperature of the first post-bake is 100 to 150 ° C.
The temperature of the second post-bake is 150 to 200 ° C., which is solved by the pattern forming method.

Further, in the above pattern forming method,
The first post-bake time at low temperature is 15-90 seconds,
The second post-bake time at a high temperature is 15 to 90 seconds, which is solved by the pattern forming method.

  The LER of the resist is suppressed and accurate fine processing is performed. In addition, the dielectric film under the resist does not cause a significant increase in dielectric constant or a significant deterioration in insulation. Furthermore, the insulating film can be processed with high accuracy.

Resist pattern formation process explanatory drawing Diagram explaining LER and LER occurrence Graph showing the relationship between post bake temperature and CD, LER Graph showing the relationship between post bake temperature and CD, LER Example of post-baking temperature profile Cross-sectional photograph of a pattern according to the practice of the present invention

  The present invention is a pattern forming method. In particular, it is a pattern forming method in which a resist is processed into a predetermined pattern by post-baking after exposure and development. For example, it is a pattern formation method used when forming a pattern with L / S of 100 nm or less. The post bake includes a first post bake and a second post bake performed after the first post bake. The second post-bake temperature is higher than the first post-bake temperature.

  In particular, the temperature of the first post-bake is 5 to 50 ° C. (more preferably 10 to 30 ° C.) lower than the boiling point of the solvent contained in the resist. More specifically, a general solvent for resist has a boiling point of about 140 to 180 ° C. For example, the resist includes a resin (support), an acid generator, a solvent, and other additives as necessary. In resists for exposure using ArF as a light source, PGMA (propylene glycol monomethyl ether acetate), EL (ethyl lactate), Diglyme (diethylene glycol dimethyl ether) and the like are used as solvents (boiling point is about 140 to 180 ° C.). Yes. Accordingly, the temperature of the first post-bake is preferably about 100 to 150 ° C. Of course, the temperature is lower than the boiling point of the solvent. More preferably, it is 100 ° C. or higher. And it is 130 degrees C or less. When post-baking is performed at a temperature higher than the boiling point of the solvent, the entire resist pattern is deformed (reflowed), and it is difficult to obtain an appropriate resist profile. Then, by first performing the low-temperature post-bake (first post-bake) as described above, the solvent is removed (scattered) at a temperature lower than the boiling point of the solvent, and the fluidity of the resist is sealed. That is, the low-temperature post-bake as described above is a heating that does not cause deformation of the resist pattern, the flowability of the resist is low, and the unexposed resist surface layer portion generated in the development process is non-uniformly dissolved in the developer ( It is difficult to cause undulation. The time for this first post-bake (low temperature post-bake) is 15 to 90 seconds. More preferably 30 seconds or more. And 60 seconds or less are more preferable.

  Following the first post-baking (low-temperature post-baking), a second post-baking (high-temperature post-baking) is performed. The temperature of the second post-bake is 5 to 50 ° C. (more preferably 10 to 30 ° C.) higher than the boiling point of the solvent contained in the resist. Specifically, since the boiling point of a general resist solvent is about 140 to 180 ° C., the temperature of the second post-bake is about 150 to 200 ° C. Of course, the temperature is equal to or higher than the boiling point of the solvent. More preferably, it is 160 ° C. or higher. And it is 180 degrees C or less. This high temperature post-bake time is 15 to 90 seconds. More preferably 30 seconds or more. And 60 seconds or less are more preferable. As a result, the resist film can be baked and the etching resistance is high. Then, the lower insulating film (Low-k film) can be patterned accurately.

  Hereinafter, specific examples will be described.

[Example 1]
In this embodiment, the present invention is applied to the formation of a via first dual damascene wiring in a fine pattern region (for example, L / S is 100 nm or less) in which LER greatly affects pattern accuracy. In this size region, the influence of LER variation is very large.

  A commercially available resist material was used for exposure of ArF rays. The solvent of this commercially available resist material had a boiling point of 140 ° C. This commercially available resist material manufacturer recommends post-baking conditions in which the temperature is 100 to 130 ° C. and the time is 60 seconds or less.

  The resist pattern formation flow in the lithography process is resist coating → pre-baking → exposure → PEB → development → post-baking. The normal flow was adopted. That is, first, the resist material was applied to a thickness of 150 nm. Thereafter, prebaking was performed at 120 ° C. for 60 seconds. Then, exposure and development were performed with an ArF scanner.

  After development, post-baking was performed. A coater / developer apparatus (ACT-12 manufactured by Tokyo Electron Limited) was used for the post-baking. That is, first, low-temperature post-baking (130 ° C., 45 seconds) was performed. This low temperature post-bake was followed by a high temperature post-bake (160 ° C., 45 seconds).

  For comparison, post-baking was performed at 130 ° C. for 60 seconds.

As a result, in this example, there was no dimensional variation at 75 nm L / S. The LER was 3.1 nm. In the comparative example, the LER was 4.3 nm. Therefore, it can be seen that the implementation of the present invention such as low temperature post-bake → high temperature post-bake can reduce the LER. That is, a fine pattern is formed with high accuracy. Moreover, an extra device as described in Patent Documents 1, 2, 3, and 4 is not necessary and can be easily implemented.
In addition, the cross-sectional photograph of the pattern obtained in the said Example is shown in FIG.

[Example 2]
It carried out similarly to the said Example. However, the resist coating thickness is 220 nm. The resist material was different, and the boiling point of the solvent was 160 ° C. For this reason, the first low-temperature post-bake condition was 120 ° C. for 50 seconds, and the second high-temperature post-bake condition was 200 ° C. for 40 seconds.

  For comparison, post-baking was performed at 120 ° C. for 60 seconds.

  As a result, in this example, there was no dimensional variation at 90 nm L / S. The LER was 4.4 nm. In the comparative example, the LER was 6.3 nm. Therefore, it can be seen that the implementation of the present invention such as low temperature post-bake → high temperature post-bake can reduce the LER. That is, a fine pattern is formed with high accuracy. Moreover, an extra device as described in Patent Documents 1, 2, 3, and 4 is not necessary and can be easily implemented.

1 resist 2 BARC (Bottom
Anti-Reflection Coating)
3 Metal insulation film (Low-k film)
4 Si substrate

Claims (5)

In the pattern forming method of processing the resist into a predetermined pattern by post-baking after exposure and development,
The post-bake comprises a first post-bake and a second post-bake performed after the first post-bake,
The pattern forming method, wherein the temperature of the second post-bake is higher than the temperature of the first post-bake. The temperature of the first post-bake is 5 to 50 ° C. lower than the boiling point of the solvent contained in the resist,
2. The pattern forming method according to claim 1, wherein the temperature of the second post-bake is 5 to 50 [deg.] C. higher than the boiling point of the solvent contained in the resist. The temperature of the first post-bake is 100 to 150 ° C.
The pattern forming method according to claim 1 or 2, wherein the temperature of the second post-bake is 150 to 200 ° C. The first post-bake time at low temperature is 15-90 seconds,
4. The pattern forming method according to claim 1, wherein the second post-bake time at a high temperature is 15 to 90 seconds. The pattern forming method according to claim 1, wherein L / S is a pattern forming method of 100 nm or less.

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