JPS61270909A - Voltage controlled oscillator - Google Patents

Voltage controlled oscillator

Info

Publication number
JPS61270909A
JPS61270909A JP11335185A JP11335185A JPS61270909A JP S61270909 A JPS61270909 A JP S61270909A JP 11335185 A JP11335185 A JP 11335185A JP 11335185 A JP11335185 A JP 11335185A JP S61270909 A JPS61270909 A JP S61270909A
Authority
JP
Japan
Prior art keywords
voltage
terminal
differential amplifier
oscillation
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11335185A
Other languages
Japanese (ja)
Other versions
JPH0666652B2 (en
Inventor
Tomoaki Hirai
智明 平井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP60113351A priority Critical patent/JPH0666652B2/en
Publication of JPS61270909A publication Critical patent/JPS61270909A/en
Publication of JPH0666652B2 publication Critical patent/JPH0666652B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/26Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
    • H03K3/28Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
    • H03K3/281Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
    • H03K3/282Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator astable

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)

Abstract

PURPOSE:To obtain excellent voltage versus oscillating frequency characteristic even at a high frequency region by forming a variable capacitor on the same semiconductor chip so as to reduce a parasitic inductance thereby eliminating a characteristic distortion at the high frequency. CONSTITUTION:A capacitor 3 on an emitter coupling multivibrator 1 is the result of optional number of selection and combination of plural variable capacitors CO-Cn formed on the semiconductor chip by switches S1-Sn. Further, an adjusting terminal 4 is provided to a differential amplifier 2 to adjust an output voltage amplitude Vx by a value of an adjusting resistor RxX5. Thus, the input voltage versus oscillating frequency characteristic is compensated. An optional capacitance is obtained by operating the switches S1-Sn and it is prevented that the reduction in the degree of freedom of the user's application is fixed by providing an adjusting terminal.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は電圧制御発振器(vC○)に関し、特に入力電
圧−発振周波数特性の高周波領域における歪を改善する
のに好適な電圧制御発振器に関するものである。
[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a voltage controlled oscillator (vC○), and particularly to a voltage controlled oscillator suitable for improving distortion in the high frequency region of input voltage-oscillation frequency characteristics. be.

〔発明の背景〕[Background of the invention]

従来、電圧制御発振器(VC○)の基本回路としては、
中沢修冶、他2名訳「アナログ集積回路」近代科学社、
昭和50年9月15日発行、P333〜334に記載さ
れている第6図のエミッタ結合マルチバイブレータ形の
ものがある。その基本回路に基づく応用回路としては、
一般に第7図に示すような回路ブロックとなる。ただし
、応用回路では5第6図において容量Cに印加する発振
電圧がVBE(V)固定であるのに対し、任意に設定で
きるようにしている。
Conventionally, the basic circuit of a voltage controlled oscillator (VC○) is as follows:
“Analog Integrated Circuits” translated by Shuji Nakazawa and two others, Kindai Kagakusha,
There is an emitter-coupled multivibrator type shown in FIG. 6, which is published on September 15, 1975, pages 333-334. As an applied circuit based on the basic circuit,
Generally, the circuit block is as shown in FIG. However, in the applied circuit, the oscillation voltage applied to the capacitor C in FIG. 5 is fixed at VBE (V), but can be set arbitrarily.

VCO64は発振部、差動増幅部、出力バッファ部によ
り構成し1発振部内の特性が等しくかつ同一の入力端子
を有している電圧制御電流源61゜62に入力した電圧
Vin(V)を発振電流I (A)に変換させ、 I  o: Vin          ・・・・・・
・・(1)その変換した電流Iをトランジスタ57およ
び58の0N10FF状態に基づいて外付はタイミング
容量63に充放電することにより発振状態となる。なお
、発振動作中は、第8図に示すように。
The VCO 64 is composed of an oscillation section, a differential amplification section, and an output buffer section, and oscillates the voltage Vin (V) input to the voltage controlled current sources 61 and 62, which have the same characteristics within one oscillation section and the same input terminal. Convert to current I (A), I o: Vin ・・・・・・
(1) The external timing capacitor 63 is charged and discharged with the converted current I based on the 0N10FF state of the transistors 57 and 58, thereby entering an oscillation state. Note that during the oscillation operation, as shown in FIG.

VSTA端子50が゛’Loν″″状態、差動増幅器5
9の入力端51.52の電圧がI O〜II  VF”
(V)、差動増幅器59の出力端53.54の電圧振幅
がΔV(V)、差動増幅器60の入力端53.54の電
圧差が±ΔV(V)である。
VSTA terminal 50 is in "Loν" state, differential amplifier 5
The voltage at the input terminals 51 and 52 of 9 is IO~II VF"
(V), the voltage amplitude at the output terminal 53.54 of the differential amplifier 59 is ΔV (V), and the voltage difference at the input terminal 53.54 of the differential amplifier 60 is ±ΔV (V).

この時、外付はタイミング容量63の両端55゜56に
発生する電圧は第8図に示す波形となるので、VCO6
4による発振周波数f(Hz)は、となる。ただし、C
は外付はタイミング容量63の値CF)、ΔVは差動増
幅器59のシングルエンド出力電圧振幅(V)、Iは入
力電圧Vin(V)に比例する発振電流(A)、tpd
は発振部と差動増幅部との帰還ループにおいて素子特性
に起因する信号伝搬遅延時間(see)であり、一般に
外付はタイミング容量63を短絡状態にし差動増幅器5
9の出力極性を逆接続にしてVCO64をトグル発振さ
せた場合の1周期(see)に等しい。
At this time, the voltage generated at both ends 55°56 of the external timing capacitor 63 has the waveform shown in FIG.
The oscillation frequency f (Hz) according to 4 is as follows. However, C
is the value CF of the external timing capacitor 63), ΔV is the single-end output voltage amplitude (V) of the differential amplifier 59, I is the oscillation current (A) proportional to the input voltage Vin (V), tpd
is the signal propagation delay time (see) caused by element characteristics in the feedback loop between the oscillation section and the differential amplifier section, and generally the external timing capacitor 63 is shorted and the differential amplifier 5
It is equal to one cycle (see) when the VCO 64 is caused to toggle oscillation by reversely connecting the output polarity of 9.

このことから、例えば差動増幅器59の出力電圧振幅Δ
Vが0.8(V)、外付はタイミング容量63の値Cが
50(pF)、信号伝搬遅延時間tpdが8(ns)、
発振電流Iが5 (m A’)の状態においては、VC
O64から出力する発振周波数fが25 (M Hz 
)となる。
From this, for example, the output voltage amplitude Δ of the differential amplifier 59
V is 0.8 (V), the value C of the external timing capacitor 63 is 50 (pF), the signal propagation delay time tpd is 8 (ns),
When the oscillation current I is 5 (mA'), VC
The oscillation frequency f output from O64 is 25 (MHz
).

このようにVin(V)の値に応じてf(MI4z)を
変化するVCO64は1例えば、磁気ディスク記憶装置
のデータ弁別窓発生回路において、PLL(P has
e L ocked L oop)回路の発振器として
使用されるが、最近のデータ転送の高速化に伴って、更
に高い周波数域の発振が要求されている。また。
In this way, the VCO 64 that changes f (MI4z) according to the value of Vin (V) is 1. For example, in a data discrimination window generation circuit of a magnetic disk storage device, the PLL (P has
The oscillator is used as an oscillator in a locked loop) circuit, but as data transfer speeds have increased recently, oscillation in a higher frequency range is required. Also.

PLL回路の発振器としては、入力電圧Vin(V)を
ある基準バイアス電圧Vo(V)と等しくした場合に、
その時の発振周波数fo(Hz)を精度良く(例えば±
0.1%程度)調整する必要もある。なお、foを特に
″自走発振周波数″と呼び、この時の発振電流Ioを特
に゛′中心発振電流″と呼ぶ。
As an oscillator of a PLL circuit, when the input voltage Vin (V) is made equal to a certain reference bias voltage Vo (V),
The oscillation frequency fo (Hz) at that time is determined accurately (for example, ±
(approximately 0.1%) may also need to be adjusted. Note that fo is particularly called a "free-running oscillation frequency", and the oscillation current Io at this time is especially called a "center oscillation current".

上記の要求を満するためVCO64においては、製造上
からバラツキが生ずる差動増幅器59の出力電圧振幅Δ
V(V)や、信号伝搬遅延時間 tpd(see)、ま
た1%程度の公差を有している外付はタイミング容量6
3に対し、外付けの可変抵抗などを使用して、電圧制御
電流源61.62の変換特性を調整し、中心発振電流I
o(A)の値を変えて所定の自走発振周波数fo(Hz
)の範囲内に合せている。
In order to meet the above requirements, the VCO 64 has an output voltage amplitude Δ of the differential amplifier 59, which has variations due to manufacturing.
V (V), signal propagation delay time tpd (see), and timing capacitance 6 for external components that have a tolerance of about 1%.
3, the conversion characteristics of the voltage-controlled current sources 61 and 62 are adjusted using external variable resistors, etc., and the center oscillation current I
By changing the value of o(A), a predetermined free-running oscillation frequency fo(Hz
) within the range.

しかし、上記の対策ではVCO64の入力電圧−発振周
波数特性が第9図に示した理想的な曲線70に対し、高
周波域でズレが生じてしまう曲線71となる。これは高
周波域になると(2)式の発振電流I (A)に依存し
ない定数項tpdが無視できなくなり、すなわち[4C
ΔV/ I )>> t pdの条件が成立しなくなっ
て、入力電圧−発振周波数の特性が非線形となるためで
ある。
However, with the above measures, the input voltage-oscillation frequency characteristic of the VCO 64 becomes a curve 71 that deviates from the ideal curve 70 shown in FIG. 9 in the high frequency range. This is because in the high frequency range, the constant term tpd that does not depend on the oscillation current I (A) in equation (2) cannot be ignored, that is, [4C
This is because the condition of ΔV/I) >> t pd no longer holds, and the input voltage-oscillation frequency characteristic becomes nonlinear.

そこでVCO64を更に高い周波数域にて動作させるた
めには、外付はタイミング容量63の値C(F)および
差動増幅器59のシングルエンド出力電圧振幅ΔV(V
)を小さくシ2発振電流I (A)を大きくするという
回路的な工夫だけでなく、信号伝搬遅延時間t pd(
see)を小さくするための素子特性の向上が必要不可
欠である。
Therefore, in order to operate the VCO 64 in a higher frequency range, external components are required such as the value C (F) of the timing capacitor 63 and the single-end output voltage amplitude ΔV (V
) and increase the oscillation current I (A), as well as the signal propagation delay time t pd (
It is essential to improve device characteristics in order to reduce .see).

以上より上記と同様、例えば差動増幅器59の出力電圧
振幅ΔVを0.4(V)、外付はタイミング容量63の
値Cを20(p F)、発振電流Iを5(m A ) 
、信号伝搬遅延時間tpclを2(nS)に低減した状
態においては、VCO64から出力する発振周波数fを
120(MH)することが可能となるが、実際には、外
付はタイミング容量器63のリード線やICパッケージ
のリード線などに寄生するインダクタンスの影響を受け
るために、ある周波域で特性歪が生じてしまう曲線72
のような入力電圧−発振周波数の特性であった。
From the above, similar to the above, for example, the output voltage amplitude ΔV of the differential amplifier 59 is 0.4 (V), the value C of the external timing capacitor 63 is 20 (p F), and the oscillation current I is 5 (m A ).
, in a state where the signal propagation delay time tpcl is reduced to 2 (ns), it is possible to increase the oscillation frequency f output from the VCO 64 to 120 (MH), but in reality, the external connection is Curve 72 where characteristic distortion occurs in a certain frequency range due to the influence of parasitic inductance in lead wires and IC package lead wires.
The input voltage-oscillation frequency characteristic was as follows.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、このような従来の問題を解決し、エミ
ッタ結合マルチバイブレータ形電圧制御発振器(VCO
)において、ユーザの用途範囲を制限することなく、高
周波域での特性歪をなくした入力電圧−発振周波数の特
性を得ると共に、信号伝搬遅延時間tpdを小さくする
ことのできる電圧制御発振器を提供することにある。
The purpose of the present invention is to solve such conventional problems and to develop an emitter-coupled multivibrator voltage controlled oscillator (VCO).
), to provide a voltage controlled oscillator which can obtain input voltage-oscillation frequency characteristics without characteristic distortion in a high frequency range and reduce signal propagation delay time tpd without limiting the range of applications of users. There is a particular thing.

〔発明の概要〕[Summary of the invention]

上記目的を達成するため1本発明の電圧制御発振器(v
co)iは、入力電圧を電流に変換する電圧制御電流源
18.19と、該N流を基に発振するエミッタ結合マル
チバイブレータと、該発振の出力を増幅して上記エミッ
タ結合マルチバイブレータに負帰還する差動増幅器2と
を半導体チップ上に形成する電圧制御発振器において、
上記半導体チップ上に形成された複数個の容量器CO”
 Cnからなり、上記電流の充放電により上記発振を行
う可変容量器3と、上記負帰還の電圧を調整するための
端子4とを備えることに特徴がある。
In order to achieve the above object, a voltage controlled oscillator (v
co)i is a voltage-controlled current source 18.19 that converts an input voltage into a current, an emitter-coupled multivibrator that oscillates based on the N current, and an emitter-coupled multivibrator that amplifies the output of the oscillation and supplies a negative signal to the emitter-coupled multivibrator. In a voltage controlled oscillator in which a feedback differential amplifier 2 is formed on a semiconductor chip,
A plurality of capacitors CO” formed on the semiconductor chip
It is characterized by comprising a variable capacitor 3 made of Cn, which performs the oscillation by charging and discharging the current, and a terminal 4 for adjusting the voltage of the negative feedback.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の実施例を図面により説明する。 Embodiments of the present invention will be described below with reference to the drawings.

第1図は本発明の一実施例を示す電圧制御発振器(VC
O)のブロック図である。同図において。
FIG. 1 shows a voltage controlled oscillator (VC) showing an embodiment of the present invention.
It is a block diagram of O). In the same figure.

11.12は等しい特性を持つダイオード、13゜14
は特性および低抗値の等しい抵抗器、15゜16は等し
い特性を持つNPN)−ランジスタ、17は正および負
の入/出力端を具備する差動増幅器、18.19は共通
の入力端子9を持つ電流引込み形の電圧制御電流源、2
は正および負の入/出力端と、前述のVSTA端子50
と同様に発振動作のスタート/ストップが指示できる切
替入力端子VsTA6と、入力電圧−発振周波数の特性
をaWiする抵抗器5を接続する調整端子4とを具備す
る差動増幅器、3は可変容量器であり、容量値を変える
ことができるような構成で同一半導体チップ上に形成す
る、10.26はそれぞれ直流バイアス電源VccyV
EEを供給する電源端子。
11.12 are diodes with equal characteristics, 13°14
are resistors with equal characteristics and low resistance, 15° and 16 are NPN transistors with equal characteristics, 17 is a differential amplifier with positive and negative input/output terminals, 18.19 is a common input terminal 9 a current-drawing voltage-controlled current source with
are the positive and negative input/output terminals and the aforementioned VSTA terminal 50.
A differential amplifier is equipped with a switching input terminal VsTA6 which can similarly instruct start/stop of oscillation operation, and an adjustment terminal 4 to which a resistor 5 is connected to adjust the input voltage-oscillation frequency characteristic aWi, and 3 is a variable capacitor. 10.26 is a DC bias power supply VccyV, which is formed on the same semiconductor chip with a configuration that allows the capacitance value to be changed.
Power supply terminal that supplies EE.

7.8は差動増幅器17からの互に逆極性の差動信号を
外部に送出する出力端子、20〜25は接続端である。
7.8 is an output terminal for sending out differential signals of opposite polarity from the differential amplifier 17 to the outside, and 20 to 25 are connection terminals.

VCOLの回路構成は、第111に示すようにダイオー
ド11.12のアノードと抵抗器13,14の一方端を
mg端子vcctoに接続し、その反対側すなわちダイ
オード11のカソードと低抗奉13の他方端を接続端2
0を介してNPNトランジスタ15のコレクタおよび差
動増幅器2の正の入力端に接続し、ダイオードI2のカ
ソードと抵抗器14の他方端を接続端21を介してNP
Nトランジスタ16のコレクタおよび差動増幅器2の負
の入力端に接続する。
The circuit configuration of the VCOL is as shown in No. 111, in which the anodes of diodes 11 and 12 and one end of resistors 13 and 14 are connected to the mg terminal vccto, and the opposite side, that is, the cathode of diode 11 and the other end of low resistance resistor 13, are connected to the mg terminal vccto. Connect end to end 2
0 to the collector of the NPN transistor 15 and the positive input terminal of the differential amplifier 2, and connect the cathode of the diode I2 and the other end of the resistor 14 to the NPN
Connected to the collector of the N transistor 16 and the negative input terminal of the differential amplifier 2.

同様に、差動増幅器2の正の出力端を接続端22を介し
て差動増幅器17の正の入力端およびNPNトランジス
タ16のベースに接続し、一方、負の出力端を接続端2
3を介して差動増幅器17の負の入力端およびNPNト
ランジスタ15のベースに接続する。NPN)−ランジ
スタ15のエミッタを接続端24を介して電圧制御電流
源18の出力端および可変容量器3の一方端に接続し、
一方、NPNトランジスタ16のエミッタを接続端25
を介して電圧制御電流源19の出力端および可変容量器
3の他方端に接続する。差動増幅器17の正、負の出力
端をそれぞれ出力端子7,8に、電圧制御、電流源L8
.L9の出力もう一端を直流バイアス電源VEEに、電
圧制御電流源18.19の共通制御入力端を入力端子9
に、差動増幅器2の振幅調整端、切換入力端をそれぞれ
調整端子4゜切替入力端子6に各々接続する。調整端子
4には後述する電圧調整用の抵抗器5を接続する。なお
、抵抗器5を除く上記各素子は同一半導体チップ上に形
成する。
Similarly, the positive output end of the differential amplifier 2 is connected to the positive input end of the differential amplifier 17 and the base of the NPN transistor 16 via the connecting end 22, while the negative output end is connected to the connecting end 22.
3 to the negative input terminal of the differential amplifier 17 and the base of the NPN transistor 15. NPN) - the emitter of the transistor 15 is connected to the output end of the voltage controlled current source 18 and one end of the variable capacitor 3 via the connection end 24;
On the other hand, the emitter of the NPN transistor 16 is connected to the connection terminal 25.
It is connected to the output end of the voltage controlled current source 19 and the other end of the variable capacitor 3 via. The positive and negative output terminals of the differential amplifier 17 are connected to output terminals 7 and 8, respectively, and voltage control and current source L8 are connected.
.. The other end of the output of L9 is connected to the DC bias power supply VEE, and the common control input end of the voltage controlled current source 18 and 19 is connected to the input terminal 9.
Then, the amplitude adjustment terminal and the switching input terminal of the differential amplifier 2 are connected to the adjustment terminal 4 and the switching input terminal 6, respectively. A resistor 5 for voltage adjustment, which will be described later, is connected to the adjustment terminal 4. Note that each of the above elements except the resistor 5 is formed on the same semiconductor chip.

VCOlは、前述した第7図(7)VCO64ト同様の
発振メカニズムで発振動作を行い、入力端子9からの入
力電圧Vin(V)の値に対応する発振周波数f(Hz
)を出力端子7,8に送出する。その発振周波数f(H
z)は、前記(2)式と同様、となる。ただし、CXは
可変容量!a3の値CF)、vXは差動増幅器2のシン
グルエンド出力電圧振*(V)、tpdは信号伝搬遅延
時間(sec)、工は入力電圧Vin(V)に比例する
発振電流(A)である。
The VCOl performs an oscillation operation using the same oscillation mechanism as the VCO64 shown in FIG.
) is sent to output terminals 7 and 8. Its oscillation frequency f(H
z) is the same as in equation (2) above. However, CX has variable capacity! a3 value CF), vX is the single-end output voltage swing * (V) of differential amplifier 2, tpd is the signal propagation delay time (sec), and Δ is the oscillation current (A) proportional to the input voltage Vin (V). be.

なお、前述したVCO64と異なる点は、■差動増幅器
2にvxを調整するための抵抗器5を接続し、■可変容
量器3を同一半導体チップ上に形成したことである。
The difference from the VCO 64 described above is that (1) a resistor 5 for adjusting vx is connected to the differential amplifier 2, and (2) a variable capacitor 3 is formed on the same semiconductor chip.

第2図は2本発明の一実施例を示す可変容量器3の構成
図である。同図において、co l CL *C2r 
C3・・・・Cnはそれぞれ後述する値で同一半導体チ
ップ上に形成する容量器であり、Sl。
FIG. 2 is a configuration diagram of a variable capacitor 3 showing an embodiment of the present invention. In the same figure, col CL *C2r
C3...Cn are capacitors formed on the same semiconductor chip with values to be described later, and Sl is a capacitor formed on the same semiconductor chip.

S2+S3・・・・Snはそれぞれ開放または短絡状態
に設定できる切替器である。
S2+S3...Sn are switching devices that can be set to an open or short-circuit state, respectively.

容量器C□”Cnは、切替wI81〜Snを全て開放状
態にしたときに、可変容量器3としての値Cx(F)を
最小C)(win(F)にし、反対に全てを短絡状態に
したときに最大CXmax (P )の値にする。それ
を式で表わすと。
The capacitor C□''Cn sets the value Cx(F) as the variable capacitor 3 to the minimum C)(win(F) when all switches wI81 to Sn are in the open state, and conversely, all are in the short-circuited state. When this happens, the maximum value is CXmax (P).This can be expressed as a formula.

Cx+*1n=C(I X(1+a)      ””
(4)C)<max=(C□ +C1+C2+”・+C
n)X(1+α)・・・(5) となる、ただし、αは製造的なバラツキによる容量値の
誤差で一般に±20%程1度である。
Cx+*1n=C(I X(1+a) ””
(4)C)<max=(C□ +C1+C2+”・+C
n)

また、容量器Co” Cnは、可変容量器3としての値
Cx(F)を目標値CTc(F)に設定するために、そ
の値を。
In addition, the capacitor Co''Cn is set to the value Cx(F) of the variable capacitor 3 to the target value CTc(F).

Co =CT c/ 2 (F)       ”(6
3C1=CTc/2CF)       ・・・・(7
)C2=CT C/ 22CF)        ””
(8)Cs =CT c/ 23(F)       
”(9)Cn=+CTc/2’(F)        
−・・・cto)のように構成する。
Co = CT c/ 2 (F) ”(6
3C1=CTc/2CF) ...(7
)C2=CT C/22CF) ""
(8) Cs = CT c/23(F)
”(9)Cn=+CTc/2'(F)
-...cto).

上記の各位に構成したときのC)(min(F)および
C)(may(F)は、上記(4)、(5)式から、C
)<+ain=CT CX(1+ a)/ 2 (F)
 ・・・・(11)=CTcX[(3/2)  (1/
2”))×(1+α)(F〕 5 ・・・・(12) となる、すなわち、可変容量器3の値Cx(F)を(1
1)式による値C)(+m1n(F)から(12)式に
よる値C)(max(F)までの中から、各切替器81
〜S nを開放または短絡状態にすることで、 CTC
(1+α)/2nCF)の単位により任意な容量値に設
定することが可能となる。つまり、第4図に示すように
、製造バラツキα=0の場合における調整範囲が0.5
(、rc〜[1,5(1/2’)ICT(:(F’)、
設定ピッチがCT(:/2’CF)となり、製造バラツ
キα;+20%の場合における調整範囲が0.6C7c
〜(1,8−(1,2/2’)JCrc(F)−設定ヒ
ラf カ1 、2 CT (:/ 2 ” (F)トナ
リ、製造バラツキα=−20%の場合における調整範囲
が0.4CTに〜(1,2(0,8/2”)]CTC(
F)、設定ピッチが0.8(、rc/2”(F)となる
。したがって1本構成とすることで、製造バラツキ±2
0%における可変容量器3の値CX(F)を最小値0.
6Crc(F)から最大値〔1,2(0,8/2”l〕
CTc(F)まで(7)中から、最大Wf4M (1,
2/2 n”” )CTa(F)(7)11位で任意に
設定することができる。
C) (min (F) and C) (may (F) when configured in each of the above parts are calculated from the above formulas (4) and (5),
)<+ain=CT CX(1+ a)/2 (F)
...(11)=CTcX[(3/2) (1/
2”)×(1+α)(F) 5 (12) In other words, the value Cx(F) of the variable capacitor 3 is set to (1
1) Value C according to formula (+m1n(F) to value C according to formula (12)) (max(F)), each switch 81
By opening or shorting ~Sn, CTC
(1+α)/2nCF) allows setting an arbitrary capacitance value. In other words, as shown in Figure 4, the adjustment range when manufacturing variation α = 0 is 0.5.
(,rc~[1,5(1/2')ICT(:(F'),
The adjustment range is 0.6C7c when the setting pitch is CT (:/2'CF) and manufacturing variation α; +20%.
~(1,8-(1,2/2')JCrc(F)-Setting angle f FC1,2 CT (:/2" (F) Adjustment range when manufacturing variation α=-20% 0.4CT~(1,2(0,8/2”)]CTC(
F), the setting pitch is 0.8 (, rc/2" (F). Therefore, by using one piece, the manufacturing variation can be reduced by ±2.
The value CX(F) of the variable capacitor 3 at 0% is set to the minimum value 0.
Maximum value from 6Crc(F) [1, 2 (0, 8/2”l)]
Up to CTc (F) (7) from medium to maximum Wf4M (1,
2/2 n””) CTa(F) (7) Can be set arbitrarily at 11th place.

以上より1例えば設ける段数nを6″にした場合には、
Cx(F)を0.6CTc 〜1.19CTc(F)の
範囲から、最大誤差0.0094CTC(F)(=0.
94%)の値で任意に設定できる。また。
From the above, for example, when the number of stages n is set to 6'',
Cx(F) from the range of 0.6CTc to 1.19CTc(F), the maximum error is 0.0094CTC(F) (=0.
94%) can be set arbitrarily. Also.

仮に製造バラツキが±30%、設ける段数nを上記と同
*”6’J: L7’=場合LC4:l:、 Cx(F
)ヲ0 、65CTC〜1.039CTc(F)の範囲
から最大誤差0.OL 02CTG(F)の値で任意に
選択できる。
If the manufacturing variation is ±30% and the number of stages n is the same as above *"6'J: L7'= then LC4:l:, Cx(F
) wo 0, the maximum error is 0.0 from the range of 65CTC to 1.039CTc(F). Can be arbitrarily selected using the value of OL 02CTG (F).

第3図(a)〜(c)は、切替器S 1〜S nの開放
または短絡状態の実現例を示すものである。
FIGS. 3(a) to 3(c) show examples of realizing open or shorted states of the switches S1 to Sn.

同図(a)においては、端子TI−’r3間、端子’r
2−T3間に大電流を流すことによって、それぞれダイ
オードDSl y DS2のジャンクションを破壊し、
端子’r、−’r2間を開放から短絡状態にする方法で
ある。同図(b)においては、端子’r、−’r、間に
大電流を流すことによって、ヒユーズ)1stを溶断し
、端子’r、−T2間を上記とは反対に短絡から開放状
態にする方法である。同図(e)においては、端子T1
−T2間を接続する金属線にレーザ光を照射して溶断し
、上1a(b)と同様に端子’r、−T2間を短絡から
開放状態に変える方法である。
In the same figure (a), between terminal TI and 'r3, terminal 'r
By passing a large current between 2 and T3, the junctions of diodes DSly and DS2 are destroyed,
This is a method of changing the state between the terminals 'r and -'r2 from open to short-circuited. In the same figure (b), by flowing a large current between terminals 'r and -'r, fuse (1st) is blown, and terminals 'r and -T2 are changed from a short circuit to an open state, contrary to the above. This is the way to do it. In the same figure (e), the terminal T1
This is a method in which the metal wire connecting between -T2 is irradiated with a laser beam to fuse it, and the terminal 'r and -T2 are changed from a short circuit to an open state as in the above 1a (b).

第5図は、差動増幅器2の一実施例を示す回路図である
。なお、同図において接続端20〜23゜抵抗器RX5
.調整端子4.切替入力端子6.ill流バイアス電源
VEEはそれぞれ上記第1図と同一のものである。
FIG. 5 is a circuit diagram showing one embodiment of the differential amplifier 2. In FIG. In addition, in the same figure, the connection end 20~23° resistor RX5
.. Adjustment terminal 4. Switching input terminal 6. The illumination bias power supplies VEE are the same as those shown in FIG. 1 above.

差動増幅器2は、切替入力端子6からの信号VSTAが
1“High”レベルのときにはトランジスタTr5を
ON状態にして増幅機能を停止し1反対にII L o
 v37レベルのときにはT r 5をOFF状態にし
て増幅動作を実行する。また、調整用抵抗器RX5の値
に応じてトランジスタT r 5のエミッタ電圧を変え
ることができるので、接続端22および接続端23の出
力電圧振幅Vx(V)をIll!することが可能である
When the signal VSTA from the switching input terminal 6 is at 1 "High" level, the differential amplifier 2 turns on the transistor Tr5 to stop the amplification function, and vice versa.
When the voltage is at the v37 level, T r 5 is turned off to perform the amplification operation. Moreover, since the emitter voltage of the transistor T r 5 can be changed according to the value of the adjustment resistor RX5, the output voltage amplitude Vx (V) of the connection terminal 22 and the connection terminal 23 can be changed to Ill! It is possible to do so.

その調整による差動増幅器2のシングルエンド出力電圧
振幅Vx(V月よ、 V x ” (Rs / (Rt + Rx ) 3X
(VER−VBE)(V)  ”(13)で表わすこと
ができる。なお1本実施例においては調整端子4に可変
抵抗器5を外付けにしたが。
The single-ended output voltage amplitude of the differential amplifier 2 due to its adjustment Vx (V month, V x ” (Rs / (Rt + Rx) 3X
(VER-VBE)(V)'' (13) Note that in this embodiment, the variable resistor 5 is externally connected to the adjustment terminal 4.

温度補償機能などを有する回路網を接続することも可能
である。
It is also possible to connect a circuit network having a temperature compensation function or the like.

このように、可変容量器3を同一半導体チップ上に個別
部品と同等以上のW1度で形成することにより、配線な
どに伴う寄生インダクタンスを極めて小さくすることが
でき、入力電圧−発振周波数特性の高周波域での特性歪
を除去することが可能となる。また、可変容量器3を(
6)〜(10)式に示す値の容量器Co” Cnで構成
し、それ等を接続するための切替器81〜Snを設けた
ことで、可変容量器3としての値Cx(F)を容易かつ
精度良く目襟値Crc(F)に設定することができると
共に、従来はタイミング容量63で実施していたのを、
差動増幅器2に接続したm′M用の抵抗器5で入力電圧
−発振周波数特性を補償するので、タイミング容量を固
定化した場合に低下してしまうユーザによる応用の自由
度を防止することができる。
In this way, by forming the variable capacitor 3 on the same semiconductor chip with a W1 degree equal to or higher than that of individual components, the parasitic inductance associated with wiring etc. can be made extremely small, and the high frequency of the input voltage-oscillation frequency characteristic can be minimized. It becomes possible to remove characteristic distortion in the area. In addition, the variable capacitor 3 (
6) to (10), and by providing switchers 81 to Sn for connecting them, the value Cx(F) of the variable capacitor 3 can be changed. It is possible to easily and accurately set the target value Crc (F), and the timing capacity was previously set to 63.
Since the m'M resistor 5 connected to the differential amplifier 2 compensates for the input voltage-oscillation frequency characteristics, it is possible to prevent the user's flexibility in application, which would be reduced if the timing capacitance was fixed. can.

〔発明の効果〕〔Effect of the invention〕

以上説明したように1本発明によれば、可変容量器を同
一半導体チップ上に形成したことにより寄生インダクタ
ンスを顕著に低減し、高周波域での特性歪を除去すると
ともに、信号伝搬遅延時間tpdも小さくなるので数十
Mz以上の高周波領域においても良好な入力電圧−発振
周波数特性が得られる。また、可変容量器を値が異なる
複数の容量器で構成したことでユーザの用途範囲が制限
されるのを防止している。
As explained above, according to the present invention, parasitic inductance is significantly reduced by forming variable capacitors on the same semiconductor chip, characteristic distortion in the high frequency range is eliminated, and signal propagation delay time tpd is also reduced. Since it is small, good input voltage-oscillation frequency characteristics can be obtained even in a high frequency region of several tens of Mz or more. Further, by configuring the variable capacitor with a plurality of capacitors having different values, the user's range of application is prevented from being limited.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す電圧制御発振器(V 
CO)のブロック図、第2図は可変容量r)3の構成図
、第3図(a)〜(c)は切替器81〜Snの実現方法
を説明するための図、第4図は可変容量器3の値Cx(
F)の設定方法を説明するための図、第5図は差動増幅
器2の回路図、第6図は従来の電圧制御発振@(V C
○)の基本回路を示す回路図、第7図は従来の電圧側m
発振器(VCO)の応用回路の等価ブロック図、第8図
は第7図の動作タイミングチャート、第9図は第7図の
入力電圧−発振周波数の特性図である。 1.64:電圧制御発振器(VCO)、2,17゜59
.60:差動増幅器、3:可変容量器、4:’111M
端子、5 *  131 14 r RL〜R4:抵抗
器、6:切瞥入力端子、7,8:出力端子、9:入力端
子、10.26:電源端子、11,12.Dsl *D
s2:ダイオード、15,16,57,58゜Trl〜
Tr5 : N P N トランジスタ、18.19゜
61.62:電圧制御電流源、20〜25.51〜54
:接続端、50:VSTA端子、55,56;外部端子
、63:外付はタイミング容量、70:理想特性曲線、
71,72:特性曲線、T1〜T3:端子、 C(1”
Cn :容量器、Hsl:ヒユーズ、81〜Sn:切替
器。 第   1   図 第   2   図 第4図 第5図
FIG. 1 shows a voltage controlled oscillator (V
CO), FIG. 2 is a block diagram of the variable capacitor r) 3, FIGS. 3(a) to (c) are diagrams for explaining how to realize the switching devices 81 to Sn, and FIG. Value of capacitor 3 Cx(
Fig. 5 is a circuit diagram of the differential amplifier 2, and Fig. 6 is a diagram for explaining the setting method of the differential amplifier 2.
○) Circuit diagram showing the basic circuit, Figure 7 is the conventional voltage side m
FIG. 8 is an equivalent block diagram of an application circuit of an oscillator (VCO), FIG. 8 is an operation timing chart of FIG. 7, and FIG. 9 is a characteristic diagram of input voltage versus oscillation frequency of FIG. 7. 1.64: Voltage controlled oscillator (VCO), 2,17°59
.. 60: Differential amplifier, 3: Variable capacitor, 4: '111M
Terminal, 5*131 14 r RL~R4: Resistor, 6: Cut-off input terminal, 7, 8: Output terminal, 9: Input terminal, 10.26: Power supply terminal, 11, 12. Dsl *D
s2: Diode, 15, 16, 57, 58°Trl~
Tr5: NPN transistor, 18.19°61.62: Voltage controlled current source, 20~25.51~54
: connection end, 50: VSTA terminal, 55, 56; external terminal, 63: external timing capacitor, 70: ideal characteristic curve,
71, 72: Characteristic curve, T1 to T3: Terminal, C (1”
Cn: Capacitor, Hsl: Fuse, 81-Sn: Switch. Figure 1 Figure 2 Figure 4 Figure 5

Claims (1)

【特許請求の範囲】[Claims] (1)入力電圧を電流に変換する電圧制御電流源と、該
電流を基に発振するエミッタ結合マルチバイブレータと
、該発振の出力を増幅して上記エミッタ結合マルチバイ
ブレータに負帰還する差動増幅器とを半導体チップ上に
形成する電圧制御発振器において、上記半導体チップ上
に形成された複数個の容量器からなり、上記電流の充放
電により上記発振を行う可変容量器と、上記負帰還の電
圧を調整するための端子とを備えることを特徴とする電
圧制御発振器。
(1) A voltage-controlled current source that converts an input voltage into a current, an emitter-coupled multivibrator that oscillates based on the current, and a differential amplifier that amplifies the output of the oscillation and provides negative feedback to the emitter-coupled multivibrator. in a voltage controlled oscillator formed on a semiconductor chip, the voltage controlled oscillator is composed of a plurality of capacitors formed on the semiconductor chip, and includes a variable capacitor that performs the oscillation by charging and discharging the current, and a voltage of the negative feedback that is adjusted. A voltage controlled oscillator characterized by comprising a terminal for.
JP60113351A 1985-05-27 1985-05-27 Voltage controlled oscillator Expired - Lifetime JPH0666652B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60113351A JPH0666652B2 (en) 1985-05-27 1985-05-27 Voltage controlled oscillator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60113351A JPH0666652B2 (en) 1985-05-27 1985-05-27 Voltage controlled oscillator

Publications (2)

Publication Number Publication Date
JPS61270909A true JPS61270909A (en) 1986-12-01
JPH0666652B2 JPH0666652B2 (en) 1994-08-24

Family

ID=14610059

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60113351A Expired - Lifetime JPH0666652B2 (en) 1985-05-27 1985-05-27 Voltage controlled oscillator

Country Status (1)

Country Link
JP (1) JPH0666652B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0785616A1 (en) * 1996-01-22 1997-07-23 Telefonaktiebolaget Lm Ericsson A balanced integrated semiconductor device operating with a parallel resonator circuit
JP2008011132A (en) * 2006-06-29 2008-01-17 Nec Electronics Corp 90-degree phase shifter

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56115019A (en) * 1980-02-15 1981-09-10 Fujitsu Ltd Switched capacitor filter
JPS5744319A (en) * 1980-08-29 1982-03-12 Fujitsu Ltd Variable attenuator
JPS60113A (en) * 1983-06-16 1985-01-05 Sony Corp Voltage control oscillator

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56115019A (en) * 1980-02-15 1981-09-10 Fujitsu Ltd Switched capacitor filter
JPS5744319A (en) * 1980-08-29 1982-03-12 Fujitsu Ltd Variable attenuator
JPS60113A (en) * 1983-06-16 1985-01-05 Sony Corp Voltage control oscillator

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0785616A1 (en) * 1996-01-22 1997-07-23 Telefonaktiebolaget Lm Ericsson A balanced integrated semiconductor device operating with a parallel resonator circuit
US5844301A (en) * 1996-01-22 1998-12-01 Telefonaktiebolaget Lm Ericsson Balanced integrated semiconductor device operating with a parallel resonator circuit
JP2008011132A (en) * 2006-06-29 2008-01-17 Nec Electronics Corp 90-degree phase shifter

Also Published As

Publication number Publication date
JPH0666652B2 (en) 1994-08-24

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