JPS61270866A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61270866A JPS61270866A JP60112722A JP11272285A JPS61270866A JP S61270866 A JPS61270866 A JP S61270866A JP 60112722 A JP60112722 A JP 60112722A JP 11272285 A JP11272285 A JP 11272285A JP S61270866 A JPS61270866 A JP S61270866A
- Authority
- JP
- Japan
- Prior art keywords
- region
- transistor
- collector
- layer
- emitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 230000002159 abnormal effect Effects 0.000 abstract description 6
- 238000009792 diffusion process Methods 0.000 abstract description 5
- 230000015556 catabolic process Effects 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 3
- 230000000694 effects Effects 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000004090 dissolution Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、基板上に形成したＮＰＮ トランジスタと
該ＮＰＮトランジスタと同一島内に形成した上記ＮＰＮ
トランジスタのコレクタ領域ヲヘース領域とするＰＮＰ
トランジスタとからなる半導体装置に関する。ものであ
る。[Detailed Description of the Invention] [Industrial Application Field] This invention relates to an NPN transistor formed on a substrate and an NPN transistor formed on the same island as the NPN transistor.
PNP where the collector region of the transistor is used as the base region
The present invention relates to a semiconductor device including a transistor. It is something.
相補トランジスタは、集積度を上げるためにＮＰＮトラ
ンジスタと四−島内にＰＮＰ）ランシスタを形成し、Ｎ
ＰＮトランジスタのコレクタ領域がＰＮＰトランジスタ
のベース領域を兼ねる構造とすることがある。Complementary transistors form NPN transistors and NPN transistors in a four-island structure to increase the integration density.
In some cases, the collector region of the PN transistor also serves as the base region of the PNP transistor.
第２図は従来のこの種の半導体装置の一例の各領域の配
置を示す平面図、第３図は第２図に示す半導体装置のＡ
Ｂ面の断面における内部構造を示す断面図である。FIG. 2 is a plan view showing the arrangement of each region of an example of a conventional semiconductor device of this type, and FIG. 3 is an A of the semiconductor device shown in FIG.
FIG. 3 is a cross-sectional view showing the internal structure in a cross section of plane B. FIG.
図においてｌはＰ″″半導体基板、２はＮ−エピタキシ
ャル成長層、３はＮ＋埋込層、４はＰ十分離溝。In the figure, l is a P'' semiconductor substrate, 2 is an N- epitaxial growth layer, 3 is an N+ buried layer, and 4 is a P-sufficient trench.
５はＮＰＮ トランジスタのエミッタ電極、６はＮＰＮ
トランジスタのベース領域、７はＮＰＮトランジスタの
コレクタ領域でＰＮＰトランジスタのベース領域を兼ね
る。８はＰＮＰトランジスタのエミッタ領域、９はＰＮ
Ｐ トランジスタのコレクタ領域、１０はＮＰＮ トラ
ンジスタのエミッタ電極、 １１はＮＰＮ トランジス
タのベースミ極、１２はＮＰＮ トランジスタのコレク
タ電極兼ＰＮＰトランジスタのベース電極、１３ハＰＮ
Ｐトランジスタのエミッタ電極、 １４はＰＮＰトラン
ジスタのコレクタ電極、１５は絶縁保護膜である。5 is the emitter electrode of the NPN transistor, 6 is the NPN
The base region of the transistor, 7, is the collector region of the NPN transistor, which also serves as the base region of the PNP transistor. 8 is the emitter region of the PNP transistor, 9 is the PN
10 is the emitter electrode of the NPN transistor, 11 is the base electrode of the NPN transistor, 12 is the collector electrode of the NPN transistor and the base electrode of the PNP transistor, 13 is the PN transistor collector region.
The emitter electrode of the P transistor, 14 the collector electrode of the PNP transistor, and 15 an insulating protective film.
半導体基板１上に接合分離されたＮＰＮ トランジスタ
を形成する場合、エピタキシャル成長工程前に、まず、
Ｐ−基板１のある領域にＮ十拡散を行う。このＮ−エピ
タキシャル成長層の下に形成したＮ十拡散層は通常Ｎ十
埋込層３と呼ばれ、ウェーハ表面のコレクタ・コンタク
トからベース領域６直下のコレクタ活性領域までのコレ
クタ直列抵抗を下げるための層である。When forming a junction-isolated NPN transistor on the semiconductor substrate 1, first, before the epitaxial growth process,
N10 diffusion is performed in a certain region of the P-substrate 1. The N0 diffusion layer formed under this N-epitaxial growth layer is usually called the N0 buried layer 3, and is used to reduce the collector series resistance from the collector contact on the wafer surface to the collector active region directly below the base region 6. It is a layer.
次に、エピタキシャル成長層２０表面に酸化膜を形成し
、この酸化膜に分離溝４を形成するための拡散窓をあげ
、ウエーノ・表面からＮ十エピタキシャル成長層２を貫
いてＰ−基板の中まで達するＰ十分離溝４を形成する。Next, an oxide film is formed on the surface of the epitaxial growth layer 20, and a diffusion window for forming the isolation groove 4 is formed in this oxide film, penetrating the N+ epitaxial growth layer 2 from the wafer surface and reaching the inside of the P-substrate. Form a groove 4 that is sufficiently separated from P.
Ｐ十分離溝４で形成した島内にＮＰＮトランジスタと同
時にＰＮＰ トランジスタを形成する。A PNP transistor is formed at the same time as an NPN transistor in the island formed by the P-sufficiently separated trench 4.
ＰＮＰトランジスタは、同−Ｐ−基板上にＮＰＮトラン
ジスタと同時につ（るために横方向構造とし、ベース領
域をＮＰＮトランジスタのコレクタ領域７と同一の領域
とし、コレクタ領域９をＰ十分離溝４に連ねて形成する
。The PNP transistor has a lateral structure in order to be mounted on the same P-substrate at the same time as the NPN transistor, the base region is the same as the collector region 7 of the NPN transistor, and the collector region 9 is placed in a groove 4 sufficiently separated from the PNP transistor. form a series.
従来のこの種の半導体装置は以上のように。 The conventional semiconductor device of this type is as described above.
Ｎ十埋込層３はコレクタ・コンタクトの直下までしか伸
びておらず、ＰＮＰトランジスタのコレクタ・エミッタ
間電圧を増していくと、Ｎ−エピタキシアル成長層２内
に第３図に点線で示すように空乏層１６が広がってゆき
ｅ ＶＯＥ （コレクタ・エミッタ間電圧）がＢ ＶＯ
ＥＯ（コレクタ・エミッタ間降伏電圧）に達する前に上
下の空乏層１６かつらなり、ペース電極１２にベース電
流が供給されな（なり、ＰＮＰトランジスタのｖｏｇ−
ＩＣ特性は第４図に示すような異常なものとなるという
問題があった。The N-buried layer 3 extends only to just below the collector contact, and as the collector-emitter voltage of the PNP transistor is increased, the N-epitaxial growth layer 2 has a layer as shown by the dotted line in FIG. As the depletion layer 16 expands, e VOE (collector-emitter voltage) becomes B VO
Before reaching EO (collector-emitter breakdown voltage), the upper and lower depletion layers 16 are formed, and the base current is not supplied to the pace electrode 12.
There was a problem in that the IC characteristics became abnormal as shown in FIG.
この発明は上記の問題を解消するためになさＩ゛
れたもので、 ＶＯ，−葦（、特性に異常現象の起らな
いこの種半導体装置を提供することを目的としている。The present invention was devised to solve the above-mentioned problems, and its object is to provide a semiconductor device of this type in which no abnormal phenomenon occurs in the characteristics.
Ｖｏｇ−Ｉ□特性における以上のような異常現象の発生
を防止するために、ＮＰＮトランジスタに対するＮ＋埋
込層の領域をＰＮＰ トランジスタのコレクタ領域の一
部の直下若しくはエミッタ領域の直下まで拡張した。In order to prevent the above abnormal phenomenon in the Vog-I□ characteristic from occurring, the region of the N+ buried layer for the NPN transistor is extended to directly below a part of the collector region or directly below the emitter region of the PNP transistor.
第１図はこの発明の一実施例を示す断面図であり９図に
おいて第３図と同一符号は同一または相当する部分を示
し、３ａ＆！領域をＰＮＰトランジスタのコレクタ領域
の一部９の直下若しくはエミッタ領域８の直下まで拡張
したＮ＋埋込 ・層である。FIG. 1 is a sectional view showing an embodiment of the present invention, and in FIG. 9, the same reference numerals as in FIG. 3 indicate the same or corresponding parts, and 3a&! This is an N+ buried layer whose region extends to directly below part 9 of the collector region 9 or directly below the emitter region 8 of the PNP transistor.
エピタキシャル成長工程前に行５Ｎ＋拡散の領域を拡張
することによって、Ｎ十埋込層３ａの領域を任意のとこ
ろまで拡張することができる。By expanding the region of the row 5N+ diffusion before the epitaxial growth step, the region of the N0 buried layer 3a can be extended to any desired location.
Ｎ十埋込層３ａがＰＮＰトランジスタのコレクタ領域の
一部９の直下若しくはエミッタ領域８の直下まで伸びて
いるの、で、ＰＮＰトランジスタのコレクタ・エミッタ
間電圧ＶＯＥを増していく場合、Ｎ−エピタキシャル成
長層２内に広がる上下の空乏層がつらなる前に、降伏電
圧ＢＶＯｇＯに達するのでｓ ｖＯＲＩＣ特性に異常
現象が発生しな（なる。Since the N-buried layer 3a extends to just below the part 9 of the collector region 9 of the PNP transistor or just below the emitter region 8, when increasing the collector-emitter voltage VOE of the PNP transistor, the N-epitaxial growth Since the breakdown voltage BVOgO is reached before the upper and lower depletion layers spread within the layer 2 are connected, no abnormal phenomenon occurs in the svORIC characteristics.
以上のように、この発明によれば、ＮＰＮトランジスタ
のコレクタ領域とＰＮＰトランジスタのベース領域を共
通にして両トランジスタを同一島内に形成した半導体装
置の従来のもののＶＯＥ−ＩＣ特性に発生していた異常
現象が発生しな（なり、実用上の効果が犬である。As described above, according to the present invention, the abnormality that occurred in the VOE-IC characteristics of the conventional semiconductor device in which the collector region of the NPN transistor and the base region of the PNP transistor are shared and both transistors are formed on the same island. The phenomenon does not occur (and the practical effect is a dog.
第１図はこの発明の一実施例を示す断面図。
第２図は従来のこの種の半導体装置の一例の各領域の配
置を示す平面図、第３図は第２図に示す半導体装置のＡ
Ｂ面の断−における内部構造を示す断面図、第４図は従
来のこの種の半導体装置の一例のｖｏＦｉ−ＩＣ特性を
示すグラフ図である。
１・・・Ｐ−半導体基板、２・・・ｙエピタキシャル成
長層、３ａ・・・Ｎ十埋込層、４・・・Ｐ十分離溶、５
・・・ＮＰＮトランジスタのエミッタ領域、６・・・Ｎ
ＰＮトランジスタのベース領域、７・・・ＮＰＮトラン
ジスタのコレクタ領域兼ＰＮＰ トランジスタのベース
領域、８・・・ＰＮＰトランジスタのエミッタ領域、９
・・・ＰＮＰトランジスタのコレクタ領域、１５・・・
絶縁保護膜である。
特許出願人 新日本無線株式会社
第１図
篇２図FIG. 1 is a sectional view showing an embodiment of the present invention. FIG. 2 is a plan view showing the arrangement of each region of an example of a conventional semiconductor device of this type, and FIG. 3 is an A of the semiconductor device shown in FIG.
FIG. 4 is a cross-sectional view showing the internal structure in a section taken along plane B, and is a graph showing the voFi-IC characteristics of an example of a conventional semiconductor device of this type. DESCRIPTION OF SYMBOLS 1...P-semiconductor substrate, 2...y epitaxial growth layer, 3a...N ten buried layer, 4...P sufficient dissolution, 5
... Emitter region of NPN transistor, 6...N
Base region of PN transistor, 7... Collector region of NPN transistor and base region of PNP transistor, 8... Emitter region of PNP transistor, 9
...Collector region of PNP transistor, 15...
It is an insulating protective film. Patent applicant: New Japan Radio Co., Ltd. Figure 1 Part 2
Claims (1)
ンジスタと同一島内に形成した上記ＮＰＮトランジスタ
のコレクタ領域をベース領域とするＰＮＰトランジスタ
とからなる半導体装置において、上記ＮＰＮトランジス
タに対するＮ＋埋込層の領域を上記ＰＮＰトランジスタ
のコレクタ領域の一部の直下若しくはエミッタ領域の直
下まで拡張したことを特徴とする半導体装置。In a semiconductor device consisting of an NPN transistor formed on a substrate and a PNP transistor formed on the same island as the NPN transistor and having a base region that is the collector region of the NPN transistor, the region of the N+ buried layer for the NPN transistor is defined as above. A semiconductor device characterized in that the semiconductor device extends directly below a part of the collector region or directly below the emitter region of a PNP transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60112722A JPS61270866A (en) | 1985-05-25 | 1985-05-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60112722A JPS61270866A (en) | 1985-05-25 | 1985-05-25 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61270866A true JPS61270866A (en) | 1986-12-01 |
Family
ID=14593888
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60112722A Pending JPS61270866A (en) | 1985-05-25 | 1985-05-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61270866A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4841675A (en) * | 1971-09-28 | 1973-06-18 | ||
| JPS56126958A (en) * | 1980-03-11 | 1981-10-05 | Toshiba Corp | Semiconductor circuit element |
-
1985
- 1985-05-25 JP JP60112722A patent/JPS61270866A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4841675A (en) * | 1971-09-28 | 1973-06-18 | ||
| JPS56126958A (en) * | 1980-03-11 | 1981-10-05 | Toshiba Corp | Semiconductor circuit element |
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