JPS61267375A - Planar type hetero junction semiconductor photodetector - Google Patents

Abstract

PURPOSE:To obtain a planar type hetero junction avalanche photodiode with guard ring effect and low noise by reducing the carrier concentration of the second semiconductor in accordance with a distance from a hetero interface. CONSTITUTION:An N-type InP buffer layer 2 and an N<-> type InGaAs layer 3 are successively formed on a sulfer doped N<+> type InP substrate 1 and the layer 2 is a layer for preventing defects and dislocations in the substrate 1 from reaching layers 3-4'' and the layer 3 is a layer for absorbing a light and generating positive hole-electron carriers. An N-type InGaAsP layer 3' is a layer for avoiding delay of travel of positive hole carriers caused by a valence band discontinuity between the InGaAs layer 3 and an InP layer 4 and an N-type InP layer 4'', which has the gradient of carrier concentration, is a layer for forming a P-N junction and generating avalanche multiplication. The N-type InP layer 4 includes a P<+> type conductive layer 5 and a guard ring 5' at its center part. A positive side electrode 7 is provided annularly through a surface protection film 6 and a negative side electrode 8 is formed over the whole backplane.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a planar heterojunction semiconductor light receiving element that has a guard ring effect and enables uniform avalanche multiplication.

(Prior art and its problems) Currently, the 1-1.6 μm band with low transmission loss of optical fiber is the mainstream wavelength range for optical communication, and In0.53G80.
Development of an avalanche photodiode (APD) using a 47As compound semiconductor is progressing. This enO
, 53oaO, 47AS Since it is possible to form a heterojunction with lattice-matched InP, InGaAs is used as a light absorption layer, and only one of the electron-hole carriers generated by photoexcitation is transferred to the InP layer, which is an avalanche multiplication layer. By adopting a structure that transports light and causes avalanche multiplication, a photodetecting element with excellent reception sensitivity can be realized. This concept has already been proposed by Nishida et al. in Applied Physics Letters (Appl, P.
hys, Lett, ), Vol. 35, pp. 251-253 (1979).

FIG. 2 shows an example of the structure proposed by Nishida et al. On an n+-InP substrate 1, an n-InP buffer layer 2, an n-In8.53 Gao layer, a 4yAS layer 3,
After the n-InP layer 4 and the n-InP layer 4' are sequentially grown, a p+ type conductive region 5 is provided to form a stepped pn junction. Here, the stepped p-n junction is defined as a transition from a first conductivity type having a high carrier concentration (in the example of FIG. 2, 5 p+ type) to a conductivity type anisotropic to the first (in the example of FIG. 2, InP This refers to a pn junction in which the change to layer 4 (n-type) is steep. Therefore, when a reverse bias voltage is applied to the stepped pn junction, the depletion layer changes to the conductive region (second layer) with lower carrier concentration. In the illustrated example, it means a junction that selectively extends toward the n-type regions (4 and 3). 6 is a surface protection film that also serves as antireflection, and 7 and 8 are a p-side electrode and an n-side electrode, respectively. In this structure, by applying a reverse bias voltage between the electrodes 7 and 8 and extending the depletion layer with three trenches in the InGaAs layer, light is absorbed by the InGaAs layer, which has a narrow forbidden band width, and only the hole carriers generated there are transferred to the forbidden band. p provided in the wide InP layer 4
It is transported to the n-junction and causes avalanche multiplication.

That is, since voltage breakdown occurs due to InP having a wide forbidden band width, generation of tunnel current from InGaAs is suppressed, and a low dark current light receiving element can be realized.

However, in the structure shown in FIG. 2, the peripheral edge 5a of the selectively formed stepped p-n junction has a center of curvature within the p-type conductive region 5 (this is referred to as "positive curvature"). ), when a reverse bias voltage is applied to the kpn junction, this "positive curvature"
A high electric field is concentrated in the portion 5a, and therefore a voltage breakdown (so-called edge breakdown) occurs at a lower voltage than the pn junction flat portion 5b. This voltage breakdown is especially true for InGa
This is noticeable when the carrier concentration of the As layer 3 is lower than that of the InP layer 4. This fact means that sufficient avalanche multiplication of carriers is not obtained in the flat portion 5b corresponding to the light receiving area.

Self-defense (T, 5hirai et a2>Eg1) is
In order to alleviate this edge-prone breakdown, we have proposed the structure shown in Figure 3 (Electron, Lett
, Vol. 19, pp. 534-535, 1983). In this structure, a p-type conductive region 5' (so-called guard ring) forming a sloped pn junction whose breakdown voltage is higher than that of a stepped pn junction, or a pn junction that can be approximated to a sloped type, is placed at the periphery of the stepped pn junction. The depth from the surface of the p-n junction is
It is provided at a position approximately equal to the depth of the stepped pn junction. Here, a graded pn junction is a pn junction in which the conductivity type of p-type and n-type conductive regions having the same carrier concentration changes gradually (from p-type to n-type, or vice versa) with a carrier concentration gradient. This means that when a reverse bias voltage is applied to a graded pn junction, the depletion layer extends almost equally into the p-type and n-type conductive regions. However, even with the structure shown in FIG. 3, it is difficult to realize avalanche multiplication with suppressed edge breakdown with good reproducibility. The reason is as follows. When a reverse bias voltage is applied, in a stepped p+n junction, the depletion layer mainly extends to the n-type conductive region, whereas in a graded pn junction, the depletion layer extends into the p-type and n-type conductive regions. It is distributed and extended to both conductive regions.

Therefore, when a reverse bias voltage is applied, the stepped p+n junction peripheral depletion layer edge 5a has a positive curvature, as shown in the depletion layer distribution 5c indicated by diagonal lines in FIG. As in the case of , edge breakdown is likely to occur eventually at this positive curvature section.

In addition, H. Ando et al. published an article in Electronics Letters (Electron, Lett, ).
, Vol. 19, pp. 543-544 (1983), or Matsushima (Y.

Matsushima et al., Electron, Lett, 20
As published in Vol. 235-236 (1984), it goes without saying that in structures where the sloped pn junction is located shallower than the stepped p+n junction, the stepped p+
It is impossible to completely cover the positive curvature of the periphery of the n-junction, and therefore, improvements in strength with respect to the problem of edge breakdown are still being sought.

Therefore, the structure shown in FIG. 5, which completely covers the positive curvature portion of FIG. 453, seems to be effective.

Such a female structure Fi8i-APD or Ge-A
This is well known and effective for APDs made of a single semiconductor such as PDs. However, although the inventors tried the structure shown in FIG. 5, it was difficult to realize uniform avalanche multiplication with suppressed edge breakdown. The reason is as follows.

As shown in FIG. 5, since the junction position of the guard ring 5' is closer to the hetero interface between the InGaAs layer 3 and the InPn layer than the stepped p+n junction 5, the electric field strength in the InGaAs layer is lower than that of the stepped p+n junction 5. The area is more of a staircase type p
It is higher than the area below the +n junction. Therefore, the influence of voltage breakdown of the InGaAs layer having a small forbidden band width appears in the guard ring portion. This effect is strongest at the positive curvature part 5'a of the guard ring, and before voltage breakdown occurs at the flat part 5b of the stepped p+n junction, the voltage breakdown occurs at the positive curvature part 5'a of the guard ring outer periphery. It has the disadvantage that it can occur.

Up to now, conventional drawbacks regarding the guard ring effect have been described, but the conventional structures shown in FIGS. 2 to 5 also have the following drawbacks. In other words, the stepped p+n junction is formed using an n-InP layer 4 with a low carrier concentration.
' and the n-InPn series of layers with high carrier concentration, or located in the n-InPn series of layers. This is n
The carrier concentration of the InP layer 4' is ~l Q "am-"
This is because it is difficult to control the position of the stepped p+n junction in such a low carrier concentration InP layer. This situation is shown in Figure 6. 9 in Figure 6 is n-I
This figure shows the hole carrier concentration distribution when a pn junction is formed by thermally diffusing Cd impurities into nP.
Since the carrier concentration of <5 x 1015 cm''3 changes slowly, ~5 x l Q15 cm-'
It can be seen that position control of a carrier concentration of <5 x 10''cm-'' is more difficult than position control of the p-type region corresponding to the above carrier concentration.

This situation also applies to impurities other than CD, such as Be and Zn. However, the lower noise APD'
If you try to make a p-type p-type layer in the n-InP layer,
It is desirable to form a +n junction. This is n −In
This is because forming a p+n junction in the P layer 4' can lower the maximum electric field strength when a reverse bias voltage is applied than forming it in the n-InP layer 4. This is because the ionization rate ratio of holes and electrons, which determines the noise characteristics of APD, increases as the electric field strength decreases, and therefore the noise decreases.

(Object of the Invention) The present invention eliminates the above-mentioned conventional drawbacks, and provides a planar heterojunction AP having a guard ring effect and low noise.
D'i is to provide.

(Structure of the Invention) The present invention provides a first
A heterostructure consisting of a semiconductor layer and a second semiconductor layer having a forbidden band width of E2 (where Eg2>Ego), or an Eg layer between the first semiconductor and the second semiconductor.
3 (where Eg2>Eg3>E, 1), the structure has a heterostructure in which a third semiconductor intermediate layer having a forbidden band width of 1 is inserted, the first semiconductor is used as a light absorption layer, and the second In a heterojunction semiconductor light-receiving element in which a pn junction is selectively provided in a semiconductor layer, the carrier concentration of the second semiconductor is at the hetero-interface between the first semiconductor and the second semiconductor, or at the hetero-interface between the first semiconductor and the second semiconductor. This is a planar heterojunction semiconductor light-receiving element characterized in that the carrier concentration decreases with an arbitrary gradient as it moves away from the heterointerface with the semiconductor of No. 3.

(Operation/Principle of the Invention) The present invention solves the conventional drawbacks by the method described above. In other words, the present invention is constructed from the following two points.

1. The guard ring completely blocks the positive curvature of the periphery of the stepped p+n junction, and also moderates the positive curvature of the periphery of the guard ring to some extent, resulting in further improvement of the breakdown voltage of the guard ring itself. .

2. To provide an AP Df with lower noise by making it easier to control the position of the stepped p+n junction and, as a result, forming the position of the stepped p+n junction in the n-InP layer. In order to satisfy the above two points, InGaAs
The InP layer formed on the light absorption layer is conventionally InGaAs.
As the distance from the layer increases, n(nP, 2 of n-InP layer
In contrast, in the present invention, the carrier concentration decreases with an arbitrary gradient as it moves away from the InGaAs layer (an InP layer is proposed). An example is shown in Fig. 1. The symbols shown in Fig. 1 are the same as in Figs. 2 to 5. As shown in Fig. 1, an n-InP carrier concentration gradient layer is adopted. As a result, the positive curvature of the guard ring periphery is more relaxed than before. In other words, the p-type impurity "i
When diffusing or implanting into an n-type conductive region, the lower the n-type carrier concentration, the deeper the p-type impurity penetrates. A guard ring with a relaxed curvature is formed.

Furthermore, since the carrier concentration of n-InP is sloped, it becomes possible to provide the stepped p+n junction in a relatively low carrier concentration region at position 1InP.

That is, as is clear from the p-type impurity carrier concentration distribution in FIG. 6, the pn junction position is easily controlled to a position where the background carrier concentration of nInP is ~5XIQIIlα-3. Therefore, higher concentrations of 1-3
IQ”cIn-3 background carrier concentration I
Compared to the conventional case in which a pn junction position is provided in the nP, APD with lower noise is possible.

Hereinafter, InP/InGaAs-based heterojunction APDs will be explained in more detail using examples, but other heterojunctions, such as AlGaAs/GaAs-based, A/GaSb-based APDs, etc.
It is easily understood that the same holds true for /GaSb systems, etc.

(Example) In FIG. 1, APD is sulfur doped (S-doped).
n'-InP substrate 1 of
-InP buffer layer 2 (approximately IAm thickness), 3 to 5 cutting Q"c
n-In(1430a0.43
As layer 3 (3.5-4.0 μm thick), wavelength 1.3 μm
InGaAsP layer 3' with a considerable forbidden band width (approximately 0.
1 μyx thick), and includes a carrier concentration gradient layer n-InP4 having a gradient carrier concentration from about 5 x 10"cIn""3 carrier concentration to about 1 x 10" cm-3 carrier concentration. Here, when laminating the n-InP buffer layer 2Fi, the InP
The n-InGaAs layer 3, which is a layer for preventing defects and dislocations of the substrate 1 from reaching layers 3 to 4', has a wavelength of 1 to 4'.
A layer that absorbs light of 1.7 μm and generates hole-electron carriers, n-In (hAsP layer 3' is an InPn seed layer In
The n-InP layer 4 is a layer for preventing a delay in the travel of hole carriers due to valence band discontinuity with the GaAs layer 3, and is a layer for forming a p-n junction to cause avalanche multiplication.

In the center of the n-InPn seed layer, a p-type conductive region 5 (about 80 mm in diameter) is selectively provided in a circular or oval shape when viewed from above.
μ77L), and includes a guard ring 5' (100 μTIL in outer diameter) provided in a ring shape at the peripheral edge of the p+ region. The p-side electrode 7 is provided in a ring shape throughout the surface protection film 6 selectively opened in the p+ type conductive region 5, and the n-side electrode 8 is formed on the entire back surface of the substrate 1.

Layers 2, 3.3', 4.4', 4' are H2SO4:H2O
An InP growth chamber and an InGaAs
It was formed at a substrate temperature of 700° C. by hydride transport vapor phase epitaxial growth method in a reaction tube that is a combination of a P growth chamber and an InQaAs growth chamber. After the epitaxial structure was formed, a guard ring was formed in the next step by beryllium ion implantation. This is because beryllium can easily form a pn junction that can be most approximated to a tilted type. An 8i02 film was laminated to a thickness of about 1 μm on layer 4' at 370°C by pyrolysis chemical vapor deposition method (abbreviated as thermal CVD method), and a ring-shaped pattern was drawn by ordinary exposure technology for forming guard link 5. Using an exposure mask, the 5i02 film is selectively opened using a puffed hydrofluoric acid etching solution, and then beryllium ions are etched at 100-140%.
The implantation was performed under the conditions of an accelerating voltage range of KV and an implantation dose of 5 x 101 scwt-2. At this time, the IJIJium ions are selectively released into the InP layer where the Si02 film is opened and exposed.
injected into the crystal. The 5i02 film was removed by etching with a hydrofluoric acid solution, and then phosphide glass (P) was removed by thermal CVD.
(abbreviated as SG) film ff: approximately 100 nm at 370°C
The guard ring 5 was formed by laminating the layers and performing a heat treatment at 700° C. for 20 minutes to activate and intrude diffusion of the aluminum ions. At this time, the diffused beryllium is
The lower the carrier concentration of n-InP, the deeper the p-type conductive region is formed, so that it takes on a guard ring shape as shown in FIG.

Thereafter, cadmium is thermally diffused at a temperature of 570'C for 20 to 30 minutes through the PSG film, which is selectively opened in a circular shape using an exposure mask inside the guard ring, to form a stepped p+n junction. The p-type conductive region 5 was formed so that the p-type conductive region 5 was located in an InP region having a carrier concentration of 3 to 5.times.IQ"cm.sup.-3.

Next, the PSG film used for thermal diffusion was removed by etching with a hydrofluoric acid solution, and then a SiN surface protection film 6 of 150 to 200 nm thick was deposited at 300 DEG C. by plasma deposition. Thereafter, windows are selectively opened on the p-type conductive region 5 using an exposure mask on which a ring-shaped pattern is drawn using an exposure technique, and titanium, platinum, and gold are sequentially deposited on the p-type conductive region 5 using an electron equilibration deposition method. 100 nm, 100 nm,
The n-side electrode 7 was formed by laminating 300 nm thick layers. Furthermore, AuGe/N is deposited on the entire back surface of the substrate by resistance heating evaporation method.
The APD was completed by forming the n-side electrode 8 using i-alloy.

(Effects of the Invention) In order to check the breakdown voltage of the guard ring, a graded pn junction was also formed by beryllium ion implantation in parallel to the above process using a wafer having the same epitaxial layer structure. The breakdown voltage of the formed sloped pn junction is 1
This is 20 to 150V, which is greatly improved compared to 100 to 10V when a graded pn junction is formed by implanting beryllium ions into the same epitaxial layer structure as shown in the conventional FIG. 3 or FIG. achieved the effect.

The breakdown voltage of the completed APD device is in the range of 100 to 1㎜, and the breakdown voltage of the guard ring is 120 to 150V.
It was lower than Therefore, avalanche multiplication of carriers was sufficiently performed at the stepped p+n junction corresponding to the light receiving area surrounded by the ring-shaped n-side electrode 7. This situation is shown in FIG. In FIG. 7, reference numeral 10 indicates a typical multiplication sensitivity distribution, and it is clear that carrier multiplication is greater in the stepped p-10 junction corresponding to the light-receiving region than in the guard ring portion.

Furthermore, since it is possible to provide a stepped p+n junction position in the n2-InP layer 4' having a medium carrier concentration, noise is lower than the conventional structure in which a p+n junction position is provided in a high carrier concentration layer. was realized. The ionization rate ratio α/β between electrons and holes (α is the ionization rate for electrons, β is the ionization rate for holes), which is used as a noise index, is based on the conventional structure shown in Figures 2, 3, and 5. In the case of the structure shown in FIG. 1, which is an example of the present invention, it was improved to 0.5 to 0.6.

Above, we have explained the structure in which the carrier concentration of InP layered on the InGaAs light absorption layer changes in three stages, but the effect of the present invention is that the carrier concentration of InP changes in three stages. The same was true for cases.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing one embodiment of a planar heterojunction semiconductor light-receiving device of the present invention, and FIGS. 2, 3, and 5 are cross-sectional views of conventional heterojunction semiconductor light-receiving devices. . FIG. 4 is a diagram showing the depletion layer distribution in the light receiving element structure of FIG. 3. Figure 6 shows p in a stepped p+n junction.
FIG. 3 is a diagram showing type conductive carrier distribution. FIG. 7 is a diagram showing multiplication characteristics as an example of the effects of the present invention. In the figure, 1
: Semiconductor substrate, 2: Same type of semiconductor buffer layer as 1, 3:
3': a semiconductor intermediate layer having a full forbidden band width between 3 and 4; 4: a semiconductor layer with a large forbidden band width; 4': the same type as 4 but with a higher carrier concentration than 4; 76% small semiconductor, 4': semiconductor layer with a large forbidden band width having a carrier concentration gradient, 5: p-type conductive region showing a stepped p+n junction, 5': p-type conductive region showing a sloped pn junction,
5 a H5'a: curved part of junction, 5b: flat part of junction, 5c: depletion layer distribution, 6: surface protective film, 7: p-side electrode, 8: n-side electrode, 9: carrier concentration distribution, 10 : Carrier multiplication distribution.
,,・-′-,/l゛・-daiyj(jinbengo±1) January 1. - Figure j Figure 2 Figure 3 Figure 4 Copper Figure 5

Claims (2)

[Claims] (1) The first one having a forbidden band width of at least E_g_1
semiconductor layer and E_g_2 (however, E_g_2>E_g_
1) has a heterostructure composed of a second semiconductor layer having a forbidden band width, the first semiconductor is used as a light absorption layer, and a pn junction is selectively provided in the second semiconductor layer. The heterojunction semiconductor light-receiving device is characterized in that the carrier concentration of the second semiconductor decreases with an arbitrary carrier concentration gradient as it moves away from the heterointerface between the first semiconductor and the second semiconductor. Planar heterojunction semiconductor photodetector. (2) a first band having a forbidden band width of at least E_g_1;
semiconductor layer and E_g_2 (however, E_g_2>E_g_
1) E between the second semiconductor layer and the second semiconductor layer having a forbidden band width of
_g_3 (however, E_g_2>E_g_3>E_g_1
) has a heterostructure in which a third semiconductor intermediate layer having a forbidden band width is inserted, the first semiconductor is used as a light absorption layer, and a pn junction is selectively provided in the second semiconductor layer. A planar heterojunction semiconductor light-receiving device, characterized in that the carrier concentration of the second semiconductor decreases with an arbitrary carrier concentration gradient as the distance from the heterointerface between the first semiconductor and the third semiconductor increases. type heterojunction semiconductor photodetector.