JPS61267347A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device with the resistance presented by its wiring decreased and the cover improved on a step attributable to the wiring by a method wherein a wiring of a three-layer structure is formed wherein a high-melting metal or its alloy is sandwiched between two polycrystalline silicon films. CONSTITUTION:A gate electrode 18 of a three-layer structure to serve as a word line is constituted of polycrystalline silicon film 15, 17 and a metal film 16 sandwiched between the two films 15, 17. On an oxide film 21, a poly crystalline silicon film 22, a metal film 23, and a polycrystalline silicon film 24 are deposited, in that order, for the formation of a bit line 25 of three-layer structure. Electrical resistance is made as low as in a conventional polycite structure and, further, polycrystalline silicon films 17, 24 are laid on the metal films 16, 23 to reinforce the metal films 16, 23. In a semiconductor device of this design, a step that may be produced on the semiconductor surface is pro vided with a coverage approximately similar to that in a design wherein the bit line 25 and gate electrode 18 are built of polycrystalline silicon only.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit which satisfies both low wiring resistance and improved step coverage.
'Relating to the body device.

[Technical background of the invention and its problems]

In general, aluminum, polysilicon with impurities diffused therein, or high-melting point metals such as molybdenum and titanium are used for wiring for circuit configuration in conductor integrated circuits. Compared to the above-mentioned high melting point metals, aluminum is suitable for wiring of integrated circuits because it has low resistance but is flexible and has poor step coverage, but its melting point is low (500℃ culm). It is not possible to apply heat to the wire after wiring.Therefore, multilayer wiring is required for high density integration (multilayer wiring with aluminum is extremely difficult, regardless of the plan.In multilayer wiring, Generally, aluminum wiring is used for the top layer, and polysilicon, high melting point metals, or other compounds are used for the lower layer wiring.

FIG. 2 is a sectional view illustrating the wiring M4 structure of a conventional semiconductor device having multilayer wiring, using a dynamic RAM as an example.

Each memory cell of J, Uni, and RAM shown in the figure is P
A MOS transistor, etc., which uses an N type diffusion layer formed in a type semiconductor substrate 10 as a source 19 and a drain 20, etc.
The N-type diffusion layer 12 formed adjacent to the drain 20 is coated with the first goo 1 to M1! It was attached via 11. 1
- Yapasita lightning pole 13. Each MO8l-transistor G1-electrode 28 constituting the word line of the RAM is covered with a polysilicon film 15 to reduce electrical resistance.
A metal film 16 made of a high-melting point metal or a compound thereof is laminated thereon to have a so-called polyside structure.

A bit line 29 connected to the source 19 of the MO8I transistor is provided on one side of the goo-electrode 28, and this bit line 29 is also made of a polysilicon film 22 and a metal FrJ23 layered thereon. . Furthermore, the V side of the bit line 29 is connected to the electrode 28 (
An aluminum wiring 27 (the connection state of which is not shown) is provided, and the gate electrode 28 and the aluminum wiring 27 constitute a word line. The aluminum wiring 27 functions to further reduce the electrical resistance of the word line.

However, in this J, U1 (conventional wiring drawing); However, due to its high hardness, poor step coverage has become a problem, as it tends to crack or break off at stepped portions.

[Purpose of the invention]

The present invention was developed in view of the above-mentioned problems, and an object of the present invention is to provide a cliff conductor device that avoids reducing the resistance of wiring and improving its step coverage.

[Summary of the invention]

In order to achieve the above object, the present invention provides a semiconductor device F having a three-layer wiring structure consisting of one polysilicon film compound layer.
? It is composed of

[Embodiments of the invention]

The present invention will be explained below with reference to embodiments shown in the drawings.

FIG. 1 is a cross-sectional view showing the wiring structure of an embodiment in which the present invention is applied to a DYNAMIC RAM having the same structure as that in FIG. 2, and the same parts as in FIG. .

In FIG. 1, a first goo 1 is formed on the surface of a ρ-type semiconductor substrate 10.
- After forming the oxide film 11, a UN-type diffusion layer 12 for thermally diffusing phosphorus or the like is formed in a predetermined surface area of the substrate 10.

Next, a polysilicon layer is formed on the surface of the first gate oxide film 11 by a vapor phase growth method or the like, and ions such as phosphorus are implanted into this layer to form a capacitor electrode 13 by a photolithography method or the like.

After that, the first gate I-oxide film 11 in the region where the MOS transistor is to be formed is removed, and then the second gate oxide film 14 is formed. Then, the second gate 1-M film 1
A polysilicon film 15 is formed on the surface of the polysilicon film 15 by a vapor phase growth method or the like, and a metal film 16 made of a high melting point metal or a compound thereof is formed on the surface of the polysilicon film 15 by a sputtering method or the like. This metal film 16 is made of, for example, molybdenum silicide, ditan silicide, etc., and is formed to have a similar property to the polysilicon film 15 and the ohmic contact 1.

Furthermore, a polysilicon film 17 is formed on the surface 1- of the metal film 16 by a vapor phase growth method q, and impurities such as phosphorus are removed from the surface 1- of the polysilicon film 17 into the polysilicon film 15 of the F layer.
Ion implantation was performed to reach the gate and electric field J! using photolithographic techniques. Form i18.

This results in two layers of polysilicon films 15 and 17 and this polysilicon film II! A gate electrode 18 having a three-phase structure made of the metal film 16 formed between J15 and J17 is formed.

This gate electrode 18 extends in a direction perpendicular to the drawing.

After forming the goo 1 to the electrode 18, phosphorus is diffused into a predetermined surface region of the substrate 10 to form a source 19 and a drain 20, which are N+ type expansion layers.

Next, an oxide film 21 is grown on these and the source 1
After opening holes 1 to 9 in the position corresponding to number 9,
Polysilicon film 22, metal film 23 and polysilicon film 2 are formed on the surface of oxide film 21 in the same manner as for goo 1 to electrode 18.
/I is sequentially deposited to form a three-layer structure of pins 1 to 25. This bit line 25 extends in a direction perpendicular to the gate electrode 18.

After that, an oxide film 26 is further formed on these plates, and then the oxide film 26 and 21 are used to form a contact 1 to the gate electrode 16.
- Holes (not shown) are formed at predetermined locations. Then, an aluminum film doped with silicon is formed on the surface of the oxide film 26, and an aluminum wiring 27 is formed using a photolithography method or the like. The gate electrode 18 extends parallel to the electrode 18 and is connected to the gate electrode 18 through the contact ball.The gate electrode 18 and the aluminum wiring 27 constitute a word line.

In this way, C is configured as follows:
Since the gate electrodes 18, which constitute the bit lines 25 and word lines, have a structure in which metal films 16 and 23 are laminated on polysilicon films 15 and 22, their electrical resistance is lower than that of the conventional poly-1-noid structure. The resistance is as low as that of . Further, a polysilicon film 17.24 is formed on the metal film 16.23.
Since the metal films 16 and 23 are reinforced by overlapping the metal films 16 and 23, step coverage similar to that obtained when the pin 1-line 25 and the goo 1-electrode 18 are formed using only one layer of polysilicon is obtained.

[Effects of the Invention] As explained above, according to the present invention, the wiring is made of a two-layer polysilicon film and a high melting point metal or a compound thereof formed between the polysilicon film and the polysilicon film. '434
As a result, it is possible to obtain a high-quality wiring with low resistance and step coverage.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing the structure of an embodiment of a semiconductor device according to the present invention, and FIG. 2 is a sectional view showing the structure of a conventional semiconductor device. 10...Semiconductor V board, 15.17.22.24...
Polysilicon film, 16.23...Metal film, 18...
・Gate electrode, wire to 25...beep].

Claims (1)

[Claims] 1. A three-layer structure consisting of two layers of polycrystalline silicon films on a semiconductor substrate and a high melting point metal or a compound of the high melting point metal formed between the two layers of polycrystalline silicon films. A semiconductor device with wiring. 2. It has multiple interconnects in multiple layers, the top layer interconnect is aluminum interconnect, and the interconnects other than the top layer are two layers of polycrystalline silicon film and a high melting point metal formed between these two layers of polycrystalline silicon film. 2. The semiconductor device according to claim 1, which has a three-layer structure consisting of a layer or a compound of the high melting point metal.