JPS61267157A - Input output control device - Google Patents

Abstract

PURPOSE:To discover rapidly the trouble at the time of transferring the data between the central control unit and the input output device by providing the hardware for automatic transfer at one chip microprocessor, providing the diagnosing part and executing the highly speedy operation. CONSTITUTION:The data transfer executed between an input output device IO and a central control unit CC is executed by providing a first-in first-out memory FIFO. A diagnosing part DIGC is provided which can stop the data transfer request to a direct memory access mode control circuit DMACTL and an input output device direct memory control circuit IDMACTL at the optional time point and at that time only, executes the writing/reading of the contents of the FIFO by the microprogram control, and a microprocessor muP diagnoses the FIFO only, or the FIFO and the IO and the CC (central control unit) diagnoses the FIFO and muP only. Simultaneously, processing is executed for the data from the CC through the FIFO and the data can be transferred to the IO.

Description

[Detailed Description of the Invention] [Summary] The program mode (PM) in which the central controller (CC) writes/reads to/from the control register (REG) in the input/output controller (IOC) is controlled by hardware. The startup and termination of the operation of the input/output control device (IOC) are controlled by firmware, and the transfer control of transfer data (TD) by direct memory access (DMA) is performed by hardware. By including the diagnostic function part controlled by the microprogram, data transfer between the central control unit (CC) and the input/output unit (IO) can be performed at high speed under automatic transfer by hardware, and the above-mentioned Reliability can also be ensured by making the diagnostic function part work.

[Industrial application field]

The present invention provides a central control unit (CC) and an input/output unit (IO).
The present invention relates to an input/output control device (I'OC) that controls the transfer of data exchanged between devices, particularly a high-speed and highly reliable input/output control device (IOC) IC.

For example, in recent years, microprogram control has been introduced into input/output control devices (IOCs) for controlling input/output devices (work 0) such as TIG writers, magnetic chip devices, and magnetic disk devices. Processors that operate under program control are (i) bit slice processors, (ii)
They can be roughly divided into two types: one-chip microprocessors.

Bit slice grosse.

(i) has high speed (approximately on the order of n3) and high processing power, and has been often used as a high-speed input/output control device (IOC). However, this bit-slice processor uses a special microprogram, has a problem with the versatility of the firmware, and has the disadvantage that it is difficult to design both the hardware and firmware. On the other hand, one-chip microprocessors (11) do not have the above disadvantages and are slower than bit-slice processors (approximately μS, 1−/
-), it is very easy to use. In the present invention, the input/output control device (IOC) described below is
) is intended for those controlled by this one-chip microprocessor.

[Conventional technology].

FIG. 9 is a diagram showing an example of a conventional input/output control device using a one-chip microprocessor.

In this diagram, ImInput 0output Con
troller) is the input/output control device, and the common bus C
-Central Controller CC (Central Controller) via -BUS (Common-Bus)
), and also connects to the external bus E-BUS (Exter
nal Bug) via the input/output device fl IO(I
nput 0output ). In addition, in the figure, a magnetic disk device DICU is used as an example of the input/output device IO.
(Disk Unit) is shown, but it may be a typewriter or a CRT display.

The core of the input/output control device IOC is a one-chip microprocessor μP (m1aro Processor), which is connected to an internal bus I-BUS (Internal BUS).
It exchanges signals with the read-only memory ROM and random access memory RAM via the ROM (us). Furthermore, the microprocessor μP is, for example, an open collector type 1"-GT (Ga1e) 1tG
The program mode data register PMREG (Program Mode data
Register), direct memory access mode data register DFv! AREG' (Diroc
tMemory A121361m mode da
taRegist@r). These two registers are further K, respectively) GT2. Connect to common bus C-BUS via GT4. The microprocessor μP also has a direct memory access mode control circuit DMACTL (DIR AET MEM
o ryAccess mode Control c
ircuit ) s interrupt control circuit INTCTL (
Interruption Control Circulation
it ) K is also connected. These circuits DMACTL.

INTCTL, and program mode control circuit PMCTL (Program Mode Cont
rol circuit ) eInput/output control device address verification circuit 10AM (InputOutput Ad
dr@ss Matching circuit) is connected to the common bus C-BUS. Also, internal bus I-
BUS and external bus E-BUS are input/output device control circuit l0CTL (Input Output Control
l circuit).

In FIG. 9, the central controller CC has a common bus C-B.
Although it is connected to multiple input/output control units IOC via US, in the figure one IO connected to the magnetic disk unit DKU is connected.
C is shown as a representative. The functions of each part in each input/output control device IOC are as follows.

(a) The input/output controller address verification circuit IOAM verifies whether the data sent on the common bus C-BUS has an address addressed to itself, and selects the own IOC from among the multiple input/output controllers IOC. This is for selective recognition.

! The program mode control circuit PMCTL controls data transfer under the program mode by the central controller CC.

(e) Program mode control register PMREG is a buffer for data transfer in program mode (PM).

(d) Direct memory access mode data register DMAREG is a buffer for data transfer in DMA mode. (e) Direct memory access mode control circuit D
MACTL performs transfer control in DMA mode.

(f) The interrupt control circuit INTCTL controls interrupt operations.

(2)) The input/output device control circuit l0CTL controls the input/output device 0.

The various functional parts described above perform the following operations, but before doing so, let us clarify the contents of the control register that stores the program control word.

Note that the program control word is stored in the RAM in this conventional example. FIG. 10 is a diagram showing the register configuration of the control register. Note that the program control word is register PMREG.
The data is transferred to the control register on RAM via . As shown in this figure, the program control word is stored in each 16-bit device status register DSR (Device 5ta).
tus Register) and file address register FAR (File Address Reglst).
er) and command register CMR (Command
Register) and memory address register MAR
(M@mo ryAddress Register
) and word count register VOR (Word Co
unt Register ), and addresses 200 to 204, for example, are assigned to this group of registers. This address is the common bus C-BUS
A specific address is given for each input/output controller IOC. The functions of each register are as follows.

(a) The device status register DSR is a flag area that indicates the status of the input/output control device IOC, and displays statuses such as "data transfer in progress" and "data transfer completed".

CO> The file address register FAR is for indicating the file address to which the desired storage data on the magnetic disk device DKU to be accessed belongs.

(c) The command register CMR is used to control starting and stopping of the input/output control device IOC and to specify various operation contents, such as writing or reading.

(d) The memory address register MAR stores read data or C-BUS sent from the input/output device IO to the common bus C-BUS through the input/output control device IOC.
This is to indicate at which address in the main memory MM (Maln Memory) the write data to be sent from the IOC to the workpiece 0 should be stored or from which address it should be read.

(.) The word count register WCR indicates how many words of data are to be transferred, that is, the number of transferred words.

Based on the contents of the various registers above, the input/output control device IO
C works.

■ In order to start up the input/output controller IOC first, the central controller CC uses the file address register FAR.

Writing to the memory address register and word count register WCR is performed in the program mode (PM), and operations for storing the file address, memory address, and number of transferred words, respectively, are started. For example, if rOJ is stored in the file address register FAR, "100" is stored in the memory address register MAR, and "10" is stored in the word count register WCR. At address 100 of MM,
"Transfer 10 words of data."

(2) The input/output control device IOC recognizes in the input/output control device address verification circuit IOAM that the above writing should be performed in its own program mode control register PMREG, and activates the program mode control circuit PMCTL.

(2) Sect the above various information from the central control unit CC into the program mode control register PMREG, send an interrupt signal to the microprocessor μP, and start the microprogram.

(2) Write information in the program mode control register PMRKG to a specified area in the random access memory RAM according to instructions from the microprogram.

After that, the central control unit [CC performs each operation (for example, the input/output device control circuit 10CTL) based on the control information in the RAM.
(for example, reading data from a predetermined sector of the magnetic disk unit DKU).

(2) After repeating the various operations up to the writing of the specified area in (2) above and accumulating the necessary information in the RAM, the central control unit CC writes a command for activating the entire input/output control unit IOC to the command register CMR for the first time. Since writing to this register CMR is also performed by program mode (PM), the registers FAR, M
As in the case of AR and WCH, microprocessor μP
The microprogram is started.

■ Register C according to instructions from the microprogram.
Writes the command in MR to a designated area in random access memory RAM. If this command is, for example, "read", the microprogram activates the input/output device control circuit 10CTL, as in the example described in item (2) above. This control circuit 10CTL activates the magnetic disk unit [DKU that constitutes the input/output device IO and temporarily transfers data read from this device DKU as transfer data (TD).
It is stored in the random access memory RAM via the internal bus I-BUS.

■ The microprogram activates the direct memory access mode control circuit DMACTL and reads data stored in the memory RAM one word at a time.

The direct memory access mode data register DMAREG &C, TOSI is sent via the internal bus I-BUS, and the central control unit CCK is sent via the common bus C-BUS. In this case, as each word is transferred, the register FA
+1 and +1 for the contents of R, MAR and WCH, respectively.
, and -1.

■ When the content of the word count register WCH becomes "0", the microprogram calls the interrupt control circuit INT.
CTL is activated, a termination interrupt is issued to the central control unit CC, and interrupt information is set in the area corresponding to the device status register DSR in the memory RAM.

This completes a series of operations of the input/output control device IOC, and waits for it to be activated again.

[Problem that the invention seeks to solve]

In the conventional input/output control device, since the above-described operation is performed, there are the following two problems.

First, DMA transfer is realized by a microprogram, which reduces data transfer speed. therefore,
A high-speed input/output control device cannot be expected.

Second, if program mode (PM) is activated during DMA transfer, an interrupt is always generated to the microprocessor μP, making the firmware complex.

In addition, as a method to solve the above problems, the input/output device control circuit I0CTL and the random access memory IJR
There is also a concept of performing data transfer with AM in DMA mode. However, even with this method, it is difficult to use the memory RAM and the common bus C-BUS.
Data transfer between the two remains slow, and overall a high-speed input/output control device has not been realized.

[Means for solving problems]

FIG. 1 is a principle block diagram of an input/output control device according to the present invention. Among the components in this figure, those corresponding to those shown in FIG. 9 are indicated with the same reference numerals or symbols. Therefore, the main difference in configuration lies in the introduction of pack memory, such as first-in first-out memory F.
IFO (First In First Out)
This is due to the introduction of Also, along with this, selector 5
EL (5elector) + input/output device direct memory access control circuit IDMACTL (IODi re
a t Memory Acces! ;Co
ntrollelrcuit) etc. have also been introduced. Furthermore, the diagnostic department DIGC (Diagnos-4i
e Cheek) is introduced. The diagnostic department DIGC is
Under the control of the microprocessor μP or central control unit CC, the input/output device direct memory access control circuit IDMACTL, direct memory access mode control circuit DMACTL, and first-in-first-out memory FIFO cooperate to realize the required diagnostic operation. do. More specifically, the first-in-first-out memory FIFO temporarily stores data transferred between the common bus C-BUS and the input/output device control circuit l0CTL. A selector 51eL that cooperates with the memory FIFO selects transfer data from the internal bus I-BUS and the common bus C.
- Select data to be transferred from the BUS.

Furthermore, a control circuit IDMA that cooperates with this memory FIFO
CTL is input/output device control circuit I0CTL and memory F
Controls transfer with IFO.

In the input/output control device IOC shown in FIG. 1, writing to or reading from the control register REG in the device IOC in the program mode (PM) is performed by hardware. Then, when writing command information to the command register CMR that instructs the operation of the device IOC, an interrupt is made to the microprocessor μP, and a microprogram for activating the device IOC is started. When a series of transfer data exchange is completed, that is, when the operation of the input/output device IO is completed, the input/output device control circuit l0C
An interrupt is made from the TL to the microprocessor μP to start the microprogram for the termination operation.

[Effect]

The DMA transfer of transfer data performed between the input/output device IO and the central controller CC often requires the intervention of a microprogram as in the past. Instead, traffic management of the transferred data is entrusted to a storage memory such as a first-in-store memory FIFO. Therefore, the microprogram simply uses the device IO
All that is required is K to start up the input/output device I0 according to the contents of the control register REG when C is started up, and to edit the interrupt information to the central control unit CC and issue an interrupt instruction when the operation of the device IOC ends. In this way, by incorporating more automatic operations by hardware, a faster input/output control device can be realized.

However, first-in first-out memory FI
Since there is hardware for automatic transfer centered on FO, central control unit (CC) and input/output unit (IO)
At first glance, there is a through line between the
P) It is not possible to quickly discover what is causing the failure. Therefore, the operational reliability of the input/output control device IOC naturally decreases. The diagnostic unit DIGC is the device I
This improves the reliability of the OC, and its functions include the direct memory access mode control circuit DMACTL and the input/output device direct memory access control circuit ID.
The first function is to stop a data transfer request to one or both of the MACTLs at any time, and the second function is to write/read the contents of the first-in-first-out memory FIFO only at that time by microprogram control.
It consists of the following functions. This allows the microprocessor μP
Depending on the configuration, you can: ■ diagnose only the memory FIFO, ■ diagnose only the memory FIFO and input/output device 0, or use the central control unit CCK to diagnose only the memo IJ FIFO and microprocessor μP. make it possible to If further necessary, ■Central control unit C
It is also possible to process the data from C through the first-in-first-out memory FIFO and transfer it to the input/output device 0. Based on the diagnosis of ■, ■, and ■ above, first-in first-out memory F-F
It is easy and efficient to identify whether a failure has occurred in the IFO system, the central control unit CC side, the microprocessor μP side, or the input/output device IO side. It can be done accurately. Further, the above-mentioned intermediate processing of data can be applied to, for example, encryption processing.

〔Example〕

Figure 2 shows the memory F excluding the diagnostic section DIGC in Figure 1.
FIG. 2 is a diagram showing an embodiment of the IFO in detail.

In this figure, the same components as those in FIG. 1 are designated with the same reference numerals or symbols. This will be explained below with reference to FIGS. 1 and 2. When explaining this machine, I will outline the functions of the main blocks.

Note that the diagnosis unit DIGC will be described in detail later.

(g) Explanation of the functional outline of the main blocks (Fig. 1).

(Fig. 2) Common bus C-BUS This is a bus that commonly connects the central control unit CC and a plurality of input/output control units IOC, and is used for data transfer.

(2) Input/output control device address verification circuit IOAM This is an address matching detection circuit for verifying addresses assigned to identify each of the plurality of input/output control devices IOC.

(2) Program mode control circuit PMCTL This is a control circuit responsible for transfer control in program mode (PM).

(2) Control register REG This is a buffer register that stores control information for controlling the input/output control device IOC and display information for displaying the internal state of the input/output control device IOC.

■ Microprocessor, μP This is, for example, a 16-pin microprocessor that serves as a command unit for controlling various operations within the input/output control device IOC.

(2) Read-only memory ROM This is a read-only memory that stores the microprogram of the microprocessor μP, that is, the control program.

(2) Random access memory RAM This is a memory used for temporary storage of various information or data used in the above microprogram.

■Interrupt control circuit INTCTL This is a control circuit for controlling interrupt operations.

■ Input/output device control circuit l0CTL This is a control circuit that controls the input/output device IO.

■ First-in first-out memory IFO Common C-BUS and input/output device control circuit l0CTI.

This is a memory that temporarily stores transfer data that goes back and forth between.

■ I/O device direct memory access control circuit ID
MACTL This is a control circuit that controls the transfer of data between the input/output device control circuit l0CTL and the first-in-first-out memory FIFO, and is one of the circuits essential for the diagnostic operation described below.

■ Direct memory access mode control circuit DMAC
TL This is a circuit responsible for controlling the transfer of data in DMA mode between the common bus C-BUS and the memory FIFO, and is one of the circuits essential for the diagnostic operation described below.

◎ Selector SEL Data from internal bus I-BUS or common bus C-BU
This is a selection circuit for selecting data from S and inputting it into the memo IJ FIFO, and also relates to the diagnostic operation described later.

(1) Internal bus I-BUS This is a bus provided within the grosser system centered on the microprocessor μP, that is, a microprocessor bus, and is also related to the diagnostic operation described later.

(6) Description of address map f (FIG. 3) An example of address assignment, ie, an address map, as seen from the microprocessor μP in the input/output control device IOC will be shown below. FIG. 3 is a diagram showing an example of an address map within the input/output control device IOC.

(2) Address 0-OFF is allocated to random access memory RAM.

■ Addresses 1000 to 1004 are input/output control device I
A control register REGK is allocated to buffer program control words for controlling the OC. For more details, please refer to the address 1000゜100, 1002, 10
03 and 1004 are device status register DSR, file address register FAR, and command register CMR, respectively.

A memory address register MAR and word count register WCR are allocated. In the example shown in FIG. 7, addresses 200 to 204 are allocated, and the difference from the above addresses 1ooo to 1004 is that addresses 200 to 204 in FIG. 7 are not addresses when viewed from the microprocessor μP, but are common addresses. This is because it is a specific address (described above) allocated on the z4 bus C-BUS.

■Address 005-3FFF are unused.

(2) Address 4000 is an address for indicating the status of the first-in first-out memory FIFO. What is the memory FIFO status?
This means whether the FIFO is full with transfer data (FULL) or whether the transfer data has been completely sent out and is empty (WTY). Note that these two states are shown in the memo IJ FIFO in Figure 2.
It can be taken out as an electrical signal from the terminal FUL and the terminal EMP.

(2) Address 4001 is a closing area for displaying an interrupt instruction to the common bus C-BUS.

(2) Address 4002 is allocated to a control register K (provided in the input/output device control circuit 10CTL) for buffering control information for controlling the input/output device IO.

■ Hatching portions below address 4003 are unused.

(2) Address 5ooo is an area allocated for designating writing or reading of the first-in-first-out memory FIFO, and becomes valid during diagnostic operation by the diagnostic unit DIGC.

■ Address 8001 is “DIR”, “ID”
MAEX” and “DMAIX”. Among the information on these champions, especially the latter two “lDMA Hiro”
DMAIJ is valid in the diagnosis mode described later, and starts (Excite) the input/output device direct memory access control circuit IDMACTL and the direct memory access mode control circuit DMACTL, respectively.
This is the ninth piece of information.

DIR (Direction) is assigned to transfer direction designation information for specifying the transfer direction of transfer data TD, and when the information bit DIR is 'O', data is transferred from the magnetic disk unit DKU to the common bus C-BUS. (DKU-+C-BUS), which means a read operation (Read) of stored data.

On the other hand, when the information pin) DIR is “1#”, the common/
Data is transferred from the 4th C-BUS to the magnetic disk unit DKU (C-BUS-+DKU). That is,
It means a write operation (Writ.) of stored data. Note that this transfer direction designation information DIR is the transfer direction designation information DIlζ-F/F (D
This flip-flop, fDIR-F/F, is set or reset by the microprocessor μPK via the internal bus I-BUS based on the information in the command register CMR shown in FIG. be done.

■ Hatching portions below address 8002 are unused.

■ Addresses 1000-FFFF are allocated to read-only memory ROM.

(Q. Explanation of the general operation within the IOC (Figures 4A, 4B, and 4C) The details of the operation within the input/output control device IOC will be described later, but
Here, the characteristic movement of the present invention will be explained using a flowchart.

(2) In the input/output control device IOC according to the present invention, various registers FAR are sent from the central control device CC.

Write/read control for the memory and WCR is performed by the program mode control circuit PMCTL, and therefore does not require control by a microprogram. Therefore, high-speed input/output control can be achieved while using an inexpensive single microprocessor.

Specifically, the contents of the word count register WCH are O.
7'
Which transfer direction is specified by DIR-F/F?
First in first out memory FIFO is FU
Control is performed based on the dominant factor of LL, EMPTY, or none of these, and data transfer is performed so as to seemingly pass through the internal circuit of the device IOC. (-Because the data transfer is performed visually, the diagnostic operation described later becomes useful.) ■ When command information is set in the command register CMR from the central controller CC, the microprocessor μP
An interrupt occurs, and thereafter the operations shown in the flowchart roughly shown in FIGS. 4A to 4C are performed.

, ■ Fig. 4A is a flowchart showing a series of operations associated with writing to CMR. When writing to command register CMR, first register 7, FkR, CMR, MAR and Each piece of information in the WCR is stored on the random access memory RAM (step &). Furthermore, according to the command information in the register CMR, the transfer direction designating flip-flop, zoDIR
-F/F (address 8001 in FIG. 3) is set, and the input/output device control circuit I0CTL is activated. Furthermore, the input/output device control circuit 10CTL starts up the input/output device IO and then controls it to prepare for data transfer (step b).After starting up the input/output device IO, the microprogram waits for an interrupt. If the contents of the command register CMH stored in the memory RAM in step a above are "read", the output of the transfer direction specifying flip-70 DI RF/'F is 'O'. In this case, if the first-in-first-out memory FIFO is not in the FULL state, that is, if there is a free area in the memory, the input/output device direct memory access control circuit IDMACTL is activated, reads data from the input/output device control circuit l0CTL, and transfers the data to the memory FIFO. and set the memory FIFO to
When the control circuit IDMACTL reaches the FULL state, activation of the control circuit IDMACTL is canceled.

First-in first-out memory FIFO is EM
If it is not in the PTY state, that is, if some read data exists in the memory FIFO, it is transferred to the common bus C.
- Send to BUS. When it is sent, it automatically adds +1 to the memory address register and stores it in the main memory M.
Update the next write address on M. Also, register F
The contents of AH are also incremented by 1, and the contents of register prefecture 1 are incremented by -1.

Thus, read data from the input/output device IO is automatically sent to the common bus C-BUS.

In the above step a, nine pieces i are stored in the memory RAM.
If the content of the command register CMH is "write", the output of the transfer direction designating flow, DIR-F, is 1.
becomes #. At the time of writing, data is transferred smoothly using the memory FIFO, as in the case of reading above, and operations to set registers MAR, F'AR, and WCR by +, +1, and -1, respectively, are also automatically performed by hardware. .

(2) FIG. 4B is a flowchart showing a series of operations accompanying the l0CTL end interrupt. When the transfer of a predetermined amount of data is completed, the control circuit l0CTL issues an interrupt to the microprocessor μP. At this stage,
There is a possibility that transfer data may still remain in the memo IJ FIFO, so after confirming that the contents of the FIFO are empty, the interrupt control circuit INTCTL K interrupts and the series of data transfers ends. Ste, de eVc o-
Then, it is checked whether the termination of the control circuit 10CTL is a normal termination (YBS) or not (No). If the end is normal, Stella 7'd is reached. Memory FI with Stellagy d
Check whether the FO status is EMPTY or not, and
After confirming that it is Y, move to Stella 766. In step e, a normal interrupt status is set in the device status register DSR, and in step f, an interrupt instruction is sent to the interrupt control circuit INTCTL.

If it is determined in Stella 7'e that the termination is not normal, or if it is determined that there is an error in the common bus C-BUS, the process goes to step g and ends.

In this step, the device status register DS
Abnormal interrupt status is set to H. Note that this end interrupt operation may not be performed immediately in response to an interrupt request from l0CTL, but may be performed as a result of multiple activations of l0CTL.
This is a diagram showing steps # and # when a US error occurs, and step h shown here is connected to step g in FIG. 4B via the * mark in the diagram. When a failure occurs on the common bus C-BUS side, the internal circuits such as the memory FIFO are cleared, but at this time, by looking at the contents of registers MAR, WCR, etc., it is possible to determine which part is causing the error. . It should be noted that the fact that a failure has occurred on the common bus C-BUS side becomes immediately clear through diagnosis, which will be described later.

(p Explanation of the operation inside the IOC (Fig. 1) When activation is activated from the central control unit CC, writing is done to the control register REG. In this case, writing to the command register CMR is important, and this writing is As a condition, an interrupt is issued to the microprocessor μP.This interrupt instruction path is indicated by line L1 in FIG.

When an interrupt occurs, the microprogram reads the contents of the control register REG and analyzes what to do.

This analysis is done using memories ROM and RAM. As a result, when it learns that input/output device 0 should be activated, it starts up, for example, the magnetic disk device DKH.

Data transfer between the activated device DKU and the common bus C-BU8 is performed directly using the first-in first-out memory IJ FIFO without using the internal bus I-BUS.
Do it via. As is well known, the memory FIFO outputs the first input data first. °The input at this time is done through the selector SEL "k. IO and FI
Data transfer between FOs is mainly controlled by the input/output device direct memory access control circuit IDMACTL. This control circuit IDMACTL operates under the following conditions. In this case, although a startup instruction is issued from the microprogram, the contents of the memo IJ FIFO are actually dominant.

First, if the memory F'IFO is in the EMPTY state,
Input/output device direct memory access control circuit IDMA
Start CTL and load the read data from the magnetic disk drive device DIGJ into the memory FIFO. If the memory FIFO is not in the EMPTY state, the gray left memory access mode control circuit DMACTL is activated and the read data in the memory FIFO is sent to the common bus C-BUS. As a result of this sending, if the memory FIFO is no longer in the FULL state, the control circuit IDMA again
Activate CTL and pack read data from device DKU into memory FIFO. The same process is repeated thereafter.

That is, the moment the memory FIFO becomes clogged and is no longer in the EMPTY state, the control circuit DMACTL is started, and conversely, the moment the memory FIFO is read out and is no longer in the FULL state, the control circuit IDMACTL is started. In the end, transfer data flows in and out of the memory FIFO without interruption. In this case, even if there is an imbalance between the amount of transferred data and the amount of people, the memory FIFO absorbs the difference between the two amounts. This absorption capacity is determined by the capacity of the memory FIFO. 'Of course, the larger this capacity is, the greater the ability to apparently eliminate the above imbalance.

In FIG. 1, GT3 is, for example, an oven collector type gate, and is connected to an internal bus I-BU8 and a memory IJ FI.
This enables selective separation from the system in which FO exists. In addition, the transfer group (TG) controls the control circuit DMACTL depending on whether data is transferred from the common bus C-BUS (at the time of writing) or data is transferred to the common bus C-BUS (at the time of reading).
Opening/closing is selectively controlled by. Furthermore, a termination interrupt from the input/output device control circuit l0CTL (see Figure 4B)
is notified to the microprocessor μPK via line L2.

@ Explanation of the operation inside the IOC (Fig. 2) The characteristics of the input/output control device IOC of the present invention are firstly high speed and secondly high reliability. The high speed is due to hardware-based transfer control as shown in FIG. First, the microprocessor μP (FIG. 1) starts up the magnetic disk unit DKU, which serves as the input/output device IO, via the input/output device control circuit I0CTL. Then, it instructs data transfer. When there is a data transfer instruction (for example, when reading from the disk device DKU), the read data is supplied from the device DKU to the memory FIFO. This supply is as follows: device DKU→control circuit l0CTL→line L3→
This is done through the path from selector SEL to input terminal Din. The condition for executing such a read (instructed from IDMACTL) is that first, the transfer direction designating free flag-flop DIR-F/F C (address 8001 in FIG. 3) is '0'.
”(Read).This DIR
'0' from -F/1' is gate Gl (and r-t)
'O# is applied to one input of the other input.
If is input, Gl becomes open (note - the small ○ mark in the input indicates negative logic, the same applies hereinafter). In other words, r
-) G1 is open unless the memory FIFO is in the FULL state. Note that the other input of Gl is connected to the terminal FUL K of the memory IJ FIFO through line L4.

By opening r-gate G1, input/output device direct memory access control circuit ID is accessed via gate G3 (OR gate).
MACTL is activated, a read instruction signal RD is sent out, the control circuit I0CTL is designated to read mode (R), and reading of data from the device DKU is started.

Conversely, WT represents a write instruction signal, and the control circuit l0CTL
W in the box represents the write mode.

In this way, the data read from the magnetic disk unit DKU enters the memory FIFO through the selector IL via the line L3.
The condition for switching to the input terminal Sl side is that it is not during writing. Note that the input terminal S3 of the selector SEL is connected to the supply terminal of the write instruction signal WT' from the control circuit IDMACTL via the line L5. In this case, the memo IJ FIFO must also be in write mode (W), but this condition is.

The input/output device direct memory access control circuit IDMACTL which passes through the gate G5 (OR gate) is obtained by the write instruction signal WT'.

When the memory FIFO is no longer in the FULL state, the read data stored in the memory FIFO is transferred to the output terminal. ut to the common bus C-BUS. To read store data to this common bus C-BUS, first the memory FIFO is set to read mode (R).
It has to be≠. The readout instruction signal RD is
This is done by applying it to the memory FIFO via line L7 and gate G4 (OR date).

In this case, the activation conditions of the control circuit DMACTL are transfer direction designation free, output of Zoflozzo DIR-F/F (currently
'O'') as one input r-toG6 (and r-)
) are all 0", and by opening G6, the control circuit DMACTL is activated through r-to-G9 (OR gate), and the control circuit DMACTL is activated from the mesori FIFO to the common bus C-BUS. Transfer of store data begins.

the above? -) The following three types of signals are applied to the other three human forces marked with "=" in G6. The first is the time monitoring unit TIMSV (T1m5Supervi) via line L9.
a common bus (C-BUS) timeout signal provided by the second memory via line LIO;
EMPTY signal given from FIFO terminal EMP,
The third is the WCR=O signal provided by register WCR in control register REG via line Lll.

Upon receiving these signals, when there is no common bus timeout, the memory FIFO is not in the EMPTY state, and the word count (WCR) number is not O? -) G 6 becomes open. The common bus timeout mentioned above is a timeout of the control signal 5CTL to the common bus C-BUS side, and the control circuit DMACTL controls the memory FIFO
This is a case where the central controller CC does not receive a response even after a certain period of time has elapsed, although the request to send the store data in the 5cTL to the common bus C-BUS was sent using the signal 5cTL.

Every time data is read from the memory FIFO, the contents of the memory address register MAR are transferred to the control circuit DMACT.
+1 due to L. On the other hand, word count register W
The contents of CH are sequentially decremented by -1. The control circuit DMACTL finishes sending data to the common/4-channel C-BUS just in case the contents of the WCR become O. This is common both when reading and writing data, and the information of WCR=0 is commonly applied to G6 and G7. or,
In addition to the information that WCR=O, information that the memory FIFO is MTY (at the time of reading) is also essential for deactivating the control circuit DMACTL.

Similarly, in the case of writing, a certain amount of data transfer is set, so if the contents of register wcR are not yet 0, data is transferred from the input/output device IOC side (DMA mode mask side) to the central control unit side (DMA mode mask side). Write requests to the device DKU are generated one after another from the slave side of the device DKU. This write request is sent to the transfer direction specified frizzo flop 7'DIR-F/
The output of F is 1", that is, it is in the write mode, and the gate G7, which has one input of 11" of
When all three types of signals applied to the other three input terminals of 7 are MO'', it becomes open and activates the control circuit DMACTL for writing.The three types of signals referred to here are WC,
Information indicating that R=O, information indicating that the memory l◆'IFO is in the FULL state, information indicating the common bus timeout from gate G8, and common bus/mother error. This will be a three-person effort. Note that the output information from G8 also serves as interrupt information 3NT to the microprocessor μP. The information PK indicating the common bus t4 property error is /J? The output from the quality check unit PTYCHK is output from the input terminal S2 of the selector SEL.
A /4 property check is performed on the write data on the common bus C-BUS to be applied to the input terminal D1n of the memory FIFO.

By opening G8, the control circuit DMACTL sends out a write instruction signal WT, which is applied to the memory FIFO via G5 to set the write mode (W). On the other hand, unless the contents of the memory FIFO are EMPTY, the control circuit IDMACTL continues to be activated and the write instruction signal W
By sending T to the control circuit l0CTL, it is set to write mode (W). Note that before this, the control circuit l was transferred from the microprocessor μP to the disk unit DKU.
A write command has already been issued via 0CTL.

■ Explanation of FIFO (Fig. 5) Since the first-in first-out memory FIFO occupies an important position in the present invention, an example thereof will be given below. Fig. 5 shows a specific example of the first-in first-out memory FIFO. It is a figure.Symbol D1 in this figure
For n, Dout, W, R1FUL and W, the second
This is as explained in the figure. Write data (Di
n) is temporarily stored in the memory MEM, and is taken out as read data (Dout) in order from the first one entered. These write and read operations are performed by address signals from multiplexers 1 and 2. Multiplexer MPX has write address counter WAC
(Writ@Address Count@r) or read address counter RAC (Read Address Count@r)
ss Counter ).

The counter WAC is incremented by 1 each time the write instruction signal WT (Fig. 2) is generated, and the counter RAC is incremented by 1 each time the read instruction signal RD (Fig. 2) is generated, and the corresponding data is written or read. .Counter R
When the content of AC reaches the predetermined maximum value, the comparator CMP
(Comparator) sends out a signal indicating the #'I'Y state from the EMP terminal, and conversely sends out a signal indicating the FULL state from the FUL terminal when the contents of counter WAC and counter RAC become equal.

(Q. Explanation of diagnosis mode (Figures 6A to 60)) As already mentioned, the input/output control device IOC of the present invention is high-speed because the transfer control is mainly performed by hardware.However, on the other hand, the automatic Due to the transfer, the communication between the central control unit CC and the input/output device 0 appears to be through, so when a failure occurs, it is difficult to discover where the cause of the failure is. A diagnostic unit DIGC will be provided to perform fault detection under a unique diagnostic mode.

FIG. 6A is a schematic block diagram of the memory FIFO in diagnostic mode. This is a so-called FIFO diagnostic mode, and the direct memory access control circuit DMACTL
Also input/output device direct memory access control circuit IDM
ACTL also stops the above-described data transfer instruction to the memory FIFO. Therefore, the control circuits DMACTL and IDMAC'rL are not depicted in FIG. 6A. In this way, the central control unit CC and the input/output device IO are first separated from the memory FIFO.

Next, under the control of the microphone tube 0hem from the microprocessor μP, predetermined diagnostic data D is sent via route I in the figure.
D (Diagnostic check Data
) is written to the memory FIFO and read out to the microprocessor μP through the route ■. Memory FIF
If there is no abnormality in O, the diagnostic data DD is correctly returned to the microprocessor μP.

FIG. 6B is a schematic diagram of the memory IJFIFO and the input/output device IO in the diagnostic mode.

This is a so-called FIFO/IO diagnostic mode, and the direct memory access mode control circuit DMACTL stops the data transmission instruction to the memory IJ PIPOK, and the input/output device direct memory access control circuit IDMACT
Only L operates normally. As a precaution, only the control circuit IDMACTL is depicted in FIG. 6B. In this way, the central controller CC is first separated from the memory FIFO and input/output device IO system.

Next, under microprogram control from the microprocessor μP, predetermined diagnostic data DD is written into the memory FIFO via route I in the figure, and this data is transferred to the FIFO again.
Read from O and write to input/output device IO via route ■. The DD written in the device IO is read out through the route (2) and written into the memory FIFO, and then read out again through the route (2) to the microcomputer and the μP. If there is no abnormality in either the memory FIFO or the device IO, the diagnostic data DD is correctly returned to the microprocessor μP. if,
If the diagnostic data DD is not returned correctly, the memory FIFO
There is an abnormality in one or both of and equipment engineer 0,
An alarm indicating the occurrence of a failure is sent by the microprocessor μP.

In this case, it is also necessary to detect whether the fault is in the memory FIFO or the device IO. If the memory FIFO is normal, it can be determined that there is a failure on the device IO side. If the memory FIFO is abnormal, please write a note +) PI
FOK% There is a possibility that a failure has occurred in the device IO, so in this case, repair the memory FIFO and restore the device IO.
Search for obstacles. In addition, the nine notes mentioned above! 7 FIFO
To check the normality or abnormality of
All you have to do is set the IFO diagnostic mode.

Figure 6C shows the memory FIFO and common bus C-BUS.
2 is a schematic diagram of the diagnostic mode for the

This is a so-called FIFO/C-BUS diagnostic mode, and the input/output device direct memory access control circuit IDMA
CTL stops the data transfer instruction to the memory IJ FIFO and direct memory access mode control circuit DMA
Only the control circuit DMACTL is depicted in FIG. 6C. In this way, the input/output device IO is first separated from the memory IJ FIFO and central control unit CC system.

Next, under microprogram control from the central controller CC, predetermined diagnostic data DD is sent via route I in the figure.
is written into the memory FIFO, read out from the FIFO again, and taken into the microprocessor μP via route (3). The microprocessor μP reads out the 9DD again through the route ■, writes it to the memory FIFO, and transfers it again to the central controller CC through the route IV.
Read out. If there is no abnormality in either the memory FIFO or the common bus C-BUS, the diagnostic data DD is correctly returned to the central controller CC. If the diagnostic data DD is not returned correctly, there is an abnormality in either or both of the memory FIFO and the common bus C-BUS, and an alarm indicating the occurrence of a failure is sent out from the central controller CC.

In this case, in addition, the memory FIFO and the common bus C-B
It is necessary to detect which US has a fault. If the memory FIFO is normal, the common bus C-BU
It can be confirmed that there is a failure on the S side. If the memory FIFO is abnormal, there is a possibility that a failure has occurred in both the memory FIFO and the common bus C-BUS.
Repair the IFO and search for failures in the common bus C-BUS. Incidentally, in order to check whether the above-mentioned memo IJ PIFOK is normal or abnormal, it is sufficient to set the FIFO diagnosis mode shown in FIG. 6A.

FIG. 7 is a schematic block diagram in data processing mode using the microprogram μP. In this data processing mode, arbitrary transfer data TD given from the central control unit CC is processed by the microprocessor μP and inputted into the input/output device 1011C% as processed data td. Therefore, in this mode, both the direct memory access mode control circuit DMACTL and the input/output device direct memory access control circuit IDMACTL operate normally.

Note that the processed data td can be used, for example, as encrypted data (confidential data).

First, the control circuit DMACTL writes the processed data TD from the central control unit CC through the route I to the memory FIFO, and then reads it from the memory FIFO and reads it out from the central control unit CC through the route I.
I to the microprocessor μP.

Here, certain data processing is performed, and the processed data td
(as RU) III to the memory FIFO. Further, data td is read out from this via route IV and written to the input/output device IO from the control circuit IDMACTLK. For example, encrypted data can be stored here.

0 Explanation of the diagnosis section DIGC (Fig. 8) Fig. 8 shows the diagnosis section DIGC that cooperates with the memo IJ FIFO Ic.
It is a figure which shows the detailed example of C. In this diagram, C-BUS
.

E-BUS, I-BUS, SEL, F
IFO etc. have already been explained. In addition, “DIR” and “IDMAEX” shown directly below the center of this figure
and “DMAα” as well at the address 800 in Figure 3.
It has already been explained as 1. This DIR" is DIR-F/
'F, and this DIR-F/ is simply represented by a double beam in the lower part of the center of FIG. But in reality,
As shown in FIG. 8, it consists of three D-shaped Frizzo flops and is indicated by the reference symbol in the same figure. This pretend,
Data o y f F7'F has three D inputs, ,D,
and D2 and three Q outputs QO=QI and Q2 and a clock input CK. Qo ratio output, transfer direction designation information DIR is sent out, Ql output is activation information I to the input/output device direct memory access control circuit IDMACTL, DMAEX is sent out, and Q2 output is activation information DM to the direct memory access mode control circuit DMACTL.
Send AEX. The activation information IDRMIX instructs whether or not to perform transfer between the input/output device control circuit I0CTL and the first-in-first-out memory FIFO. The activation information DMAIX indicates whether or not a transfer is to be performed between the memory FIFO and the common bus C-BtlS (L, thus the central control unit CC).

In other words, if the activation information DMAEX is 1", the control circuit D
Activate MACTL, and if activation information IDMAEX is 1#, activate control circuit IDMACTL. An important point of the diagnostic unit DIGC is that it is controlled by this activation information.

For example, in the case of data transfer from read IO to FIFO), the transfer direction designation information DIR is 'O
It is #. In this case, one of the conditions for opening gate 21 (AND gate) and gate G22 (AND gate) is satisfied. Furthermore, memory PIFO75E FUL
If it is not in the L state and the startup information IDMAEX is 1#,
A write request WRK Q 1 to the control circuit IDMACTL is outputted from the f gate G22, and the read data f from the input/output device IO is written to the memory FIFQ.

Also, if the transfer direction designation information DIR is 0#, the memory FIFO
is not in the EMPTY state and the startup information DMAEX is '1'', the r-to-G21 is opened and the control circuit D
A read request RRE Q 2 to MACTL is output. As a result, data is read from the memory FIFO and sent onto the common bus C-BUS.

On the other hand, in the case of writing (data transfer from FIFO to process 0), the transfer direction designation information DIR is 1#.

In this case, gate 20 (and gate) and r-)2
One of the conditions for opening 3 (andf gate) is satisfied. Furthermore, if the memory FIFO is not in the FULL state and the startup information DMAEX is '1', r-)G2
3 is open, and a write request W to the control circuit DMACTL is made.
Rg Q 2 is output. From this button, common bus C-
Transfer data from the BUS is written to the memory PIFO.

Also, if the transfer direction designation information DIR is 1", the memory FIFO
is not in the EMPTY state, and the startup information I DMAE
When X ii''1m, the gate G20!>Z is opened and a read request RREQ1 is output to the control circuit IDMACTL. As a result, data is read from the memory FIFO and written to the input/output device 0.

In this way, the above-mentioned various requests (RREQI.

RRE Q 2 etc.) is formed. This 7 rippufuro, 7'F/F' Tsukuo Tsuku input CKK &'l'-)G
24 (AND gate) is received. Gate G2
4 is address 8001 (3rd
In the figure, a clock/IP pulse is applied to the clock input CK every time a write command WRITE is issued. Also, an internal bus I-BUS is connected to the microprocessor μP.
various commands are given to the D inputs Do, Dl and D2.

Data is read from the first-in-first-out FIFO every time a read command READ is issued from the microprocessor μP to address 5ooo (FIG. 3). For example, the r-t G30-
Of G35 (AND gates), G35 is open (G30 is open when the write command is WRITE), and gate G4 is opened.
The memory FIFO is set to read mode (R) through G42 of 0-G42 (OR gate). At this time, gate G5°0 (AND gate drawn at the lower right of FIFO) also becomes active, activating gate G51 (transfer gate) and opening the path to internal bus I-BUS.On the other hand, The path to the external bus E-BUS is opened by the transfer gate G52 () activated by IDMAEX.
In the case of reading during MA transfer, r-to-G33 and G34 are sent by DMACTL read request DMARD or read request IDMARD from IDMACTL.
Let's open. Therefore, these gates G33 and G
34 corresponds to a more detailed breakdown of FIG. 2 (71''-)G4.

Data is written to the first-in-first-out memory FIFO from the microprocessor μP by 5ooo.
This is performed every time a write command (WRITE) is issued to an address. The break is the goo drawn above the center of Figure 8) G6
0 (and gate), activates G61 (transfer gate) and connects the internal bus I-BU.
Opening the path from S and also opening the path from -BUS to the external bus is DATA)G62()transfer gate] activated by activation information IDMAEXK. In addition, in the case of writing during normal DMA transfer, write request DMAWT or ID from DMACTL
Gates G31 and G32 are opened in response to a write request IDMAWT from MACTL. Therefore, these gates G31 and G32 correspond to a more finely broken down gate G5 in FIG.

〔Effect of the invention〕

As explained above, according to the present invention, although it is an input/output control device using a one-chip microprocessor that is inexpensive, easy to use, and low-speed, the one-chip microprocessor is slow. By supplementing this with hardware, a substantially high-speed input/output control device is realized, and it also takes into account diagnostic measures in the event of a failure, which tend to be difficult due to the introduction of this hardware, and enables quick failure recovery. A highly reliable input/output control device is realized.

[Brief explanation of drawings]

Fig. 1 is a principle block diagram of the input/output control device according to the present invention, and Fig. 2 is a memo IJ excluding the diagnostic section DIGC in Fig. 1.
FIG. 3 is a diagram showing an example of an address map in the input/output control device IOC; FIG. 4A is a flowchart showing a series of operations associated with writing to CMR; FIG. 4B The figure is a flowchart showing a series of operations associated with the l0CTL end interrupt, Figure 4C is a diagram showing the steps associated with the occurrence of a C-BUS error, and Figure 5 is the first-in first-out memory FIF.
Figure 6A is a schematic block diagram of Memo+J PIFOK in diagnostic mode; Figure 6B is Memo! 7 Schematic block diagram for FIFO and input/output device IO in diagnostic mode 9, Figure 6C is a schematic block diagram for memo IJ FIFO and common node C-BUS in diagnostic mode, Figure 7 is based on Micro Zoroce, μP Schematic block diagram in data processing mode, Figure 8 is the diagnostic unit DIGC that cooperates with the memo IJ and FIFOK.
FIG. 9 is a diagram showing an example of a conventional input/output control device using a one-chip microprocessor, and FIG. 10 is a diagram showing a register configuration of a program mode data register PMREG. IOC...input/output control device, CC...central control device, ■0...input/output device, C-BUS...common bus,
μP...Microprocessor, I-BUS...Internal bus, E-BUS...External bus, l0CTL...
Input/output device control circuit, FIFO...first-in-first-out memory, DMACTL...direct memory access mode control circuit, IDMACTL
...I/O device direct memory access control circuit,
PMCTL...Program mode control circuit, SEL/
...Selector, IDMACTL...I/O device direct memory access control circuit, DMACTL...Direct memory access mode control circuit, DIGC...
Diagnosis section, G20-023...logic gate. Fig. 3: A flowchart showing a series of operations associated with writing to CMR Fig. 4A: A flowchart showing a series of operations associated with an end interrupt of l0CTL Fig. 4B: A diagram showing steps associated with the occurrence of an arrow C-BUS error Fig. 40: IFO First FIG. 5 is a diagram showing a specific example of an in-first-out memory FIFO. FIG. 5 is a schematic block diagram of memory FIFO in diagnostic mode. FIG. 6A is a schematic block diagram of DD...diagnostic data in diagnostic mode. Figure 7 ↓d...Processed data PMREG Diagram showing the register configuration of program mode data register PMREG DSR...Technical status register FAR...
File address register CMR...Command register MAR...Memory address register WCR...Word count register Procedure amendment August 7, 1985 Commissioner of the Patent Office Black 1) Akio Tono 1, Display of the incident 1988 Patent Application No. 108337 2, Name of the invention Input/output control device 3, Relationship with the amended case Patent applicant name (522) Fujitsu Ltd. 4, Agent address 8-chome Toranomon, Minato-ku, Tokyo 105 No. 10 No. 5,
Drawing subject to correction (Figure 1) 6. Contents of correction The drawing (Figure 1) will be corrected as shown in the attached sheet. 7. List of attached documents

Claims (1)

[Claims] 1. Central control unit (C-BUS) via common bus (C-BUS)
C), and also connects to the input/output device (IO) via the external bus (E-BUS), and connects to the central control device (CC).
) and an input/output device (IO), and at least executes a microprogram using various information supplied from a central controller (CC). microprocessor (
μP) and the program mode control circuit (PMC), which is connected to the common bus (C-BUS) and controls transfer under program mode.
TL) and an input/output device control circuit (IOCTL) that connects to an external bus (E-BUS) and controls the input/output device (IO) according to instructions from a microprocessor (μP). Input/output device control circuit (I
An input/output control device that transfers the data between a common bus (C-BUS) and a common bus (C-BUS) includes a buffer memory in which the transferred data is once written and then read out, and the buffer memory and an input/output device control circuit (IOCTL). An input/output device direct memory access control circuit (I
DMACTL), a direct memory access mode control circuit (DMACTL) that controls the data transfer between the buffer memory and the common bus (C-BUS), and an input/output device direct memory access control circuit (IDMACTL) or direct memory. Access mode control circuit (DMAC)
a diagnostic unit (DIGC) for temporarily stopping the request for data transfer to one or both of the TL) and executing writing/reading to/from the buffer memory by the microprogram; μP) is the central controller (
When the data transfer request is received from the CC), it is activated by receiving an interrupt directly via the program mode control circuit (PMCTL), and when the data transfer is completed, the data transfer request from the input/output device control circuit (IOCTL) is The diagnostic unit (DIGC) operates to cancel the activation caused by the data transfer request in response to the end interrupt, and the diagnostic unit (DIGC) is a diagnostic unit that transmits and receives diagnostic data (DD) only between the buffer memory and the microprocessor (μP). a second mode in which diagnostic data (DD) is exchanged only between the buffer memory, the microprocessor (μP), and the input/output device (IO); and a second mode in which diagnostic data (DD) is exchanged only between the buffer memory, the microprocessor (μP), and the central control unit. An input/output control device characterized by selectively setting at least three modes including a third mode in which diagnostic data (DD) is exchanged only between CC and CC. 2. The input/output control device according to claim 1, wherein the buffer memory is a first-in-first-out memory (FIFO). 3. Transfer direction designation information (DIR) given under the control of the microprogram, activation information (IDMAEX) to the input/output device direct memory access control circuit (IDMACTL), and direct memory access mode control circuit (DMACTL)
) and the first-in-first-out memory (FIFO) are in the FULL state and E
When in MPTY state, each memory (FIFO)
A diagnostic section (
DIGC) and logic gate group (G20 to G23)
A read request (RREQ1) to the input/output device direct memory access control circuit (IDMACTL) from either
), direct memory access mode control circuit (DMA
CTL) read request (RREQ2), control circuit (I
3. The input/output control device according to claim 2, wherein the input/output control device sends either a write request (WREQ1) to the control circuit (DMACTL) or a write request to the control circuit (DMACTL). 4. Under the first mode, diagnosing that there is no fault in the first-in-first-out memory (FIFO);
3. Diagnosing that there is no fault in the input/output device (IO) under the second mode, and diagnosing that there is no fault in the microprocessor (μP) under the third mode. input/output controller.