JPS61267087A - Online verification system for image generator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to video display systems. More particularly, the present invention relates to a system for online verification of the functionality of various subsystems within a video display system.

[Conventional technology]

Traditionally, video display systems have been verified online by displaying test data and allowing a user to examine it. The user observes the test pattern and concludes that everything is working properly if the test pattern matches the expected display.

[Problem that the invention seeks to solve]

The above-described verification method is good when the user is trying to find something abnormal, but it has the disadvantage that the user has to think that there is something abnormal.

The present invention isolates the user from the loop of determining whether there is an error and allows the image generator to function properly online without user intervention and without affecting the information being displayed. Verify.

[Means for solving the problem] A system for online verification of an image generating device of a video display system that displays an image on a display screen by a scanning beam responsive to an information control signal on a position control signal is provided.
It consists of display memory, scanning logic, image generator, test register means and test comparison means.

The display memory has a display portion and a non-display portion.

The display portion is used to store display information to be displayed on the monitor, and the non-display portion is used to store test data.

The scanning logic provides position control signals to the monitor. The scanning logic also accesses the display memory at locations corresponding to the position of the scanning beam of the monitor.

An image generator generates display control information from display information stored in display memory. The image generator also provides information control signals to the monitor's scanning beam. Thereby, an image display corresponding to the display information is obtained.

Test register means is operatively connected to the image generator and stores test display control information generated from test data stored in a non-display portion of the display memory. The operation of this register is enabled by a control signal indicating the end of the display frame where the scan opening/sick occurs.

This control signal corresponds to the timing at which the test data is to be accessed by the scanning logic. The scanning logic is also active during the blank state of the monitor, during which time the monitor's scanning beam is located at the beginning of the display screen.

The test comparison means is operatively connected to the test register means and compares the test display control information loaded into the test register means with an expected result. This comparison is performed while the monitor is blank and allows for verification that the image generation device is functioning properly on-line and without affecting normal display operation.

〔Example〕

FIG. 1 shows an image generating device. The image generation device includes a graphics processor 10 and an image generator 11.

The example graphics processor 10 includes a Motorola 68000 microprocessor and a RAJII.

The image generator 11 includes a display memory 22, a pixel clock 24, a latch 26 and a shift register 30, a cursor display logic 18, a rask scan logic 20, a color lookup address generation logic 28, a color lookup memory 16, and a controller ζ-tactor. Includes 32ft.

The image generator 11 of the present invention further includes a loopback register 34 and a snapshot register 36 as test register means.

The loopback register 34 is used to write and read m data patterns by the graphics processor 10, and is connected to the graphics processor 10 and the image generator 11.
Enables verification of data between

Snapshot register 36 loads the 8-bit output or display control information generated by color lookup address generation logic 28 based on predetermined display information stored in display memory 22 by graphics processor IOK.

The display control information loaded into the snapshot register 36 is checked for correctness by a test comparison means within the graphics processor 10. This check makes it possible to verify various logic within the image generator 11.

These additional registers make it possible to test the image generator 11 while performing display operations on the ORT monitor, ie to verify it in online mode.

Display memory 22 is configured in two different types: alpha graphics memory 14 and pixel memory 12. Details of the configuration and operation of this display memory 22 will be described later.

The pixel clock 24 generates the clock signals required by the image generator 11.

The latch 26 and shift register 30 are operationally display memo 1.
722K connection, and is shifted in synchronization with the beam scanning of the ORT monitor by a clock signal from the pixel clock 24 in order to display the desired display.

Cursor display logic 18 generates a visible cursor that can be freely positioned on the display screen under control of graphics processor 10.

For details of cursor generation on a rask scanning type CRT monitor, please refer to Japanese Patent Application No. 59-167309 (U.S. Patent Application No. 52
No. 2,140) % Color Raster Graphics System Cursor Generation Method and Apparatus I.

Raster scan logic 20 generates all timing and synchronization signals for a raster scan CRT monitor (not shown) and all timing and control signals for accessing display memory 22. A counter in the raster scan logic 20 (not shown) is the raster scan fiOR
Which pixel on the T monitor display screen is being displayed?
and determine which location in display memory 22 is to be accessed.

The color lookup address generation logic 28 determines whether the currently displayed pixel is a pixel, alpha graphic, or cursor pixel based on the display priority, and uses this determination and an index (described later) to perform a color lookup. Generates an address for up memory 16.

Color lookup memory 16 stores color control information in locations corresponding to the color addresses provided by color lookup address generation logic 28. This color control information is used to control the brightness of the electron beam from the color electron gun of a color CRT monitor (not shown) and determines the color and brightness of each pixel on the display screen. Color control information is 8 bits. Color control information is read from the color lookup memory 16 and applied to the D/A converter 32 in synchronization with the scanning of each pixel on the display screen. The D/A converter 32 converts the 6 bits of color control information into an analog signal for controlling the brightness of the red, green, and blue electron guns of the ORT%2.

In the preferred embodiment, the remaining two bits of color control information are applied to a fourth D/A converter and converted to a black and white analog signal for use by a black and white hard copy device (not shown) for permanent recording. .

Details regarding the color lookup address generation logic 28 and the color lookup memory 16 can be found in Japanese Patent Application No. 5
8-500566 (U.S. Pat. No. 4,490,797)
A method and apparatus for controlling the display of a two-star computer-generated graphics system is described.

Before explaining the online verification of the present invention, the operation of each element of the image generator 11 will be explained.

FIG. 2 shows the configuration of the vixel memory 12.

Figure 3 shows the layout of the OR'l' monitor display screen.
- Show. The relationship between the display memory 22 and the display screen will be explained using FIGS. 2 and 3. (In FIG. 2, the pixel memory 12 will be described, but the same relationship applies to the alpha graphics memory 14.) In the embodiment of the present invention, the display screen of the ORT monitor has 640 horizontal pixels and 448 horizontal pixels.
Divided into vertical pixels.

The size of the character is 5 star pixels out of 8×10 pixels. The pixel memory 12 includes five memory planes PO
Each plane of pixel memory 14, including *P1*P2*P3 and P4, stores information for a pixel display. That is, planes O to 2 include color information, plane 3 includes brightness information, and plane 4 includes blink information.

Each memory plane is 64 words of memory eight pits wide. Each location in the memory plane stores 8 bit information for the corresponding 8 pixels. For example, location 0 of each plane of pixel memory 12 contains information about pixels o, o through 0.7 of the display screen.

The first bit in location 0 of pixel memory 12 contains information about pixel 0,0 of the display screen, and the second bit contains information about pixel 0.1 of the display screen. The same applies below.

In a rask-scan CRT monitor, scanning is generally from left to right and top to bottom. The scan starts at position 0.0 and moves horizontally across the display screen to position 0.639. The information read from the display memory 22 is CR
It must correspond to the scanning position of the T monitor. That is, first, pixel o.

The contents of location 0 of display memory 22 corresponding to 0 and 7 are read out. Next, from pixel 0°8 to 0,
Location 51 of display memory 22 corresponding to up to 15
The contents of 2 are read out. The process continues in the same way, pixel 0
．． The contents of location 40448 corresponding to 632 through 0 and 639 are read. The next line of the display screen (pixels 1,0 to 1,639) is then scanned and the corresponding information is stored in display memory 22 at locations 1,513,1025, . The contents of ...... are read out. When line 447 is completed, one screen display is completed and scanning begins again at line 0.

Locations 448 through 511 of display memory 22 are non-display portions. That is, it does not have a corresponding display screen. Similarly location 960 to 1023.147
2 to 1535. . . . is also a hidden part. Also, locations 40960 to 65 of the display memory 22
Even 535 (64K) is a non-display portion. These portions correspond to horizontal positions 640 to 1023 on the display screen. By providing the non-display portion of the display memory 22K in this way, it becomes easy to control the counter of the rask scanning logic. That is, when the OR'l' scanning beam is scanned along the horizontal line I/c, a 1 is placed at bit 9 of the address counter (i.e., the bit position representing 512).
By adding #) the correct address configuration is obtained corresponding to the CRT scanning beam. This facilitates addressing corresponding to the display layout, which has advantages that more than offset inefficient memory usage.

Regarding vertical scanning, although a simple scanning method has been described, other vertical scanning methods are well known. In the embodiment, interlaced scanning is used.

In interlaced scanning, the ninth counter that the rask scanning logic accesses in display memory 22 has its lowest bit position alternated between 1 and OK for each vertical scan. Interlaced scanning will be discussed later.

Alpha graphics memory 14 also accommodates a display screen of 640 horizontal pixels and 448 vertical pixels. al7
Graphical memory 14 consists of two memory planes. Each 8 bits of each memory plane corresponds to 8 horizontal pixels. The first memory plane is called dot memory, each bit of which specifies whether the pixel is a foreground or background color. The second memory plane is behavior memory.
The contents of each 8-bit location are defined by the attribute index (beha) of the corresponding dot memory location.
viorindex) and the display priority between pixel memory 12 and alpha graphics memory 14. The 8 bits of the attribute system consist of 6 bits of attribute index and 2 bits of display priority. Seven bits consisting of six pits representing the attribute index and one pit representing the foreground/background color from the dot memory are used as an index into the color lookup memory 16. The two bits representing display priority indicate the priority of pixel display over alpha graphic display. This priority takes one of three levels, as detailed in patent application no. 58-500566, cited above.

FIG. 4 shows the logic within the image generator 11.

The main logic for displaying information stored in display memory 22 is shown. Rask scan logic 2° reads the same locations in alpha graphics memory 14 and pixel memory 12.

In FIG. 4, location O is being read.

The 8 bits read from location O of dot memory 14' are loaded into shift register 26B, and the 8 bits read from location 0 of attribute memory 14'' are loaded into latch 26A. The contents of location O of each of the 12 memory planes are loaded into the shift register corresponding to each memory plane, i.e. location O of memory plane O.
The 8 bits read from shift register 8R-0
The 8 bits read from location 0 of memory plane 1 are pulled low to shift register 8R-1. The memory planes 2, 3.4 are similarly loaded into 5R-2, 5R-3, and 5R-4. Information regarding pixel 0,0 from pixel memory 12 and dot memory 14' loaded into these shift registers is shifted into color lookup address generation logic 28 for processing. This process is controlled by the information loaded into latch 26A, namely the attribute index and display priority. At this point, the CRT monitor's scanning beam is at position 0.0 on the display screen. It's in O. Then, in synchronization with the pixel clock signal, the scanning beam moves to the next position 0,
Move to 1. At the same time, information regarding pixel 0.1 from shift register 30.26 is shifted into color lookup address generation logic 28 and processed in response to the information contained in latches 26. In this way, the CRT
Scanning of the monitor continues until eight pixels of a horizontal line are displayed. The next pixel to be displayed is at position 0 on the display screen.
, 8 to 0, 15t. Rask scan logic 20
causes the contents of locations 512 in alpha graphics memory 14 and pixel memory 12 to be read into shift registers and latches. These operations continue until all lines are displayed. That is, the processing continues until all of the display portion of the display memory has been processed.

FIG. 5 shows a portion of the rask scan logic 200 functional block diagram. The rask scan logic 20 includes a frequency divider 42
, horizontal address counter 44, vertical address counter 4
6, an odd/even frame counter 48, two P-of-line detectors 50, and an end-of-frame detector 52.

Frequency divider 42 divides the pixel clock signal by eight.

Horizontal address counter 44, vertical address counter 46
and odd/even frame counter 48, display memory 22
The outputs of those counters constitute the display memory address. The output of odd/even frame counter 48 indicates the lowest bit of the display memory address. vertical ap
The 8-bit output of the response counter 46 constitutes the next lowest bit group. The 7-bit output of horizontal address counter 44 constitutes the highest bit group.

Pixel information is loaded from display memory 22 into shift registers and latches 26.30 eight pixels at a time. In order to count up the horizontal address counter 44 by that number, it is necessary to divide the pixel clock signal by eight.

The horizontal address counter 44 continues counting during the horizontal retrace period, and the count is used to generate a synchronization signal. In the exemplary embodiment, the horizontal retrace count for horizontal address counter 44 is 16, giving a total horizontal count of 96 for each horizontal line. End off when horizontal address counter 44 reaches the end of the current scan line. Line detector 50 is horizontal address counter 4
The end-of-line signal is fed back to 4.

At the same time, the horizontal address counter 44 is reset to -14. While the horizontal address counter 44 counts from -14 to Off, the display is blanked, but the image generator 11 continues to generate a horizontal synchronization signal to the CRT monitor (not shown). Further, the vertical address counter 46 is incremented by the end-of-line signal from the end-of-line detector 50.

In the embodiment, the image generator 11 uses an interlace method. That is, two frames of display constitute one screen. Frame 1 consists of all the even-numbered horizontal lines of the screen, and frame 2 consists of all the odd-numbered horizontal lines of the screen. Frames are alternately switched by an odd/even frame counter 48 for each vertical scan of the CRT monitor.

Vertical address counter 46 operates similarly to horizontal address counter 44, except that it is incremented at the end of each horizontal line. That is, when end-of-frame detector 52 detects that the display has reached the end of a frame, it generates an end-of-frame signal, vertical address counter 46 is reset to -16, and odd/even frame counter 48 is toggled. While the vertical address counter 46 counts from -16 to 0, the display is blanked, but the image generator 11 continues to generate the vertical synchronization signal to the ORT monitor.

The above is a description of the normal operation of the image generator 11.

FIG. 6 shows a block diagram of a portion of the image generator 11 to which an online verification function is added.

To perform on-line verification of the image generator 11, an end-of-frame signal is sent to the graphics processor 100 microprocessor as a vertical retrace interrupt signal.

In Figures 2 and 3, the odd 7th frame is completed when the scanning beam reaches the last position 447, 639 on the screen and a vertical retrace interrupt signal is generated. (For even frames,
446,639 is the last position. The horizontal address counter 44 and vertical address counter 46 continue counting during the retrace period so that the logic addresses location 449't- of display memory 22. This location 449 is located in a hidden part of the display memory 22, i.e. there is no corresponding real screen but the virtual location 449
49, corresponding to 449.7 from O. Test data is stored in advance in this location 449.

Returning to FIG. 6, the end-of-frame signal (i.e., the vertical retrace interrupt signal) is active for eight pixel clocks, and during the retrace period the open serial/parallel shift register 39 is addressed with location 449. operation.

Although the odd frame has been described above, the description is the same for even frames except that location 449e is replaced by location 448.

The address information on the data lines from the color lookup address generator 28 is an 8-bit address generated by the logic of the image generator 11 based on the test data stored in location 449 (or location 448 for even frames). address information. An interrupt routine within graphics processor 10 sets loop knock register 34 so that multiplexer 37 sequentially inputs this address information into serial/parallel shift register 39. Once shift register 39 is full, its data is read into graphics processor 10 and compared with the expected result. The test data stored in the display memory 22 is varied in various patterns by the graphics processor 10 so that all the logic of the image generator 11 is properly tested.

Since the color lookup memory 16 is R and AM, it can be changed by writing and reading.

The loop check register 34 is used to verify the data path from the graphics processor 10 to the image generator 11. This verification is possible not only in online mode but also in offline mode.

In this way, all the logic of the image generator 11 can be verified online from the input to the D/man converter 32. From shift register 39 to graphics processor 1
If the data read into 0 differs from the expected result, the verification is repeated until an error signal is generated or an equipment failure is identified. How to determine equipment failure is a matter of design choice.

In the preferred embodiment, it takes eight vertical frames to verify the test word address generated by color lookup address generator 28. Capturing the generated address in the manner described above is a design choice, but doing so can save hardware. In one embodiment, during the first vertical retrace interval, graphics processor 10 sets loopback register 34 to select bit O of the output of color lookup address generator 28 . As a result, the contents stored in the shift register 39 are bit 0 of the first pixel and bit 0 of the second pixel.
1... is bit O of the 8th pixel. The contents of this shift register 39, ie, bit O of the color lookup address for the first to eighth pixels, are read into the graphics processor 10. Bit 1 is read during the second vertical retrace interval. The process continues in the same manner until bit 7 is read during the eighth vertical retrace period. Therefore, eight vertical frames are required for the color lookup addresses for all eight pixels of the test word to be read into graphics processor 10 and verified.

Although an embodiment using a raster scanning type ORT monitor has been described above, the present invention can also be applied to other task scanning type monitors.

〔Effect of the invention〕

As is clear from the above description, the present invention provides an image generation device verification system having the following features.

(1) It is an online operation.

(2) Does not require human intervention.

(3) Does not affect normal display operations.

Although the embodiments of the present invention have been described above, it is clear that changes and modifications can be made without departing from the spirit and scope of the present invention. It is therefore intended that the appended claims cover such changes and modifications as fall within the true scope of this invention.

[Brief explanation of drawings]

FIG. 1 shows an image generating device. FIG. 2 shows the configuration of the pixel memory of the image generating device. FIG. 3 shows the layout of the display screen corresponding to the configuration of the pixel memory. FIG. 4 shows the portion of the image generator logic used to display information stored in the display memory. FIG. 5 shows a portion of a functional block diagram of the rask scanning logic of the image generator. FIG. 6 shows a block diagram of the parts added to the image generation device for on-line verification. lO...Graphic processor 11...Image generator 12...Vixel memory 14...Alpha graphics memory 16...Color lookup memory 18...Kanle display logic 20...Rask scan logic 22...・Display memory 24 ・Pixel clock 26 people ・Latch 26B ・Shift register 28 ・Color lookup address generator 30 ・・
- Shift register 32...D/A converter 34...Loop back register 36...Snapshot register 37...Multiplexer 39...Serial/parallel shift register 42...Frequency divider. 44...Horizontal address counter 46...Vertical address counter 48...Odd/even 7 frame counter 50...End of line detector 52...End of frame detector Patent applicant Honeywell Incorporated Agent Private patent attorney Yoshiharu Matsushita 8g2 Rg, 3

Claims (1)

[Claims] (1) In an image generation device of a video display system that displays an image on a display screen by a scanning beam responsive to a position control signal and an information control signal, a display memory, a scanning logic, an image generator, a test register means, and a test comparison are provided. The display memory consists of a display part and a non-display part,
The display portion is used to store display information to be displayed on the monitor, the non-display portion is used to store test data, and the scanning logic is used to store display information that is to be displayed on the monitor. accessing said display memory and providing a position control signal to a monitor; said image generator generating display control information from display information stored in said display memory and providing an information control signal to a scanning beam of said monitor; , the test register means is enabled by a control signal indicating the end of a display frame generated by the scanning logic, and loads test display control information generated from test data stored in a non-display portion of the display memory. , the test comparison means is operatively connected to the test register means and is configured to compare the test display control information loaded into the test register means during a blank period of the monitor with an expected result; 1. An online verification system for an image generation device, characterized in that online verification is performed to confirm that the image generation device is functioning normally, and when the comparison results do not match, it is indicated that there is an error.