JPS61266088A - Digital phase controller - Google Patents

Abstract

PURPOSE:To improve the function without increasing the cost by operating the standby mode of continuous video and voice recordings set by an arbitrary X-value shifting time with the same preset data. CONSTITUTION:The standby mode outputs of continuous video and voice recordings generated from a mode controller 16 by a mode input is input to a preset data generator 4 of a capstan phase comparing phase discriminator 2, which generates a preset value, and a capstan phase comparing counter 3 is preset by the output timing of a preset generator 7. Thus, the preset values of the counter 3 at the standby mode time of the countinous video and voice recordings are equal and commonly used.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital phase control device for phase-locking the phases of two motor systems, for example, a continuous recording operation of a magnetic recording/reproducing device (VTR) and This is used for the phase servo system in the synchronization mode (standby mode) of splicing and recording operations.

The basic operating modes of conventional VTR servo systems, such as recording, playback, continuous recording, and insert, are described in, for example, National Technical Report Vol. 28, P! 1L3P661-P576
1982. The continuous recording mode has already been divided into a standby mode (also called short play), which synchronizes the video signal on the magnetic tape with the video signal to be newly recorded, and a recording mode after phase synchronization. Through this series of operations, noise in the reproduced image due to synchronization disturbance at the joint in the reproduction operation mode of the video signal that has been spliced and recorded is removed.

In addition, continuous recording is a standby mode in which the FM-modulated audio signal that has already been recorded on the video track of the magnetic tape using a rotating head is synchronized with the audio signal to be newly recorded, and a phase synchronization mode. Separately from the subsequent recording mode, this series of operations removes noise in the reproduced audio due to synchronization disturbance at the joint in the reproduction operation mode of the audio signal recorded continuously.

The difference between the two is that in continuous recording, the reference signal for the cylinder phase comparison system is obtained from an external vertical synchronization signal (vsyc), whereas in continuous recording, the same reference signal is obtained internally in the cylinder phase comparison system. This is the point where it occurs. Since the present invention relates to the standby mode, the description will be limited to this mode and will proceed below.

FIG. 6 shows a timing chart of standby mode operation during continuous recording.

In standby mode during continuous recording, an external vertical synchronization signal (vs Y
At the input timing of C), the playback control signal (P B CT
In order to phase-synchronize the input timing of L), it is necessary to synchronize the cylinder servo system that controls the rotary head position with the external vertical synchronization signal (VSYC) and the capstan servo system that controls the transport of the magnetic tape. be.

Therefore, a configuration is adopted in which the capstan servo system phase comparison counter is preset to the initial value NPAN at, for example, the initial counting timing NHT of the cylinder servo system phase comparison counter.

FIG. 7 shows a timing chart of standby mode operation during continuous recording.

On the other hand, in standby mode during continuous recording, the external vertical synchronization signal (vsy) is used as the reference signal for the cylinder servo system.
Since there is no external reference signal input as in c), it is necessary to operate in an internal reference mode in which a reference signal is generated within the cylinder phase comparison system. At that time, (vsyc) is virtually set as the cylinder phase control system, designed in the same manner as continuous recording, and the capstan servo system phase comparison counter is preset to the initial value NP□22.

The details will be described later, but in the case of a device with the timing characteristics shown in Figures 6 and 7 without the so-called , NP, , = NP, 22, which can be supported if there is preset data for the capstan phase comparison counter that is common to the continuous recording mode and the continuous recording mode.

Problems to be Solved by the Invention However, in this case, during a series of operations of acceleration, constant speed, deceleration, and stop of the frame-by-frame feed shifter, the control of the tape running servo (capstan servo system) at constant speed is difficult. In order to improve performance, a special playback head was added and the phase of the control signal (PBCTL) was changed to an external vertical synchronization signal (v
In a system that has a so-called □ is the trapezoidal wave part of the capstan phase comparison signal (NL□ to N in Figure 6)
H, period), and phase lock may not be achieved or may be significantly disturbed.

SUMMARY OF THE INVENTION The present invention has been made to solve these problems, and it is an object of the present invention to provide a digital phase control device that has an X-value shift correction function and is capable of performing continuous recording and standby mode operation for continuous recording.

Means for Solving the Problems In order to solve the above problems, the present invention provides a pair of digital phase discriminators that obtains the deviation of the periods of two types of mutually synchronized input signals from a reference period as binary outputs. , the second digital phase discriminator for input signal deviation output is preset to the initial value MP at the initial count value preset timing of the first digital phase discriminator for input signal deviation output; Interpolate both HP1 and NP2 with respect to the two theoretical initial values NP, NP2 of the second phase discriminator corresponding to the case where the reference signal input is an external signal input and the internal reference signal input, respectively. This digital phase control device is characterized in that it is applied to the two external/internal reference input operation modes using only one arbitrary value NP1.

Function: With this device, continuous recording and standby mode of continuous recording, which are set at an arbitrary X value shift time, can be operated using the same preset data of the capstan phase comparison counter.

Embodiment FIG. 1 shows a timing chart of standby operation during continuous recording according to an embodiment of the present invention, and FIG. 2 shows a cylinder phase comparison counter during standby operation during continuous recording to explain this in detail. and a diagram showing the operating principle of the capstan phase comparison counter.

The operation of the cylinder phase comparison system will be explained. At the fall timing of the field synchronization external vertical synchronization signal (vSYc), the cylinder phase comparison counter is
L P/CR), reset, and the counter value becomes N.
At timing Y, the cylinder phase comparison counter preset signal (CYLP/CPR) is used to preset the counter to the count value NPa, and the external vertical synchronization signal (vs y c) falls one frame later. In this configuration, the count value of the counter becomes NFY/ at the timing, and the fall timing of the head switching signal (HSW) is determined by sampling the center NCT of the trapezoidal wave (NL, ~NH,) of the counter. υ, head switching signal (HS
The phase difference from the rising edge of W) to the falling edge of the external vertical synchronization signal (vsyc) is defined by the standard. τ(RXC) = 6H
A preset count value M P is determined. As a result, the cylinder phase comparison counter is activated by the external vertical synchronization signal (VS
YC) period 1/fv(syxc). In addition, in case the external vertical synchronization signal (VSYC) is lost, the cylinder phase comparison signal is
The internal buffer oscillates at a cycle of 1/fv' (syxc) between Y%NPY1. However, 1/fv (syxc)
<1/fv'(syxc).

Next, in the capstan phase comparison system, (CYLP/C;
PR) At the timing, preset the capstan phase comparison counter to count value NP, 1, and set the X value shift time Tx.
Sample the center count value NG□ of the trapezoidal wave (II, □ to NH□) using the playback control signal (PBCT L) at the timing defined by s (delay time from the rise of the head switching signal to the playback control signal). The initial count value NP, , is set.

Based on the above, cylinder phase comparison counter precent value N
PY, and capstan phase comparison counter preset value H
PA is obtained from the relationship of the following equation.

NPl ” NCY + NW + T (RXC
)' fOK(YP)Zcx(yp) / 2・fv(
syxc) −(1)NPmu,=Ncm+NW'fc
x (mu p) / fcx (yp) + τ (RIIC)',
? 'CtK(AP) ``Is'fCK(AP)...
(2) However, fc (YP) Clock frequency of Niji Linda phase comparison counter fc (□P): Clock frequency of capstan phase comparison counter τ (Rxc): From the rising timing of (H2N) (V SY C) Phase difference T until falling edge timing: X value shift time f, (≦Y[): Frame synchronization frequency NCY during recording
Phase lock count value NG of the Niji Linda phase comparison counter: Phase lock count value NW of the capstan phase comparison counter Internal preset generation timing count value of the Niji Linda phase comparison counter FIG. FIG. 4 is a diagram showing the operating principle of the cylinder phase comparison counter and the capstan phase comparison counter during the standby mode operation of continuous recording, which explains this in detail.

In continuous recording operation mode, external vertical synchronization signal (vs
Since yc) is not input, a virtual external vertical synchronization signal (vsyc) is assumed, and the cylinder phase comparison counter receives the preset signal (CYC) at the count value NFa timing.
LP/CPR) is generated internally, and the center NO of the trapezoidal wave (NLA~NH,) is the phase lock count value.
The configuration is such that P and 2 are preset. As a result, the cylinder phase comparison counter is: 1/fv(pm) = 1/fv(syNc)
The internal buffer oscillates.

The capstan phase comparison system outputs a reproduction control signal (P B
The configuration is such that an initial count value (preset value) NP,2 that can latch the phase lock count value NG, is determined by CT L).

Based on the above, in the same manner, the cylinder phase comparison counter preset value NPY□ and the capstan phase comparison counter preset value NP,2 are determined as shown in the following equations.

HPY□: N CY+ N FY-N FY/-(1
/2・fy(3y)la)−τ(Rm.))・f,
1,)...Drop) NPA2 = NCh + (f(nxc) -Txs
)・fcB*p)+(NFy N'y')・fc
x(ip)/fax(rp)...(4) However, NFY/: (VSYC) Cylinder phase comparison counter count value at input NF: Cylinder phase comparison counter count at internal preset signal generation timing The difference between the numbers (4) and (3) NP□2 and NP1 is N P
-MP,.

M2: (IF! -NF Dingt NW) to fa (
p)/fc becomes (YP)...(6).

From the internal buffer oscillation state when the external vertical synchronizing signal (VSYC) is missing, the external vertical synchronizing signal ("/5YC
) To reduce the pull-in time when inputting (6)
In the formula, N F - N FY/ N W =0! N P A 1 ””; N
P□2 can be selected. Therefore, instead of the theoretical preset value NP This can also be used in operation mode.

FIG. 5 shows a functional block diagram for realizing the present invention. The continuous recording standby mode output generated from the mode control circuit 16 upon mode input is input to the preset data generation circuit 4 of the capstan phase comparison phase discriminator 2, which generates a preset value NP1. , are preset to the capstan phase comparison counter 3 at the output timing of the preset generation circuit 7.

For comparison with the present invention, a configuration will be described in which there is no X value shift correction and the capstan phase comparison counter is preset at the timing of the count value NH of the cylinder phase comparison counter.

Figure 6 shows the standby mode operation timing chart during continuous recording without the X value shift function, and Figure 7 shows the
A timing chart of standby mode operation during continuous recording without a value shift function is shown.

The preset value NPY1+NPklj is determined from FIG.

NP! 1=NG, +NW+(τ(Rxc) 1/2
°fv(syNc))・f, 工(Y,)...(1) MPmu, 1 ==NOmu +(NHY-N0d) °
fax (mu p ) / f c x (ding p) - (τ (R
XG) 1/2°fv (syNc) ) (chip)
-fCIC (AP) / fY (SYNO)
``'(6) Obtain NPY2.NP, 22 from Fig. 7.

NP, =NG, +IFY-NFY/ -[1/2・fY
(syNc)−τ(nxc) ) °fct(yp)
−(3)NPh22=NOA+(NHY
”Y)・fax(ip)/fcxBp)+(1/
2°f (SYNG) - τ<nzc) )°fcBmuP
) fax(□P)/j'V(STNO) ・
...(A) As described above, NPAll ""122. According to the above configuration without X value correction, the preset values of the capstan phase comparison counter in the standby mode of continuous recording and continuous recording are equal and can be shared.

Effects of the Invention As described above, according to the present invention, the preset value of the capstan phase comparison counter for continuous recording with X-value shift correction and standby operation mode of continuous recording can be used as one count value that does not cause any practical problems. Additionally, since there is no increase in hardware, cost increases due to functional improvements can be eliminated.

[Brief explanation of drawings]

Figure 1 is a timing diagram of standby mode operation during continuous recording (with X value shift correction), Figure 2 is a diagram of the operating principle of the cylinder phase comparison counter and capstan phase comparison counter during standby operation during continuous recording, Figure 3 is a timing chart of standby mode operation during continuous recording, Figure 4 is a diagram of the operating principles of the cylinder phase comparison counter and capstan phase comparison counter during standby operation during continuous recording, and Figure 6 is a functional block diagram. The figure is a timing chart of standby mode operation during continuous recording, and FIG. 7 is a timing chart of standby mode operation during continuous recording. 1... Phase discriminator for cylinder phase comparison, 2...
...Phase discriminator for capstan phase comparison. Figure 2: S i δ area; Figure 4: Txj

Claims (1)

[Claims] a pair of first and second digital phase discriminators for obtaining the deviation of the periods of two mutually synchronized input signals with respect to the reference period as binary output; the digital phase discriminator for outputting the deviation of the first input signal; The digital phase discriminator for outputting the second input signal deviation is preset to the initial value NP at the initial count value preset timing of the device, and when the reference signal input to the first phase discriminator is an external signal input. and the two theoretical initial values NP_1, N of the second phase discriminator corresponding to the cases of internal reference signal input, respectively.
A digital phase control device characterized in that it is applied to the two external/internal reference input operation modes by using only one arbitrary value NP_F that interpolates both NP_1 and NP_2 with respect to P_2.