JPS61265632A - Data correcting circuit - Google Patents

Abstract

PURPOSE:To reduce the scale of a circuit by rotating an input data, executing a processing for correcting the extension of a code to an output data of a shifter, and executing a digit movement correction in case of a decimal point operation. CONSTITUTION:When a data for executing a processing of a digit movement correction is inputted to a data register 1, and the number of shifts is set to a shift control register 2, a shifter 6 rotates an input data by a portion of an optional number of bits. An output of the shifter 6 is inputted to a data selector 8, and by a value of a shifter control register 2, three values are outputted to a data output line 7. In case of a right arithmetic shift control, a bit which is positioned on the left from the number of shifts outputs a code bit SF of the data register 1. In case of a left arithmetic shift control, a bit which is positioned on the right from the number of shifts outputs a logical value '0'. Other bit is outputted as it remains an output value of the shifter 6.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a data correction circuit that performs digit shift correction in decimal point calculations.

Conventional technology FIG. 5 shows the configuration of a conventional data correction circuit.

11 is a data register that inputs and holds data for correcting digit shift; 12 is a data register that arithmetic shifts one word to the right and holds data for correcting digit shift;
2 is a shifter ill 10 register for inputting and holding the shift number; 31 is a left/right shift instruction signal indicating left or right shift; 32 is a shift amount instruction signal indicating the shift number; 4
5 is a selector that selects the contents of data register 11 or 12 based on left/right shift instruction signal 31; 5 is a decoder that performs shift control based on left/right shift instruction signal 31 and shift amount instruction signal 32; A shifter 7 performs a left shift according to control, and a data output line 7 outputs data corrected for digit shift by the shifter 6.

Conventionally, selected data has been shifted to the left by an amount determined by a left/right shift instruction signal 31 and a shift m instruction signal @32 to realize a shift operation in both left and right directions.
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Problems to be Solved by the Invention In conventional circuits, in order to prevent bit loss in the value to be corrected for digit shift, selection circuits must be provided for the number of bits to be shifted to the left. There is a problem that the circuit scale becomes large in the configuration to be handled.

An object of the present invention is to provide a data correction circuit that can perform digit shift correction even if the circuit scale is small.

Means for Solving the Problems The data correction circuit of the present invention includes a data latch that inputs and holds data for correcting digit shift, a shifter control register that holds the number of shifts in an arithmetic shift, and a data correction circuit that inputs and holds data for correcting digit shifts, a shifter control register that holds the number of shifts in an arithmetic shift, and a data correction circuit that inputs and holds data for correcting digit shifts. It is equipped with multiple bit shifters that rotate the input data, and a data selector that selects the sign of the input data, the output of the shifter, or a constant value according to the number of shifts, and rotates the input data by an arbitrary number of bits, and outputs the shifter according to the number of shifts. The present invention is characterized in that it is configured to perform digit shift correction in decimal point arithmetic by performing sign extension correction processing on the decimal point calculation.

Effect With this configuration, input data is rotated using a shifter that rotates an arbitrary number of bits, and digit shift correction in decimal point operations is performed by performing sign extension correction processing on the output data of the shifter. The digit shift correction process can be executed without providing selection ports and paths for the number of bits to be shifted in order to prevent bit loss.

Example The present invention will be explained below based on one embodiment.

FIG. 1 shows the configuration of a data correction circuit according to the present invention.

1 is a data register that inputs and holds data for correcting digit shift, 2 is a shift control register that inputs and holds the number of shifts, 3 is a shift control signal that controls the number of shifts, and 6 is for an arbitrary number of bits. 7 is a data output line that outputs the digit shift-corrected data; 8 is a data output line that performs code extension correction processing on the data rotated by an arbitrary number of bits by the shifter 6 in accordance with the shift control signal 3; It is a data selector.

The configuration of the shifter 6 is shown in FIG. 61 is a 2° pit shifter that selects a value obtained by rotating the output of data register 1 by 1 bit to the right or an original value that is not rotated by shift control signal 3, and 62 is a value obtained by rotating the output of data register 1 by 2 bits to the right or rotation. This is a 21-bit shifter in which the original value that is not selected is selected by the shift control signal 3, and n 2
' It is equipped with a bit shifter (+-o, 1...n-1), and is configured to rotate input data by an arbitrary number of bits.

The configuration of each bit of bit shifters 61 to 63 is shown in FIG. The configuration of the data selector 8 is shown in FIG.

In the configuration diagram of FIG. 4, 81 outputs the sign @SF of input data to data output 8Y when the corresponding bit position k is located to the left of the shift number indicated by shift control signal 3 during right arithmetic shift. The decoder LT0182, which generates a control signal for the shift, outputs a logical value ゛°0'' to the data output line YK when the corresponding bit position k is located to the right of the shift number indicated by the shift control signal 3. Decoder GTC183 that generates a control signal for output is connected to decoder LTC81 and decoder GTC during arithmetic shift.
This gate is used to control output of the shifter 6 to the data output line Y when the control signal 82 is not enabled.

The operation of the data correction circuit of this embodiment configured as described above will be explained below.

Data for performing digit shift correction processing is input into the data register 1, and the number of shifts is set in the shifter control register 2.

The 2° bit shifter 61 selects and outputs a value obtained by rotating the output of the data register 1 one bit to the right or the original value without rotation, depending on the value of the shifter control register 2. The 21-bit shifter 62 selects and outputs a value obtained by rotating the output of the 2° bit shifter 61 by 2 bits to the right or the original value without rotation, depending on the value of the shifter control register 2. 2I Bit shifter (+ -0, 1,..., n-1) is 2 bit shifter (+ -0, 1,..., n -1)
'-1 bits rotated to the right or the original value without rotation is selected and output. Said 2i Got Shifter (i
-0, 1, . . . , n-1), the value of data register 1 can be rotated by the maximum data bit length -1. The output of shifter 6 is data selector 8
and outputs three values to the data output line 7 according to the value of the shifter control register 2.

(2) In the case of right-handed shift control, the bit located to the left of the shift number outputs the sign bit SF of data register 1.

(2) In the case of left arithmetic shift control, the bit located to the right of the shift number outputs logic w10.

(2) Bits other than (2) and (2) output the output value of the shifter 6 as is.

As described in the detailed description of the invention, the data correction circuit of the present invention includes a shifter that rotates the data for digit shift correction by an arbitrary number of bits, and a data selector that performs sign extension correction. This has the effect of being able to perform a small-scale, arbitrary bit shift.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of an embodiment of the data correction circuit of the present invention;
2 is a block diagram of the shifter 6 in FIG. 1, FIG. 3 is a block diagram of the selection circuit of the dot shifter in FIG. 2, FIG. 4 is a block diagram of the data selector 8 in FIG. 1, and FIG. FIG. 2 is a configuration diagram of a conventional data correction circuit. 1... Data register, 2... Shifter control register, 3... Shift control signal, 4... Selector, 5...
・Decode, 6...Shifter, 7...Data output line,
8...Data selector

Claims (1)

[Claims] 1. A data latch that inputs and holds data for correcting digit shifts, a shifter control register that holds the number of shifts for arithmetic shifts, multiple bit shifters that rotate arbitrary number of bits, and input according to the number of shifts. Equipped with a data selector that selects the sign of the data, the output of the shifter, or a constant value, rotates the input data by an arbitrary number of bits, performs sign extension correction processing on the output of the shifter according to the number of shifts, and digits in decimal point operations. A data correction circuit configured to perform movement correction.