JPS61264986A - Agc buffer circuit for catv converter - Google Patents

Abstract

PURPOSE:To accomplish the simplification and integration of the circuitry by shifting, a part of the video signal when a scramble video signal is being inputted so that the video signal can be processed only with a peak AGC. CONSTITUTION:When the input signal is a normal video signal, a switching circuit 2 lets it inputted to a peak AGC circuit 6, but if it is a scramble video signal, it is inputted to a video shift circuit 3. In the circuit 3, the burst period is shifted using a sampling pulse generated by a sampling pulse generator 4, then the signal is inputted to the circuit 6. The circuit 6 applies the peak AGC using the reference level set by a reference level generating part 5 without discriminating the normal video signal with the scramble video signal. Thus the scramble video signal is made subjected to peak AGC by an AGC buffer circuit equally with the normal video signal.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an AGC buffer circuit for an ATV converter having a scrambling function using a synchronization signal level shift technique.

Prior Art FIG. 4 shows a conventional example, and shows the circuit configuration required up to the application of AGC.

In FIG. 4, the video signal input through the input terminal 1 is input to the AGC circuit 18 as is. In the case of a normal video signal, a peak AGC reference level generation circuit 12 generates a reference level for applying peak AGC, and in the case of a scrambled video signal, a keyed AGC17 reference level generation circuit 13 generates a reference level for applying keyed AGC. The reference levels are respectively switched by a switching circuit 16 and inputted to an AGC circuit 18.

Similarly, in the case of a normal video signal, the hold voltage of the peak hold circuit 14 composed of a capacitor etc. is
The keyed pulse from 6 is input to the AGC circuit by a switching circuit 17.

Problems to be Solved by the Invention However, in the above configuration, the normal video signal is subjected to peak AGC, and the scrambled video signal is subjected to keyed AG.
It is necessary to have two circuits, one for setting the reference level for each, a switching circuit for peak hold and keyed pulse, etc., which makes the overall circuit complicated and requires the use of volume capacitors, etc. Therefore, it has a problem that it is not suitable for integration.

In view of the above problems, the present invention provides an AGC buffer circuit that can process a normal video signal and a scrambled video signal using one type of AGC and is suitable for integration.

Means for Solving the Problems To achieve this object, the AGC buffer circuit of the present invention is configured to shift a part of the video signal when a scrambled video signal is input.

Function: This configuration allows video signals to be processed only by peak AGC, which is advantageous for circuit simplification and integration.

Embodiment Hereinafter, an AGC buffer circuit according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a block diagram of this embodiment.

In FIG. 1, a video signal is input from an input terminal 1. Reference numeral 2 denotes a switching circuit for switching between a normal video signal and a scrambled signal; if the input signal is a normal video signal, it is inputted as is to the peak AGC circuit 6, and if it is a scrambled video signal, it is inputted to the video shift circuit 3. In the video shift circuit 3, the burst period is shifted by the sampling pulse generator 4 and inputted to the peak AGC circuit 6. The peak AGC circuit 6 performs peak AGC using the reference level set by the reference level generator 6, regardless of whether the signal is a normal video signal or a scrambled video signal.

In this way, the AGC buffer circuit of this embodiment allows peak AGC to be applied to the scrambled video signal or the normal video signal in the same way.

Regarding the AGC buffer circuit configured as above,
The operation will be explained below.

First, FIG. 2 shows a specific circuit diagram of the block diagram shown in FIG. 1.

First, if the video signal input from the base of transistor Q, which is input terminal 1, is a normal video signal, the sampling pulse at the base of transistor Q7 is oV, but 6V is input to the base of transistor Q8, so transistor Q8 is turned on. to lower the base potential of transistor Q6. Therefore, 1 of the signal at the base input of transistor Q1
A signal that has been DC shifted by one diode is output from the AGC video signal output terminal 10 (EOoUT from AGC).

If the next input video signal is a scrambled video signal,
First, a video signal shown in FIG. 3 is input to the base of the transistor Q1. Also, on the transistor Q7 base,
A sampling pulse synchronized with the burst period is input. As a result, the transistor Q4 turns on (ON) L, and a voltage drop occurs due to the constant current flowing through the resistor R6 and the resistor R4.

Of course, since the burst is set to be dropped at the time of input, the burst will not be added to the shifted signal. The video signal at this time is shown in FIG. 3b.

Furthermore, when no sampling pulse is input, transistor Q7 is off (OFF), and since a scrambled video signal is being input, transistor Q8 is also off. Therefore, the pace potential of transistor Q6 becomes higher than the pace potential of transistor Q1, and during this period, AGC A constant voltage is output from the video signal output terminal 10. Therefore, the scrambled video signal becomes the signal shown in C in FIG. 3 and is output. The AGC circuit detects this shifted portion and applies peak AGC to the scrambled video signal.

As described above, according to this embodiment, it is possible to reduce the number of peripheral circuits of the AGC circuit and reduce costs through integration.

Effects of the Invention As described above, the present invention combines the conventionally divided ACiC system into one by applying peak AGC to the scrambled video signal whose synchronization signal level has been shifted by the AGC buffer circuit in the same way as the normal video signal. It also has great practical effects in terms of integration.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a circuit diagram showing the specific configuration of Fig. 1, Fig. 3 is a waveform diagram of a video signal showing the same operation, and Fig. 4 is a conventional This is an example pro diagram. 1...Input terminal, 2...Switching circuit, 3
・・・・・・Video shift circuit. 4...Sampling pulse generator, 5...Reference level generation section, e...Peak AGC circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2

Claims (2)

[Claims] (1) A CATV converter configured to perform signal processing to apply the same peak AGC as a normal video signal to a video signal that has been subjected to synchronization signal level shift or video polarity inversion processing using a video scrambling method. AGC buffer circuit for (2) The AGC buffer circuit for a CATV converter according to claim 1, wherein the signal processing shifts the burst period of the scrambled video signal to the same level as the leading value of the synchronization signal of the normal video signal.