JPS61264738A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve the integration by forming an insulating layer having contacting holes on the first conductive layer, forming the second conductive layers on inner surface of the hole and the insulating layer, and burying a block material in the hole thereon to raise the wiring density without improper wirings or decrease in the reliability. CONSTITUTION:An insulating layer 3 is formed on a semiconductor substrate 1, and a contacting hole 4 is opened at the prescribed position on an impurity region 2. A wiring layer 51 made, for example, of an aluminum layer is formed on the inner surface of the hole 4 and the layer 3. At this time, the width of the layer 51 formed on the layer 3 is equal to that of the hole 4. A block material 61 is buried in the hole on the layer 51. Since the layer 51 and the region 2 are thus connected on the entire bottom surface of the hole 4, even if the layer 51 has the width equal to that of the hole 4 without marginal width of the displacement from the hole 4, no danger of improper disconnection of wirings occurs.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to a semiconductor device and a method for manufacturing the same.

[Technical background of the invention and its problems]

Generally, when two conductive layers, for example, an impurity region formed on the surface of a semiconductor substrate and an AtJ layer, are connected through a contact hole, a contact hole 4 is opened above the impurity region 2 as shown in FIG. A wiring layer 51 having a margin width 1 equal to the width C of the contact hole 4 is formed over the contact hole 4 .

This margin width 1 is usually arranged by lithography to match the contact hole 4! This is provided in consideration of misalignment when forming the WJ51 pattern.

Therefore, the width of the wiring layer 51 is C+2 around the contact.
J, which is usually larger than the width outside the periphery of the contact. As a result, when other wiring layers 52 and 53 are formed adjacent to the wiring layer 51, the wiring density is lower around the contact than in areas other than the periphery. Therefore, if the wiring layer 51 has a margin p around the contact hole 4, the density of the wiring layer in the semiconductor device will be reduced, and this will hinder the improvement of the degree of integration of the semiconductor device.

In order to solve the above problem, if the wiring layer 51 is formed without taking the margin width 1 in the conventional semiconductor device, as shown in FIG.
．． 53 becomes a space S, and the density of the wiring layer is improved.

However, in this case, if misalignment occurs between the contact hole 4 and the pattern of the wiring Wa 51, as often occurs in the process of normal adhesive processing, the pattern of the wiring layer 51, 52, 53 will be formed according to the pattern shown in FIG. When the wiring layer other than the portions covered by the resists 71, 72, 73 is etched away, the impurity region 2 at the bottom of the contact hole 4 is also etched, and there is a risk that the impurity region 2 may be destroyed. Further, in this case, since the wiring layer 51 does not completely cover the bottom surface of the contact hole 4,
There is a problem in that the current density in the wiring layer 51 on the bottom surface increases, and resistance increases or disconnection defects are likely to occur due to electromigration.

[Purpose of the invention]

The present invention has been made in consideration of the above circumstances, and it is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which can increase the wiring density and improve the degree of integration without causing wiring defects or deteriorating reliability.

[Summary of the invention]

In order to achieve the above object, a semiconductor device according to the present invention includes a first conductive layer, an insulating layer having a contact hole formed on the first conductive If layer, and an inner surface of the contact hole and the insulating layer. and a block material embedded in the contact hole on the second conductive layer.

Further, the method for manufacturing a semiconductor device according to the present invention includes a first step of forming an insulating layer on the first conductive layer, a second step of forming a contact hole in the insulating layer, and a second step of forming a contact hole on the entire surface. a third step of forming a conductive layer; a fourth step of filling the contact hole on the second conductive layer with a block material; and forming the second 13-conductor layer formed on the insulating layer. A fifth step of forming a predetermined pattern.

As a result, the second conductive layer completely covers the bottom surface of the contact hole, and there is no need for the second conductive layer to have an allowance for misalignment with the contact hole.

[Embodiments of the invention]

A plan view and a cross section of a semiconductor device according to an embodiment of the present invention are shown in FIGS. 1(a) and 1(b).

An impurity region 2 is formed on the surface of a semiconductor substrate 1 . Further, an insulating layer 3 is formed on the semiconductor substrate 1, and an impurity region 2 is formed on the semiconductor substrate 1.
A contact hole 4 is provided at a predetermined location on the top.

It is opened. A wiring layer 51 made of, for example, AfJm is formed on the inner surface of this contact hole 4 and on the insulating layer 3. At this time, the wiring layer 5 formed on the insulation 113
The width of contact hole 4 is equal to the width of contact hole 4 . And wiring layer 5
A block material 61 is embedded in the contact hole on the top.

As described above, according to this embodiment, since the wiring layer 51 and the impurity region 2 are connected to each other on the entire surface of the contact hole 4, the wiring layer 51 has a margin width that takes into account misalignment with the contact hole 4. Even if the width is set equal to the width of the contact hole 4 without holding the contact hole 4, there is no risk of disconnection or the like.

In this embodiment, an example is taken of a wiring [51] consisting of an impurity region 2 on the surface of a semiconductor substrate 1 as a first conductive layer and Ajll as a second conductive layer, but the present invention is not limited to this example. This is true when two conductive layers, such as a surface impurity region and a polycrystalline silicon layer, a polycrystalline silicon layer and a polycrystalline silicon layer, a polycrystalline silicon layer and an All 125 layer, or an Aj layer and an AfJ layer, are connected through a contact hole. The invention can be applied.

Furthermore, although the block material 61 in this embodiment may be removed, it is more convenient to leave it as long as it does not adversely affect the semiconductor device because the contact portion is flattened.

FIG. 2 shows a plan view of a semiconductor device according to another embodiment of the present invention. In the above embodiment, the width of the wiring layer 51 is assumed to be equal to the width of the contact hole 4, and the margin width that takes into account misalignment with the contact hole 4 is set to zero, but in this embodiment, the width of the wiring layer 51 is equal to the width of the contact hole 4. The width of ff51 is smaller than the width of contact hole 4.

As described above, according to this embodiment, even when the contact hole 4 is wide and has a large area, the width of the wiring layer 51 can be made smaller than the width of the contact hole 4, thereby making it possible to 52.degree. and 53. The minimum necessary space S can be taken respectively.

Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIG. Impurities are added to the surface of semiconductor substrate 1 to form impurity region 2 .

Further, an insulating layer 3 is formed on the semiconductor substrate 1, and an impurity region 2 is formed on the semiconductor substrate 1.
A contact hole 4 is opened at a predetermined location on the top. A all over
The I layer 50 is deposited, and then a negative resist 60 is applied to flatten its surface (FIG. 3(a)). This negative resist 60 is subjected to RIE (Rea-active Ion)
The negative resist 61 is removed by etching using etching method (Etchino et al.), leaving the negative resist 61 only in the contact hole 4. Then, this negative resist 61 is exposed to light ((Fig. 3(b)
)). Resist is again applied to the entire surface, and resists 71, 72, . . . corresponding to the patterns of the wiring layer are formed by lithography.
73 will remain. Using the resists 71, 72, 73 and the negative resist 61 in the contact hole 4 as block materials, the A1 layer is patterned into a wiring 11151 by etching. At this time, the width of the wiring layer 51 is equal to the width of the contact hole 4.
The width of the negative resist 6 is set equal to the width of the negative resist 6.
1, the wiring layer 51 in the contact hole 4 is not etched away (FIG. 3(C)). Next, the resists 71, 72 and 73 are removed (FIG. 3(d)).

As described above, according to this embodiment, even if the pattern of the wiring 1lI51 is misaligned with the contact hole 4, the wiring layer 51 and the impurity region 2 are connected over the entire bottom surface of the contact hole 4, so that the wiring layer 51 contact hole 4 without having a margin that takes into account misalignment with contact hole 4.
It can take a width that does not exceed the width of .

In this embodiment, the impurity region 2 on the surface of the semiconductor substrate 1 is used as the first conductive layer, and the wiring layer made of ARm is used as the second conductive layer. and polycrystalline silicon layer, polycrystalline silicon layer and polycrystalline silicon layer, polycrystalline silicon layer and Ajll
! , AjJI and Al1 layers, the present invention can be applied when two conductive layers are connected through a contact hole.

Further, in this embodiment, a photosensitive negative resist 61 was used as a blocking material to prevent the wiring layer 51 inside the contact hole 4 from being removed by etching. secondly, it must be resistant to the developer of the resist 71,72,73, and thirdly, it must be resistant to etching of the second conductive layer and act as a blocking material. Any material is fine as long as it is available. For example, a resin material such as polyimide resin or a glass material such as spin cord glass can be used. Further, this block material does not need to be removed as long as it does not adversely affect the semiconductor device, and on the contrary, the contact portion is flattened, which is convenient.

Furthermore, in this embodiment, RIE was used to remove the negative resist 60 by etching and leave the negative resist 61 only in the contact hole 4, but this was
chemical dry etching), but W
E (Wet Etchina) may be used, and in short, any etching method may be used as long as the etching progresses uniformly from the flattened surface and only the inside of the contact hole is left unetched.

〔Effect of the invention〕

As described above, according to the present invention, wiring density can be improved without causing wiring defects or deterioration of reliability, and it can contribute to improving the degree of integration of semiconductor devices.

[Brief explanation of the drawing]

1(a) and 1(b) are a plan view and a sectional view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a plan view of a semiconductor device according to another embodiment of the present invention, and FIG. FIG. 4 is a process diagram showing a method for manufacturing a semiconductor device according to an embodiment of the invention;
FIGS. 5 and 6 are diagrams showing conventional semiconductor devices. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Impurity region, 3... Insulating layer, 4... Contact hole, 50.51.52.53
... Wiring layer, 60.61.71, 72.73... Resist. Applicant's agent Kiyoshi Inomata Figure 3

Claims (1)

[Claims] 1. A first conductive layer, an insulating layer having a contact hole formed on the first conductive layer, and a second conductive layer formed on the inner surface of the contact hole and on the insulating layer. A semiconductor device comprising: a conductive layer; and a block material embedded in the contact hole on the second conductive layer. 2. A first step of forming an insulating layer on the first conductive layer, a second step of opening a contact hole in the insulating layer, and a third step of forming a second conductive layer on the entire surface. , said second
a fourth step of filling the contact hole on the conductive layer with a block material; and a fifth step of forming the second conductive layer formed on the insulating layer into a predetermined pattern. A method for manufacturing a semiconductor device, characterized in that: