JPS61263264A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve the electrostatic withstand voltage by forming the same conductive type region as a semiconductor region for forming an input protecting circuit at the side near the input protecting circuit in a scribing region, thereby preventing the function of the protecting circuit from damaging. CONSTITUTION:An N<+> type diffused layer 34b and an input protecting circuit made of a clamping MOS transistor 37 is formed on a P-type silicon substrate 31, and connected with a pad 38. An N<+> type diffused layer 36 is formed as the second diffused layer to surround an inner circuit which contains the input protecting circuit in a scribing region 43. When an excess voltage is applied to the pad 38 to cause a surge current to flow, the implanted charge flows to the substrate 31 side, also flows to the diffused layer 36 through the substrate 31 from the layer 34 to be diffused. As a result, it can prevent the function of the transistor 37 from damaging to protect the inner circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device, and particularly to a semiconductor device with improved electrostatic withstand voltage.

[Background technology]

In a semiconductor device, an input protection circuit (electrostatic protection circuit) as shown in FIG. 4 is provided to protect internal circuits from electrostatic damage. In the figure, 1 is a pad, and this pad 1 is connected to the internal circuit via a resistor 2 (made of polycrystalline silicon or a diffusion layer), and a clamp MO8.
) A transistor 3 is connected to the connection point 4.

The present inventor constructed the circuit shown in FIG. 4 by using a complementary MO8FET (
A case where the present invention was applied to a semiconductor device equipped with a CMO8 (hereinafter referred to as CMO8) was investigated. As a result, we found the following problem.

FIG. 5 shows an example of a semiconductor device studied by the present inventor.

In FIG. 5, 11 is a P-type silicon substrate, 13 is a field oxide film (810m film), 14 is an N+ type semiconductor region, and the horizontally extending portions 1 and 4a are resistors 2
used as Clamp MO8) Transistor 3 is N”
It has W drain and source regions 14. 1 is an AA bad. The P+ type semiconductor region 17 is formed at the same time as forming the source and drain regions of the P-channel transistor (O8) of the CMOS device. P+ layer 17 is A
It is fixed at the substrate potential by the A electrode 18. P layer 17
is formed to surround the internal circuit, and serves to fix the substrate surface around the internal circuit to the substrate potential. Furthermore, contaminants (eg, alkali metals, etc.) that have entered the interior through the scribed cut surface are gettered by the P+ layer 17. 20 is phosphorus silicate glass CPSG) film,
21 is a scribe area, and this scribe area 2
1 is a field oxide film 13 that partitions the outer periphery of the internal circuit.
This refers to the substrate area outside of a for scribing.

In the semiconductor device configured in this manner, even if an overvoltage is applied from the pad 16, the current normally flows to the substrate side through 49 routes and the internal circuit 5 is protected by providing the electrostatic protection circuit.

However, according to further study by the present inventors, for example, when a steep overvoltage (surge voltage) is applied to the pad 16, the overcurrent may destroy the junction at the PN layer interface 22.

Therefore, clamp MO8) transistor 15 does not function (
As a result, the drain potential becomes the same as the substrate potential, making it impossible to control the gate voltage of the internal circuit 5.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device with improved electrostatic withstand voltage and thereby improved reliability.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, a second semiconductor region of the same conductivity type as the semiconductor region constituting this is formed on a small side of the scribe area (both near the input protection circuit).As a result, when an overcurrent is applied to the input protection circuit, In addition to the input protection circuit, current can also flow to the second semiconductor region in the scribe area, which prevents functional breakdown of the input protection circuit and improves the electrostatic withstand voltage, thereby increasing reliability. This is intended to improve the quality of life.

[Embodiment 1] FIG. 1 shows a first embodiment of a semiconductor device according to the present invention, and particularly shows a case in which a CMOS dynamometer RAM is configured as an internal circuit 5 via a gate circuit.

In the figure, 31 is a P-type silicon substrate, 33 is a field oxide film (SiOx film), and 34 to 36 are N+ type semiconductor regions (hereinafter referred to as N+ diffusion layers), and these N+ layers 34 to 36 are used for CMOS devices. N channel MO8)
Ranjistha source.

It is formed at the same time as forming the drain region.

Of the N+ diffusion layer 34 as the first diffusion layer, an N+ diffusion layer portion 34b extending laterally from the N+ diffusion layer portion 34a in the drain region is used as a resistor and corresponds to the resistor 2 in FIG. 4. 37 is an N+ diffusion layer portion 34a serving as a drain and source region.

Clamp MO8) transistor with N+ diffusion layer 35, using a polycrystalline silicon gate as the gate. Here, the N+ diffusion layer portion 34b and the clamp MOS transistor 37 constitute an input protection circuit as shown in FIG. The N+ diffusion layer 36 as a second diffusion layer is formed so as to surround the internal circuit (including the input protection circuit connected to the pad 38) as shown in FIG. 3(a). This P+ diffusion layer 39 is a P+ type semiconductor region (P+ diffusion layer), and this P+ diffusion layer 39 is a P+ type semiconductor region (P+ diffusion layer).
It is formed at the same time as forming the P+ diffusion layers of the source and drain regions of the Jannel MOS transistor. A! 40 is formed across the surfaces of the N+ diffusion layer 36 and the P+ layer 39. il electrode, to which a substrate potential is applied. The P+ layer 39 and the A chisel electrode 40 are also formed to surround the internal circuits, and there is no voltage drop due to the PP+ junction, and the surface of the P+ layer 39 is also maintained at the substrate potential (for example, -3V in the case of a dynamic RAM). Therefore, the surface of the outer periphery of the internal circuit 5'' is fixed at the substrate potential.This has the effect of suppressing the substrate effect described above, suppressing the noise of the diffusion layer, and reducing parasitic capacitance.Furthermore, by forming the contact hole 41, , the contaminants that have entered the inside through the thin 5iQ1 film (not shown) on the surface of the silicon substrate 31 from the bullet separation point of the scribe portion are blocked as described above. 42 is the PSG film, 43 is the scribe area,
That is, the field oxide film 33a defines the outer periphery of the internal circuit.
This is the outside of the substrate and is the substrate area for scribing.

With this configuration, even if an overvoltage is applied to the pad 38, the current normally flows to the silicon substrate 31 side through 42 routes, and the internal circuit 5 is protected. Furthermore, even if a steep overvoltage is applied and an excessive current (surge current) flows in, of the injected charge Q, the charge ΔQ is transferred to the N+ diffusion layer 34 - P type silicon substrate 31 - N+
Flows into the diffusion layer 36, and the remaining charge Q-ΔQ is 4 as before.
It flows to the silicon substrate 31 side through one route.

Even if an excessive current flows in this way, by increasing the number of excessive current buses and dispersing the excessive current, the current flowing to the input protection circuit can be reduced, and the PN layer interface 44
Therefore, the clamp MO
The function of the S transistor 37 is not destroyed, and the internal circuit is also protected.

As described above, by providing the N+ diffusion layer 36 as a second diffusion layer adjacent to the field oxide film 33a on the side closest to the internal circuit in the scribe region 43, the pad 3
Even if an excessive current flows into the capacitor 8, by diverting the current to the N+ diffusion layer 36 in the scribe region, the electrostatic withstand voltage can be improved, and the reliability can be improved.

[Embodiment 2] FIG. 2 shows a second embodiment of the semiconductor device according to the present invention, and particularly shows a case where a CMOS dynamic RAM is configured as the internal circuit 5 via a gate circuit.

In this figure, the difference from FIG. 1 is that the n+ diffusion layer resistance (n+ diffusion layer portion 34b) of the electrostatic protection circuit (input protection circuit)
) instead of polycrystalline silicon layer resistance (polycrystalline silicon layer 4
5), the diffusion layer 3 in the drain region of the clamp MOS transistor 37 out of the N+ diffusion layer 34
4a and the connection part between the pad 38 and the silicon substrate 31.
Only the diffusion layer 34c (first diffusion layer) is formed, the N+ diffusion layer resistance portion 34b is replaced by a polycrystalline silicon layer 45 formed on the field oxide film 33b, and one end of this polycrystalline silicon layer 45 is connected to A! Connect to pad 38 and connect the other end to A.
! This is because it is connected to the drain electrode of the clamp MOS transistor 37 via the wiring 46. Note that the internal circuit is an input protection circuit (consisting of a polycrystalline silicon layer 45 and a clamp MOS transistor 37) connected to the pad 38.
shall be included.

As in the case of the first embodiment (Fig. 1) described above, even if, for example, a steep overcurrent (surge current) flows in, the charge of ΔQ of the injected charge Q is transferred to the N+ diffusion layer 34 cm P-type silicon substrate. 31-N+ flows to the diffusion layer 36 and the remaining charge Q
-ΔQ is polycrystalline silicon layer 45, An wiring 46. Clamp MO8) Even if an excessive current flows into the silicon substrate 31 side through the N+ diffusion layer 34a in the drain region of the transistor 37 from the pad 38, the input is protected by dispersing (shunting) the excessive current. The current flowing through the circuit can be reduced, the junction of the PN+ layer interface 44 can be prevented from being destroyed, and the function of the clamp MOS transistor 370 can therefore be prevented from being destroyed.

Compared to the conventional art, by providing the N+ diffusion layer 36 in the scribe region, it is possible to improve the electrostatic breakdown voltage and improve the reliability.

〔effect〕

(1) Even if an excessive voltage is applied and an overcurrent flows from the pad part, the overcurrent is shunted (dispersed) from the first diffusion layer through the semiconductor substrate to the second diffusion layer in the scribe region. Therefore, the electrostatic withstand voltage can be improved compared to the conventional method.

(2) Reliability can be improved compared to (1).

Although the invention made by the present inventor has been specifically explained based on examples, the present invention is not limited to the above-mentioned examples (and various changes can be made without departing from the gist of the invention). Needless to say, for example, Figure 1,
In the embodiment shown in FIG. 2, the N+ diffusion layer 36 is
As shown in FIG. 3(a), the N+ diffusion layer 36 is placed around the entire periphery of the internal circuit 5, but as shown in FIGS. 3(b) and 3(c), the N+ diffusion layer 36 is placed only near the pad 38 in the scribe area. may be set.

[Application field]

The above explanation will mainly focus on the CMOS memory (C
MOS dynamic RAM-PC'MOS static R
We explained the case where AM) is applied to the internal circuit, but
(For example, MOS devices in general such as CMOS logic circuits and N-channel MOS devices can be applied to the internal circuit. In the case of a CMOS logic circuit, for example, the internal circuit 5 as shown in FIG. 3(d) A second diffusion layer of conductivity type opposite to that of the semiconductor substrate (
As shown in the figure, an n+ diffusion layer 36) may be integrally provided on the P-type silicon substrate 31.

[Brief explanation of drawings]

1 and 2 are diagrams showing a simplified main part layout of a semiconductor device according to the present invention, FIG. 4 is a circuit diagram showing an example of an input protection circuit, and FIG. 5 is a simplified diagram showing an example of a conventional semiconductor device. FIG. 34.34cmN+diffusion layer (first diffusion layer), 36...
・N+ diffusion layer (second diffusion layer), 38...pad, 4
3...Scribe area. 3 (d)

Claims (1)

[Claims] 1. An internal circuit having an input protection circuit on a semiconductor substrate;
In a semiconductor device in which a pad portion connected to the input protection circuit and arranged around the internal circuit is formed, at least the side closest to the internal circuit in the scribe region has a conductivity opposite to that of the semiconductor substrate. 1. A semiconductor device comprising: a second diffusion layer having the same conductivity type as the first diffusion layer to which the pad portion is connected; 2. The semiconductor device according to claim 1, wherein the second diffusion layer is formed all around the internal circuit in the scribe region. 3. The semiconductor device according to claim 1, wherein the second diffusion layer is formed only in the vicinity of the pad portion in the scribe region.