JPH0613563A - Static electricity protective device - Google Patents

Abstract

PURPOSE:To protect an internal circuit against a high voltage, a large current by increasing a length of a part to be disposed oppositely to a contact hole group for connecting a drain of a MOS transistor to input/output terminals and a contact hole group for connecting an impurity region of an outer periphery to a power source terminal to a special value or more. CONSTITUTION:When high voltage noise is applied between a power source VDD and a signal input terminal, a current flows through a route between contact hole groups on an N-type drain region 4 in order to remove it. A length of a part in which the group on the region 4 and a contact hole group on an N-type impurity region 7 are opposed is about 200mum. Thus, routes in which current flows in order to erase noise to a power source VDD are increased, and static electricity breakdown voltage at the time of applying noise to the power source VDD is raised.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for protecting an internal circuit connected to a signal input terminal or a signal output terminal in a complementary MOS semiconductor device against static electricity.

[0002]

2. Description of the Related Art FIG. 4 is a circuit diagram showing an example of an electrostatic protection device for an input circuit. In FIG. 4, a gate control diode 10 for connecting the signal input pad 2 and the power supply VSS, and the power supply VSS, the signal input pad 2, and the power supply VD.
Diodes 11 and 12 connecting D respectively form an electrostatic protection device. In addition, Pch transistor 14 and N
The ch transistor 13 is an internal circuit that constitutes an inverter and is connected to a not-shown next-stage internal circuit.
In the electrostatic protection device having such a configuration, the power source V
When a negative high voltage noise with respect to DD or the power supply VSS is applied to the input pad 2, the current flows from the power supply VDD through the diode 12 biased in the reverse direction to the power supply VSS.
To the input pad 2 through the diode 11 forward biased from the power supply VSS. on the other hand,
When a positive high-voltage noise with respect to the power supply VDD or the power supply VSS is applied to the input pad 2, the current flows from the input pad 2 through the gate control diode 10 to the power supply VSS, or from the input pad 2. There is a path that flows through the diode 11 biased in the direction to the power supply VSS, and further flows from the power supply VSS through the diode 12 biased in the forward direction to the power supply VDD.

In order to realize the circuit as described above, the layout pattern of FIG. 5 having the sectional view shown in FIG. 3 has been conventionally used. In FIG. 3, a P well region 2 and an N type impurity region 8 are formed in an N type substrate 1, and a P type impurity region 6, an N type drain region 3 and an N type drain region 3 are formed in the P well region 2. The source region 4 is formed, and a contact hole group for connecting the metal wiring connected to the power supply VDD and the N type impurity region 8 is formed on the N type impurity region 8 on the P type impurity region 6. Is a contact hole group for connecting the metal wiring connected to the power source VSS and the P-type impurity region 6, and the metal wiring connected to the signal input pad 2 and the N-type drain region on the N-type drain region 3. A group of contact holes for connecting the metal wiring connected to the power source VSS and the group of contact holes for connecting the N-type source region 4 are formed on the N-type source region 4. The N-type drain region 3 and the N-type source region 4 and the gate 5 connected to the power supply VSS are the gate control diode 10 in FIG. 4, and the N-type drain region 3 and the P-well region 2 are in FIG. Diode 11
The P well region 2 and the N type substrate 1 respectively form the diode 12 in FIG. Figure 5 shows the layout configuration.
In the above, the N-type impurity region 8 is formed as a rectangular outer periphery of the electrostatic protection device, and the P well region 2 inside thereof is formed.
A P-type impurity region 6 is formed therein as a rectangular stopper frame. N-type drain regions 3 and N-type source regions 4 are alternately arranged with a gate 5 interposed therebetween on a P well region 2 in the frame. When static electricity is applied here, the current for noise removal passes through the portion where the contact holes face each other. Therefore, the path is when negative voltage high voltage noise is applied to the input pad 2 with respect to the power supply VDD. , Between the contact hole group on the drain region 3 and the contact hole group on the impurity region 8, the power supply VDD
On the other hand, when a positive high voltage noise is applied to the input pad 2, between the contact hole group on the drain region 3 and the contact hole group on the impurity region 8 and from the contact hole group on the drain region 3. It is a path that passes through the contact hole group on the source region 4 and the contact hole group on the impurity region 6 to reach the contact hole group on the impurity region 8. When a negative high-voltage noise with respect to the power supply VSS is applied to the input pad 2, the path through which the current flows for removing noise is between the contact hole group on the drain region 3 and the contact hole group on the impurity region 6. When a positive high voltage noise with respect to the power supply VSS is applied to the input pad 2, between the contact hole group on the drain region 3 and the contact hole group on the impurity region 6, and
Contact holes on drain region 3 and source region 4
Between the above contact hole group.

[0004]

However, in the conventional electrostatic protection device having the layout pattern as shown in FIG. 5, the contact hole group on the drain region 3 and the contact hole group on the impurity region 8 are arranged to face each other. Since there are few portions, there are few paths from the contact hole group on the drain region 3 to the contact hole group on the impurity region 8, and there is a problem that it is vulnerable to high voltage and large current, causing breakdown.

Therefore, the present invention solves the above problems and realizes an electrostatic protection device which protects an internal circuit against noise of high voltage and large current.

[0006]

According to another aspect of the present invention, there is provided an electrostatic protection device including the first conductivity type semiconductor substrate formed on the surface of the first conductivity type semiconductor substrate.
A well region of a second conductivity type opposite to the conductivity type and a first well region
A first region of the first conductivity type formed on the surface of the well region and the surface of the well region and connected to the ground terminal by a first contact hole group, and a second contact formed on the surface of the well region and the input terminal or the output terminal. A MOS transistor comprising a drain region of the first conductivity type connected by a group of holes and a gate connected to a ground terminal, the MOS transistor comprising:
The first region is connected to the power supply terminal by a third contact hole group on at least one side of the outer periphery of the transistor, and the length of the facing portion of the second contact hole group and the third contact hole group is 100 μm or more. Characterizing

[0007]

1 and 2 are layout pattern diagrams showing an embodiment of an electrostatic protection device for a signal input terminal of a complementary MOS semiconductor device formed on an N-type substrate according to the present invention. In FIG. 1, a rectangular N-type impurity region 8 is formed on the outer periphery on the N-type substrate so as to surround the P-well region 2, and a metal wiring connected to the power supply VDD and N
A contact hole group is formed to connect with the impurity region 8 of the mold. A rectangular N-type impurity region 7 is formed in the P-well region to form the diode 12 in the circuit of FIG. 4, and a metal wiring connected to the power supply VDD and the N-type impurity region 7 are formed on the rectangular N-type impurity region 7. A contact hole group for connection is formed. This is because the Zener voltage is as high as about 50V when the voltage is applied in the opposite direction in the N ^- P ^- diode composed of the N-type substrate and the P-well region, and the gate 5 is destroyed. This is because a low N ⁺ P ⁻ diode is formed by the N-type impurity region 7 and the P well region. A rectangular P-type impurity region 6 is formed in the P-well region further inside thereof, and a contact hole group for connecting the metal wiring connected to the power supply VSS and the P-type impurity region 6 is formed above the rectangular P-type impurity region 6. There is.
A rectangular N-type drain region 3, a rectangular gate 5 connected to the power supply VSS 5 and a rectangular N-type source region 4 are formed in this order from the outside, respectively, on the N-type drain region 3. Is a group of contact holes that connect the metal wiring connected to the signal input terminal and the N-type drain region 3, and the metal wiring connected to the power supply VSS and the N-type source region 4 on the N-type source region 4. Contact hole groups are formed to connect with each other. On the other hand, in FIG. 2, a comb-shaped N-type drain region 3 and a U-shaped N-type source region 4 are provided inside the rectangular P-type impurity region 6 in the P-well region, and a gate 5 connected to the power supply VSS is provided between them. Similarly, on the N-type drain region 3, a contact hole group for connecting the metal wiring connected to the signal input circuit and the N-type drain region 3 is formed on the N-type source region 4. Is metal wiring connected to the power supply VSS and N
Contact hole groups are formed to connect to the source regions 4 of the mold. 1 and 2 both,
The N-type drain region 3 and the P-well region constitute the diode 11 in the circuit of FIG. 4, and the N-type drain region 3, the gate 5 and the N-type source region 4 constitute the gate control diode 10 in the circuit of FIG. ing. When high voltage noise is applied between the power supply VDD and the signal input terminal, the high voltage noise is removed between the contact hole group on the N-type drain region 4 and the contact hole group on the N-type impurity region 7 to remove it. Current will flow through the path,
In the example of FIG. 2, the length of the portion where the contact hole group on the N-type drain region 4 and the contact hole group on the N-type impurity region 7 face each other is about 200 μm.
The number of paths through which current flows for erasing noise against the power source VDD is high, and the electrostatic withstand voltage at the time of applying noise to the power supply VDD is high. On the other hand, in the example of FIG. 1, the contact hole group on the rectangular N-type drain region 3 is arranged to face the contact hole group on the N-type impurity region 7 on three sides of the N-type drain region 3. Since the length of the portion is approximately 220 μm, there are many paths through which current flows for erasing noise with respect to the power supply VDD, and electrostatic withstand voltage at the time of applying noise to the power supply VDD is high.

FIG. 6 shows the EIAJ (C = 2) of the electrostatic protection device.
It is a characteristic graph figure of the electrostatic withstand voltage with respect to the length of the part which a contact hole group opposes at the time of static electricity application of 00pF, R = 0 (ohm). According to FIG. 6, it is possible to obtain the performance exceeding the general lower limit of 250 V in EIAJ of electrostatic withstand voltage in a region where the length of the facing portions of the contact hole group is 100 μm or more.

[0009]

As described above, according to the present invention, it is possible to realize the electrostatic protection device which protects the internal circuit against noise of high voltage and large current.

The MOS transistor may not have a gate connected to the ground potential or may have no gate.

[Brief description of drawings]

FIG. 1 is a layout diagram showing an embodiment in which the present invention is applied to an electrostatic protection device.

FIG. 2 is a layout diagram showing an embodiment in which the present invention is applied to an electrostatic protection device.

FIG. 3 is a cross-sectional view of a conventional electrostatic protection device.

FIG. 4 is a circuit diagram showing an example of the present invention and a conventional electrostatic protection device.

FIG. 5 is a conventional layout diagram of FIG.

FIG. 6 is a characteristic diagram of electrostatic withstand voltage with respect to a length of a contact hole group facing each other.

[Explanation of symbols]

 1 ... N-type semiconductor substrate 2 ... P-well region 3 ... N-type drain region 4 ... N-type source region 5 ... Gate 6 ... P-type impurity region 7, 8 ... N-type impurity region 10 ... Gate control diode 11, 12 ...... Diode 13 ...... Nch transistor 14 ...... Pch transistor 15 ...... Power supply VDD 16 ...... Power supply VSS 17 ...... Input pad 18 ...... Metal wiring 19 ...... Contact hole 20 ...... Insulation film

Claims (2)

[Claims] 1. A well region of a second conductivity type having a conductivity type opposite to that of the first conductivity type, a first region of the first conductivity type, and a surface of the well region formed on the surface of a semiconductor substrate of the first conductivity type. Of the first conductivity type which is formed on the ground terminal and is connected to the ground terminal by the first contact hole group, and the first conductivity type which is formed on the surface of the well region and is connected to the input terminal or the output terminal by the second contact hole group. A MOS transistor comprising a gate connected to a drain region and a ground terminal,
The first region is connected to the power supply terminal by a third contact hole group on at least one side of the outer periphery of the MOS transistor, and the length of the facing portion of the second contact hole group and the third contact hole group is 100 μm or more. An electrostatic protection device characterized in that 2. The electrostatic protection device according to claim 1, wherein the first conductivity type is N type.