JPS61263256A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61263256A JPS61263256A JP60103735A JP10373585A JPS61263256A JP S61263256 A JPS61263256 A JP S61263256A JP 60103735 A JP60103735 A JP 60103735A JP 10373585 A JP10373585 A JP 10373585A JP S61263256 A JPS61263256 A JP S61263256A
- Authority
- JP
- Japan
- Prior art keywords
- input
- resistor
- type
- semiconductor region
- protection resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract 2
- 229910052782 aluminium Inorganic materials 0.000 abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 23
- 238000009792 diffusion process Methods 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000002265 prevention Effects 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は半導体装置に関し、詳しくは半導体装置の静電
破壊防止回路の技術に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device, and specifically relates to a technique for an electrostatic breakdown prevention circuit for a semiconductor device.
半導体装置の静電破壊防止回路には種々のものがあるが
、一般に入力保護抵抗とクランプ素子との組合せによる
ものがその主流となっている。クランプ素子にはＰＮ接
合ダイオードやＡ！あるいはポリシリコンをフィールド
絶縁膜上にゲート電極として形成した寄生ＭＯ８素子等
がある。また、入力保護抵抗としてはポリシリコンや拡
散抵抗を使用したものが知られている。これら技術は、
例えば本出願人による特願昭５８−２４３８０１号に詳
述されている。Although there are various types of electrostatic damage prevention circuits for semiconductor devices, the mainstream is generally a combination of an input protection resistor and a clamp element. The clamp element is a PN junction diode or A! Alternatively, there is a parasitic MO8 element in which polysilicon is formed as a gate electrode on a field insulating film. Further, as input protection resistors, those using polysilicon or diffused resistors are known. These technologies are
For example, it is detailed in Japanese Patent Application No. 58-243801 filed by the present applicant.
ところで、入力保護抵抗として拡散抵抗を利用した場合
、静電破壊に対して強くかつラツチア、ツブにも強くす
るには拡散抵抗の抵抗値が高い方が良い。しかしながら
、拡散抵抗による入力保護抵抗を高くすると入力から次
段以降への信号が遅延してしまうという問題がある。た
とえば入力信号が直流あるいは低周波であればこの遅延
はさほど問題とならないが、入力信号が高周波であれば
高入力抵抗による遅延が問題となってくる。このよ５Ｋ
、同一基板内の半導体装置に直流あるいは低周波の入力
（以下ＤＣ入力と称する）信号と高周波の入力（以下Ａ
Ｃ入力と称する）信号との両信号か入力として使用され
る場合、入力保護抵抗として抵抗の高いウェル等の拡散
抵抗を用いることができなかった。By the way, when a diffused resistor is used as an input protection resistor, it is better to have a high resistance value of the diffused resistor in order to be strong against electrostatic discharge damage and also against latches and bumps. However, if the input protection resistance using the diffused resistance is increased, there is a problem in that signals from the input to the next stage are delayed. For example, if the input signal is a direct current or a low frequency, this delay is not so much of a problem, but if the input signal is a high frequency, the delay due to high input resistance becomes a problem. This is 5K
, direct current or low frequency input (hereinafter referred to as DC input) signal and high frequency input (hereinafter referred to as A) to the semiconductor device on the same board.
When both signals (referred to as C input) are used as inputs, a diffused resistor such as a well with high resistance cannot be used as an input protection resistor.
本発明の目的は、同一基板内の半導体装置に対して入力
信号としてＤＣ入力およびＡＣ入力を用いることができ
、かつ抵抗の高い拡散抵抗を用いることができるように
した静電破壊保護回路の技術を提供するものである。An object of the present invention is to provide a technology for an electrostatic discharge protection circuit that can use DC input and AC input as input signals for semiconductor devices on the same substrate, and can also use a high-resistance diffused resistor. It provides:
本発明の前記ならびにそのほかの目的と新規な特徴は本
明細書の記述および添付図面からあきらかになるであろ
う。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
〔発明の概要］
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.
すなわち、同一半導体基板の半導体装置に対してＤＣ入
力用端子とＡＣ入力用端子とを備えている。That is, a semiconductor device on the same semiconductor substrate is provided with a DC input terminal and an AC input terminal.
ＤＣ入力用端子は比較的高抵抗の半導体領域である。た
とえばウェル層によって形成された第１の入力保護抵抗
に接続されている。ＡＣ入力用端子は前記半導体領域と
は別個に形成された、たとえば、ポリシリコンあるいは
ウェル層より濃度の高い半導体領域による第２の入力保
護抵抗に接続されている。このため、ＡＣ入力信号をＡ
Ｃ入力端子に印加し、ＤＣ入力信号’ＹＤＣ入力端子に
印加することができ、信号の遅延を防ぐとともに静電破
壊耐圧の向上ならびにラッチアップの防止を達成するも
のである。The DC input terminal is a relatively high resistance semiconductor region. For example, it is connected to a first input protection resistor formed by a well layer. The AC input terminal is connected to a second input protection resistor formed separately from the semiconductor region and made of, for example, polysilicon or a semiconductor region having a higher concentration than the well layer. Therefore, the AC input signal is
It can be applied to the C input terminal and the DC input signal 'YDC input terminal, thereby preventing signal delay, improving electrostatic breakdown voltage, and preventing latch-up.
第】図および第２図は本発明の半導体装置の一実施例な
示し、第１図は静電保護回路の縦断面構造図であり、第
２図はその電気的等価回路図である。1 and 2 show an embodiment of the semiconductor device of the present invention, FIG. 1 is a vertical cross-sectional structural diagram of an electrostatic protection circuit, and FIG. 2 is an electrical equivalent circuit diagram thereof.
第１図において、Ｎ″″型シリコン半導体基板】内には
、第２図の電気的等価回路に示す第１の入力保護抵抗２
、第２の入力保護抵抗３、クランプダイオード４．５か
形成されている。第２図での符号６．７は各々、第１の
保護抵抗２および第２の保護抵抗３に接続されたＤＣお
よびＡＣ入力用端子（パッド）を示し、矢印は内部回路
（図示せず）に接続されている。In FIG. 1, a first input protection resistor 2 shown in the electrical equivalent circuit of FIG.
, a second input protection resistor 3, and a clamp diode 4.5 are formed. Reference numerals 6 and 7 in FIG. 2 indicate DC and AC input terminals (pads) connected to the first protection resistor 2 and the second protection resistor 3, respectively, and arrows indicate internal circuits (not shown). It is connected to the.
第１の入力保護抵抗２はＰ″″型ウェつ膚８で形成され
ており、両端部にはＰ＋型拡散層９を介してＡ２のコン
タクト電極Ａ、Ｂが形成されている。The first input protection resistor 2 is formed of a P″″ type groove 8, and contact electrodes A2 and B are formed at both ends with a P+ type diffusion layer 9 interposed therebetween.
第２の入力保護抵抗３はＰ＋型半導体領域１０で形成さ
れており、両端部には同様にＡ！のコンタクト電極Ｃ，
Ｄが形成されている。The second input protection resistor 3 is formed of a P+ type semiconductor region 10, and similarly A! contact electrode C,
D is formed.
さらに、クランプ素子の一方のダイオード５は、Ｐ−型
ウェル１ｉ】１とこのウェル層１１内（７）Ｎ”型拡散
層１２とによるＰＮ接合で形成されている。Further, one diode 5 of the clamp element is formed by a PN junction between a P- type well 1i]1 and an N'' type diffusion layer 12 (7) in this well layer 11.
Ｎ＋型型数散層１２Ａ！のコンタクト電極Ｅと電気的に
コンタクトをとられ、ウェル層１１はＰ＋型拡散層１３
を介してＡ！のコンタクト電極１４と電気的にコンタク
トがとられてＶｓｓ電位（回路の接地電位たとえばＯＶ
）が供給されている。クランプ素子の他方のダイオード
４は、第１の入力保護抵抗２の場合にはそのＰ−型ウェ
ル層８と基板１とのＰＮ接合で形成され、第２の入力保
護抵抗３の場合にはＰ＋型半導体領域ｌＯと基板１との
ＰＮ接合で形成されている。N+ type scattered layer 12A! The well layer 11 is electrically contacted with the contact electrode E of the P+ type diffusion layer 13.
Via A! electrical contact is made with the contact electrode 14 of
) is supplied. The other diode 4 of the clamp element is formed by a PN junction between the P- type well layer 8 and the substrate 1 in the case of the first input protection resistor 2, and is formed by a P+ junction in the case of the second input protection resistor 3. It is formed by a PN junction between the type semiconductor region lO and the substrate 1.
Ｐ−型ウェル層８，１１は各々内部回路のＮチャネルＭ
Ｏ８素子を用いるためのＰ″″型ウェル層の形成のとき
に同時に形成され、同様にＰ”型拡散層９．１３、Ｐ＋
型半導体領域１０．Ｎ”！Ｊ拡散層１２は内部回路のＰ
チャネルおよびＮチャネルＭＯ８素子のソースおよびド
レイン形成時に同時に形成される。従って、通常、第１
の入力保護抵抗２のＰ−型ウェル層８による抵抗をＩＭ
Ωとすると、第２の入力保護抵抗３のＰ＋型半導体領域
１０の抵抗はｌｋΩ〜２にΩ程度となっている。P-type well layers 8 and 11 each have an N-channel M of the internal circuit.
They are formed at the same time as the P'' type well layer for using the O8 element, and similarly P'' type diffusion layers 9.13, P+
Type semiconductor region 10. N''!J diffusion layer 12 is P of the internal circuit.
It is formed simultaneously when forming the channel and the source and drain of the N-channel MO8 device. Therefore, usually the first
The resistance due to the P-type well layer 8 of the input protection resistor 2 is IM
Ω, the resistance of the P+ type semiconductor region 10 of the second input protection resistor 3 is about lkΩ to 2Ω.
なお、第１図中、符号１５はＰＳＧ等の層間絶縁膜、符
号１６は５ｉＯｔ等のパブシペーシ冒ン膜、符号１７は
Ｓｉｎ、のフィールド絶縁膜を示す。また、第２の保護
抵抗３のＰ＋型半導体領域１０と基板１とのＰＮ接合は
、図示しないがＰ＋型半導体領域１００周辺に形成する
Ｎ＋型型数散層公知のガードリングとの間で形成するこ
とが望ましく、このガードリングに基板１と同電位のＶ
ＤＤ（電源電位たとえば５Ｖ）を供給しておく。In FIG. 1, reference numeral 15 indicates an interlayer insulating film such as PSG, reference numeral 16 indicates a public space insulating film such as 5iOt, and reference numeral 17 indicates a field insulating film such as Sin. Further, the PN junction between the P+ type semiconductor region 10 of the second protection resistor 3 and the substrate 1 is formed between a well-known guard ring of an N+ type scattered layer formed around the P+ type semiconductor region 100, although not shown. It is desirable that this guard ring be connected to V at the same potential as the substrate 1.
DD (power supply potential, for example, 5V) is supplied.
第１図と第２図とを参照すると、上記構成になる静電保
護回路において、コンタクト電極ＡはＤＣ入力用端子６
にＡ！配線され、コンタクト電極ＣはＡＣ入力用端子７
Ｋｋ１３配線され、コンタク上電極ＢおよびＤはλｋに
よって共通接続されるとともにＮ＋型型数散層１２コン
タクト電極ＥＫＡＡ配線されている。Referring to FIGS. 1 and 2, in the electrostatic protection circuit configured as described above, the contact electrode A is connected to the DC input terminal 6.
Ni A! The contact electrode C is connected to the AC input terminal 7.
The upper contact electrodes B and D are commonly connected by λk, and the N+ type scattered layer 12 contact electrode EKAA is wired.
このような構成の静電保護回路はＤＣ入力の保護抵抗と
してＰ″″型クエり層８を用いている。このため、静電
破壊に対しては、＋（正電位）入力の場合ウェル層８と
基板ｌの濃度が低く静電破壊耐圧（順方向）が向上し、
−（負電位）入力の場合、空乏層の広がりが大きく逆方
向耐圧が高くかつ熱破壊に対しても強い。さらにラッチ
アップに対しては、順方向電流が高抵抗のために減少す
るので同様に改善されることがわかる。しかも、ＤＣ入
力用の保護抵抗として専用の第１の入力保護抵抗２を用
い、ＡＣ入力用の保護抵抗として第２の入力保護抵抗３
を用いている。そしてこの第２の入力保護抵抗３を拡散
抵抗で形成する本実施例ではその抵抗を低くしているの
で遅延の問題が解決される。The electrostatic protection circuit having such a configuration uses a P″″ type square layer 8 as a protection resistor for DC input. Therefore, in the case of + (positive potential) input, the concentration of the well layer 8 and the substrate l is low, and the electrostatic breakdown voltage (forward direction) is improved against electrostatic breakdown.
In the case of − (negative potential) input, the depletion layer spreads widely, has a high reverse breakdown voltage, and is resistant to thermal breakdown. Furthermore, it can be seen that latch-up is similarly improved since the forward current is reduced due to the high resistance. Moreover, a dedicated first input protection resistor 2 is used as a protection resistor for DC input, and a second input protection resistor 3 is used as a protection resistor for AC input.
is used. In this embodiment, in which the second input protection resistor 3 is formed of a diffused resistor, the resistance is made low, so that the problem of delay is solved.
なお、本実施例において第２の入力保護抵抗３として拡
散抵抗（半導体領域で形成された抵抗）を用いたがこれ
をポリシリコンによる抵抗として形成することも可能で
ある。さらにまた、クランプ素子４及び５を第１および
第２の入力保護抵抗２．３に対して共用としたが、抵抗
２，３毎に別個に独立して形成して内部回路に接続する
ことも可能であることは当然である。Although a diffused resistor (a resistor formed in a semiconductor region) is used as the second input protection resistor 3 in this embodiment, it is also possible to form this as a resistor made of polysilicon. Furthermore, although the clamp elements 4 and 5 are shared by the first and second input protection resistors 2.3, they may also be formed separately for each of the resistors 2 and 3 and connected to the internal circuit. Of course it is possible.
同一基板内の半導体装置に対して、ＤＣ入力用端子とＡ
Ｃ入力用端子とを備え、ＤＣ入力用端子には比較的抵抗
の高い半導体領域（ウェル層）で形成した第１の入力保
護抵抗を用い、ＡＣ入力用端子にはこれとは別個の第２
の入力保護抵抗を用いている。従って、ＤＣ人力に対す
る静電破壊およびラッチアップの向上がはかれると同時
にＡＣ入力に対しては信号の遅延を防止することができ
るという効果を有する。For semiconductor devices on the same board, DC input terminal and A
A first input protection resistor formed of a relatively high resistance semiconductor region (well layer) is used for the DC input terminal, and a separate second input protection resistor is used for the AC input terminal.
input protection resistor is used. Therefore, it is possible to improve electrostatic damage and latch-up caused by DC input, and at the same time, it is possible to prevent signal delay with respect to AC input.
以上本費明者によ−ってなされた発明を実施例にもとづ
き具体的に説明したが、本発明は上記実施例に限定され
るものではなく、その要旨を逸脱しない範囲で種々変更
可能であることはいうまでもないＯ
〔利用分野〕
本発明は少なくとも直流入力あるいは低周波入力をもつ
とともに高周波入力をももつ集積回路、たとえば、Ｃ−
ＭＯＳ、加入者線回路を有した半導体装置に適用できる
。Although the invention made by the present inventor has been specifically explained above based on examples, the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. [Field of Application] The present invention is applicable to integrated circuits having at least a DC input or a low frequency input as well as a high frequency input, such as a C-
It can be applied to semiconductor devices having MOS and subscriber line circuits.
第１図は本発明の半導体装置の一実施例の静電保護回路
の断面構造図、
第２図は第１図の静電保護回路の電気的等価回路である
。
１・・・半導体基板、２・・・第１の保護抵抗、３・・
・第２の保護抵抗、４．５・・・クランプダイオード、
６・・・ＤＣ入力用端子、７・・・ＡＣ入力用端子、８
．１１・・・Ｐ−型ウェル層（半導体領域）、９，１３
・・・Ｐ＋星拡散層、１０・・・Ｐ＋型半導体領域、１
２・・・Ｎ４型゛拡散層、１６・・・パッシベーシヲン
ＩＩ、１７・・・フィールド絶縁膜、Ａ、Ｂ、Ｃ，Ｄ、
Ｅ、１４・・・コン第 １ＦｊＡ
第 ２ 図FIG. 1 is a cross-sectional structural diagram of an electrostatic protection circuit of an embodiment of the semiconductor device of the present invention, and FIG. 2 is an electrical equivalent circuit of the electrostatic protection circuit of FIG. 1. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... First protective resistor, 3...
・Second protection resistor, 4.5...clamp diode,
6...DC input terminal, 7...AC input terminal, 8
．． 11...P-type well layer (semiconductor region), 9, 13
...P+ star diffusion layer, 10...P+ type semiconductor region, 1
2... N4 type diffusion layer, 16... Passive basin II, 17... Field insulating film, A, B, C, D,
E, 14... Con No. 1FjA Fig. 2
Claims (1)
とを備え、前記ＤＣ入力用端子は比較的高抵抗の半導体
領域によって形成された第１の入力保護抵抗に接続され
、前記ＡＣ入力用端子は前記半導体領域とは別個に形成
された第２の入力保護抵抗に接続されたことを特徴とす
る半導体装置。1. A DC input terminal and an AC input terminal are provided on the same semiconductor substrate, the DC input terminal is connected to a first input protection resistor formed by a relatively high resistance semiconductor region, and the AC input terminal is connected to a first input protection resistor formed of a relatively high resistance semiconductor region. A semiconductor device characterized in that a terminal is connected to a second input protection resistor formed separately from the semiconductor region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60103735A JPS61263256A (en) | 1985-05-17 | 1985-05-17 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60103735A JPS61263256A (en) | 1985-05-17 | 1985-05-17 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61263256A true JPS61263256A (en) | 1986-11-21 |
Family
ID=14361887
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60103735A Pending JPS61263256A (en) | 1985-05-17 | 1985-05-17 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61263256A (en) |
-
1985
- 1985-05-17 JP JP60103735A patent/JPS61263256A/en active Pending
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