JPS61262951A - Fault recovery system for microprogram memory by service processor - Google Patents

Abstract

PURPOSE:To avoid a system breakdown state due to the incapability of fault recovery of a control memory by using a device processor for the correction of the fault of the control memory. CONSTITUTION:When a parity check circuit 14 detects a parity check error, an R-SFF 15 is set through a signal line 105. Thus gates 16-18 are closed to suppress a replacement. At the same time, the trouble of a control memory 12 is informed to a service processor 2 through a communication control line 107. The processor 2 reads out the values of a CM register 10, a CM address register 11 and a CM address history register 13 via a scan bus 108 and checks te fault generating address of the memory 12 from the value of the register 11 to write the correct value of a microprogram command to a service processor maintenance area on the memory 12. While the address branching out to the fault generating address is checked from the value of the register 13 for the correction of the branch field of the microprogram command. Then the corrected field is branched out to the device processor maintenance area and written to the present address of the memory 12.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a failure recovery method for microprogram memory (generally referred to as control memory), and particularly to control memory (hereinafter sometimes referred to as CM) by a service processor. Failure recovery method [Conventional technology] In recent years, in the era of increasing integration with LSI and VLSI, the number of fits in static RAM used for control memory has been increasing as a proportion of the number of fits in the entire device. be. In a microprogram controller,
It is no longer rare to find devices in which the proportion of static RAM in the control memory is about 50%. Therefore, among the cases where the system goes down, the percentage of static RAM destruction tends to increase.

[Problem that the invention seeks to solve]

Conventionally, this type of device has performed a parity check in small systems, but parity errors have led to system downtime.

In addition, medium-sized and large-sized systems used Hamming codes to correct single-bit errors, but this resulted in an increase in hardware. Moreover, a 2-bit error in the control memory caused the system to go down. When the system went down, the equipment would not start up until a maintenance person replaced the faulty package.

The object of the present invention is to control the faulty microprogram command by the control memory processor when an unrecoverable error occurs (for example, a 1-bit error in parity check or a 2-bit error in ECC). By writing to the maintenance area of the memory, modifying the branch destination address of the microprogram command that branches to the microprogram command, and writing it to the control memory, the above-mentioned drawbacks are solved and system down due to unrecoverable failure of the control memory is avoided. The purpose is to provide a method.

[Failure to solve the problem]

The present invention provides a microprogram control device having a service processor, and a control memory having a service processor maintenance area.

an address register of the control memory; an address history register that holds a history of one or more control memory addresses; a microphrogram command register that stores the output of the control memory indicated by the address register; a fault detection circuit that detects a fault in a microprogram command; a flip-flop that is set when a fault is detected by the fault detection circuit;
means for inhibiting updating of the control memory address register, the address history register, and the control memory command register when the flip-flop is set; and a communication means for notifying the service processor of the occurrence of a failure; The service processor reads the contents of the control memory address register, the address history register, and the control memory command register in response to a signal from the means, and also reads out the contents of the control memory address register, the address history register, and the control memory command register, and avoids the faulty microprogram command and stores the faulty area in the control memory maintenance area. This is a microprogram memory failure recovery method characterized by performing control to write a microprogram command and a microprogram command modified to branch to the =4-microprogram command in which the failure occurred.

〔Example〕

Next, one embodiment of the present invention will be described in detail with reference to the drawings.

In FIG. 1 showing a first embodiment of the invention.

The failure recovery device of the present invention is a central processing unit (hereinafter referred to as a central processing unit).

It consists of a CPU (abbreviated as "CPU") 1 and a service processor 2. In the addressing system of the microprogram control device, the address of the next microprogram to be executed is specified through the entire control line 100 by some fields of the CM register 1o. The address is written to the CM address register 11. The control memory 12 is read from the address line 101K of the CM address register 11.

Microprogram command cutter line 1 to be executed next
02 is set in the CM register 10 throughout. Also,
The previously executed microprogram address is set in the CM address history register 13 through the address line 103.

When checking the correctness of the control memory only by a parity check, the data in the CM register 10 passes through the data line 104 and is subjected to a parity check in the parity check circuit 14. When a parity check error is detected, the entire parity error signal line 105 is
S flip-flop 15 is set. As soon as the flip-flop 15 is turned on, the control line 10 becomes
0M address register for CM register by 6]1
゜Each gate circuit 16 for setting the CM address history register 13. Gate circuit 17. Gate circuit 1
Close 8 and prevent updates. In addition, the service process 9 is notified by the communication control 1107 of the occurrence of a ``j2 VC control memory failure''.

Service processor 2 immediately scans CM register 10 . CM address register 11
．． Read the value of CM address history register 13. CM
The failure address in the control memory is checked from the value of the address register 11, and the correct value of the microprogram command is written into the service processor maintenance area on the control memory. In addition, the branch field of the check microprogram command is modified so that the address that branches to the failure address is written to the current address of the control memory based on the value of the CM address history register 13, so that the address branches to the service processor maintenance area. It's crowded.

Finally, the value of the CM register 10 is saved as log data of the bus processor 2 as failure information of the IC to be replaced during regular maintenance.

Figure 2 shows microprogram commands A and B.

This is a flow in which the microprogram was modified by the service processor because a failure occurred in the microprogram command B while it was being executed sequentially.

Further, FIG. 5 is a timing chart for the case of FIG. 2. Address A of the 0M address register becomes command A of the control memory and is set in the CM register. C
Address B is set in the 0M address register by some fields of command A in the M register, and at the same time, address A is placed in the CM address history register. Command B is read to the CM register by address B of the 0M address register, but since a parity error is detected, the R-8 flip-flop is set and updates of the 0M address register, CM register, and CM address history register are inhibited. .

Finally, FIG. 4 is a control memory map diagram showing a case where a microprogram branch spans between pages of the control memory. In the case where a service processor maintenance area is provided in each page and a failure occurs in command B as shown in FIG.

The service processor writes command Bi to the maintenance area within the same page. By doing this, command A
It has been shown that it will be easier to correct addresses. ” [Effects of the Invention] As explained above, the present invention has the advantage that by configuring the service processor to perform correction in the event of a failure in the multi-control memory, the possibility of system failure of the microprogram device can be reduced. effective.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. Figure 2 is a flow diagram of the microprogram, Figure 3 is the flow diagram of the microprogram.
FIG. 4 is a time chart when a failure occurs in the microprogram flow shown in FIG. 4, and FIG. 4 is a control memory map diagram of FIG. ]...Central processing unit, 2...Service processor. 10...CM register, 11...0M address register. 12...Control memory, 13...CM address history register. 14...Parity check circuit. 15...R-S flip-flop.

Claims (1)

[Claims] 1. In a microprogram control device having a service processor, a microprogram storage circuit having a maintenance area for the service processor, a microprogram address register of the storage circuit, and a history of one or more microprogram addresses are retained. an address history register that stores an output of the storage circuit indicated by the address register; a fault detection circuit that detects a fault in a microprogram command stored in the command register; a flip-flop that is set when a fault is detected in the circuit; and means for inhibiting updating of the address register, the address history register, and the command register when the flip-flop is set;
and communication means for notifying the service processor of the occurrence of a fault, and in response to the signal from the communication means, the service processor reads the contents of the address register, the address history register, and the command register, and also reads out the contents of the microprogram in which the fault has occurred. By writing the faulty microprogram command and a microprogram command in which the branch field of the microprogram command is modified so as to branch to the faulty microprogram command in the maintenance area of the storage circuit, avoiding the command. A microprogram memory failure recovery method characterized in that recovery is performed in the event of a failure in a memory circuit.