JPS61261972A - Video signal processor - Google Patents

Abstract

PURPOSE:To perform the optimum process regardless of a scanning system by processing a video signal using a alternatively a field number discriminating signal and a frame period signal which are obtained from a vertical and a horizontal synchronizing signals in the video signal. CONSTITUTION:An inputted video signal is sent to a horizontal synchronizing separator circuit 1 and a vertical synchronizing separator circuit 2 through a compound synchronizing separator circuit 11 and a horizontal synchronizing signal (HD) and a vertical synchronizing signal (VD) are separated. A field discriminating circuit 3 outputs the discriminating signal of a field number from the HD and the VD and supplies them to an interlace/non-interlace detecting circuit 5. And by the output of the detecting circuit 5, the field discriminating signal in an interlace scanning system or the output of a false field discriminating signal generating circuit 4 to which the VD signal is inputted in a non-interlace scanning system is supplied to a processing circuit 12 as a field synchronizing signal.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a video signal processing device, and more particularly to a video signal processing device capable of processing a video signal using a so-called interlaced scanning method in which one frame is formed by a plurality of fields. It is.

<Summary of the Disclosure> This specification and drawings describe a discrimination signal obtained by discriminating the field number using vertical and horizontal synchronization signals in a video signal, and a frame period generated using the vertical synchronization signal in the video signal. By processing the video signal using the signal as an alternative, the same signal processing can be performed regardless of whether an interlaced scanning video signal or a non-interlaced scanning video signal is input. The present invention discloses a technology that enables optimal signal processing for each scanning method.

<Prior Art> Conventionally, a video signal processing device capable of processing a video signal using an interlaced scanning method has generally been configured as shown in FIG.

The input video signal is supplied to a composite synchronization separation circuit 11, where a composite synchronization signal 5ync is separated.

5ync further includes an HD separation circuit 1. It is supplied to the VD separation circuit 2, where the horizontal synchronization signal ()! D), vertical synchronization signal (
VD) are separated from each other. The field discrimination circuit 3 uses the separated HD and VD signals to discriminate whether the input video signal is a first (odd number) field or a second (even number) field.

FIG. 5 is a timing chart for explaining the operation of each part in FIG.
outputs a field discrimination signal as shown in FIG. 5(b), which has a high level (H) in the first field portion of the video signal and a low level (L) in the second field portion, for example. This is referred to as a field synchronization signal (FD).

These HD, VD, FD, etc. are supplied to the video signal processing circuit 12 together with the input video signal, and used for processing the video signal. Now, assuming a printer device as the output system device 1. For example, a video signal using an interlaced scanning method is converted into analog/digital (A/D), and when transferred to memory, the @l field video signal is converted into a second For example, if the memory is a line memory corresponding to pixels on a straight line extending vertically on the output screen, the video signal of the first field is determined. is an odd numbered address, and an even numbered address is given to the video signal of the second field.

<Problems to be Solved by the Invention> However, in recent years, there has been a need to handle not only interlaced scanning video signals such as television signals but also non-interlaced scanning video signals output from microcomputers and the like. When a video signal based on the non-interlaced scanning method is input to the device as shown in FIG. 4, it is always determined to be the video signal of one field, as shown in FIGS. 5(c) and 5(d).

Therefore, for example, when using a printer device as described above as an output system device, only the scanning line corresponding to one field is printed, or the scanning line corresponding to one field is printed normally, but the scanning line corresponding to the other field is printed normally. In the scanning lines, situations such as incorrect data being printed occur, resulting in a significant deterioration of the output image quality.

In view of the problems typified above, the present invention has been developed to provide a video signal that is optimal for each scanning method, regardless of whether the input video signal is based on an interlaced scanning method or a non-interlaced scanning method. An object of the present invention is to provide a video signal processing device that can perform signal processing.

<Means for Solving the Problems> In order to solve the above-mentioned problems, the present invention uses a discrimination signal obtained by discriminating the field number using vertical and horizontal synchronization signals in a video signal; The video signal is processed using a frame period signal generated using a vertical synchronization signal in the video signal.

<Operation> By configuring as described above, the same signal processing is possible whether a video signal using an interlaced scanning method or a video signal using a non-interlace scanning method is input, and each scanning method is It is now possible to perform optimal signal processing for

(Embodiment) The present invention will be explained below using an embodiment. Fig. 1 is a diagram showing a video signal processing device as an embodiment of the present invention, and the same components as in Fig. 4 are the same. They are numbered and their explanations are omitted.

The field discrimination signal is input to the interlace/non-interlace detection circuit 5, and is also input to the changeover switch 6.
It is also supplied to the I side of. On the other hand, VD is supplied to a pseudo field discrimination signal generation circuit 4, and a frame period signal is supplied from the circuit 4 to the N side of the switch 6.

In the interlace/non-interlace detection circuit ty5, if the field discrimination signal is inverted for each field, it is determined that the video signal is based on the interlace scanning method, and if not, it is determined that the video signal is based on the non-interlace scanning method. Depending on the output signal of the circuit 5, the switch 6 outputs a field discrimination signal (shown in FIG. 5(b)) from the circuit 3 in the case of an interlaced scanning video signal, and outputs the field discrimination signal (shown in FIG. 5(b)) from the circuit 3 in the case of a non-interlaced scanning video signal. outputs a periodic signal (shown in FIG. 5(e)) from the circuit 4.

With the above configuration, the same F
D is obtained. Therefore, for example, when a printer device as described above is used as an output device, even if a video signal based on a non-interlaced scanning method is input, the first . The same data will be printed on the scan line corresponding to the second field. That is, the same data is written to address numbers (2n) and (2n-1) of the vertical line memory.

FIG. 2 is a diagram showing a video signal processing circuit 12 as another embodiment of the present invention. In FIG. 2, the same components as in FIG. 4 are designated by the same numbers, and their explanations will be omitted. HD is on the I side of switch 8, VD is on the field discrimination/
The signal is input to the pseudo field 1 discrimination signal generation circuit 9. The ltj force of the circuit 9 inverted by the inverter 10 is input to the N side of the switch 8 . The switch 8 is controlled by the manual operation of the interlace/non-interlace switching circuit 7, and supplies HD to the circuit 9 when the interlace scanning method is specified, and supplies the output of the inverter 10 to the circuit 9 when the non-interlace scanning method is specified. In the case of interlaced scanning, the circuit 9 functions similarly to the field discrimination circuit 3 of FIG. 1 and outputs a field discrimination signal.

In the case of non-interlaced scanning, the output of the inverter 10 is output every time VD is input, and a pseudo field discrimination signal of the frame period is output.

FIG. 3 is a diagram showing a specific circuit configuration of the main parts of the device shown in FIG. ).Here, if the interlaced scanning method is specified by the circuit 7, the AND gate 13 supplies HD to the (or game) 1B, and since the output of the inverter 14 is L, the output of the AND gate 15 also becomes L, and the D terminal of DFF17 is H from the OR gate 16.
D is supplied, and the DFF 17 operates as a field discrimination circuit. That is, in the first field) (D and VD
The timings match, and in the second field when the Q output is H1, the timings of HD and VD are shifted by 1/2 horizontal scanning period, so the Q output becomes L, and this Q output is used as the FD.

On the other hand, when the non-interlaced scanning method is specified by the circuit 7, the AND gate 13 does not pass through the HD and its output is always L. And gate 15 is DFF
The Q output of 17 is supplied to the OR gate 16. Therefore DF
The Q output of F17 is inverted every time VD is input, and operates as a pseudo field discrimination signal generation circuit.

It goes without saying that even in the configuration as described above, the same effects as in FIG. 1 can be obtained.

<Effects of the Invention> As explained above, according to the present invention, whether the input video signal is an interlaced scanning method or a non-interlaced scanning method, A video signal processing device capable of performing optimal signal processing is obtained.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a video signal processing device as an embodiment of the present invention, FIG. 2 is a diagram showing the configuration of a video signal processing device as another embodiment of the invention, and FIG. 2 is a diagram showing an example of a specific circuit configuration of the main part of the device shown in FIG. 4, FIG. 4 is a diagram showing the configuration of a conventional general video signal processing device, and FIG. It is a timing chart for explaining the operation. 1 is an HD separation circuit, 2 is a VD separation circuit, 3 is a field discrimination circuit, 4 is a pseudo field discrimination signal (periodic signal) generation circuit, 5 is an interlace/non-interlace switching circuit, 6 is a changeover switch, and 7 is an interlace/non-interlace circuit. 8 is a switch, 9 is a field discrimination/pseudo field discrimination signal generation circuit, and 12 is a video signal processing circuit.

Claims (1)

[Claims] means for separating vertical and horizontal synchronization signals in a video signal; means for determining a field number of the video signal using the separated vertical and horizontal synchronization signals to generate a discrimination signal; 1. A video signal processing apparatus, comprising means for generating a frame period signal using a synchronization signal, and processing the video signal using alternatively the discrimination signal and the period signal.