JPS61260673A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the ohmic resistance of an ohmic electrode by introducing an element from the outside to a surface layer in a region in which the ohmic electrode is formed. CONSTITUTION:The ions of Si as an N-type impurity I for shaping source/drain regions 3 are implanted to a substrate 1 in which a channel region 2 and a gate electrode 4 are formed according to a conventional manufacturing process and a mask 8 patterned conformed to the source/drain regions 3 is shaped. The implantation of In as an introducing element E is added. The implantation of In is added, and processes are returned to the conventional manufacturing process again. Regarding Ga1-xXInXAs in a surface layer 7 shaped, X is increased on the surface side though X changes in the depth direction that is, a band gap is narrowed on the surface side, and the ohmic resistance of an ohmic electrode 6 formed is reduced largely as approximately half a conventional example.

Description

[Detailed Description of the Invention] [Summary] In a semiconductor device in which an ohmic electrode is formed on a compound semiconductor, the bandgap of the surface layer in the region where the ohmic electrode is formed is narrowed by introducing an element from the outside. This reduces the Ohmink resistance of the electrode.

[Industrial application field]

The present invention relates to a semiconductor device using a compound semiconductor, and particularly to the configuration of a junction portion of an ohmink electrode.

Semiconductor devices using compound semiconductors are increasingly being used as high-speed operation semiconductor devices and optical semiconductor devices.

In these semiconductor devices, since the object to which the ohmic electrode is bonded is a compound semiconductor, the ohmic resistance is generally high, but its reduction is desired to improve quality.

[Conventional technology]

Figure 4 shows a gallium arsenide field effect transistor (GaAs-FET), which is an example of a semiconductor device using a compound semiconductor.
FIG.

In the figure, 1 is semi-insulating gallium arsenide (GaAs)
2 is a channel region in which silicon (Si), which is an n-type impurity, is implanted and activated to make it an n-type; 3 is a source/drain region in which Si is also implanted and activated to make it an n-type;
4 is a gate electrode made of tungsten (W) silicide, 5 is an insulating layer made of silicon dioxide (SiO2), and 6 is an ohmic electrode made of gold germanium/gold (^uGe/Au) that is in ohmic contact with the source/drain region 3.

In this GaAs-FET, one of two source/drain regions 3 serves as a source and the other serves as a drain, and the drain current flowing between the two is controlled by the voltage of the gate electrode 4. This drain current is then led out by the ohmic electrode 6.

[Problem that the invention seeks to solve]

Therefore, for the drain current, the source/drain region 3
Since the junction resistance (ohmic resistance) existing between the electrode 6 and the ohmic electrode 6 is connected in series, it is desirable that this ohmic resistance is small.

However, since the source/drain region 3 of the GaAs-FET is formed of GaAs, there is a problem in that the ohmic resistance cannot be made sufficiently small due to the size of the hand gap.

This problem is not limited to the GaAs-FET described above, but is a common problem in many semiconductor devices using compound semiconductors.

[Means for solving problems]

FIG. 1 is a side sectional view showing the gist of the present invention.

As shown in FIG. 1, the above problem is caused by the region 3 (i.e., the source/drain region also) in which the ohmic electrode 6 (i.e., the ohmic electrode 6 in the case shown in FIG. 4) is formed, which is made of the first compound semiconductor, as shown in FIG. The surface layer 7 of 3) is changed into a second compound semiconductor having a band gap narrower than that of the first compound semiconductor by introducing an element E from the outside prior to the formation of the ohmic electrode 6. This problem is solved by the semiconductor device of the present invention.

[Function] With the above configuration, the semiconductor to which the ohmic electrode 6 is bonded changes from the conventional first compound semiconductor to the second compound semiconductor, and its bandgap becomes narrower than before, so the ohmic resistance of the ohmic electrode is reduced. Smaller than before.

By this, for example, the GaAs-FET shown in FIG.
It is possible to improve the quality of the semiconductor device, such as by reducing the resistance connected in series with the drain current and improving the operating speed.

〔Example〕

FIG. 2 is a side sectional view of an embodiment of a semiconductor device according to the present invention;
FIG. 3 is a side sectional view of a manufacturing process for realizing the present invention in its embodiment.

The semiconductor device shown in FIG. 2 is the GaAs-FET shown in FIG.
The configuration of the present invention is applied to.

That is, indium (In), which is the element E, is formed on the surface layer 7 of the source/drain region 3 where the ohmic electrode 6 is formed.
is introduced, and the surface layer 7 is made of gallium indium arsenide (Gal
-xlnx As), and the rest is the same as shown in FIG.

Below, using FIG. 3, the surface layer 7 is made of Gal-xlnXAs.
We will explain the manufacturing process to change the

Channel region 2 and gate electrode 4 are formed according to conventional manufacturing processes.
Si, which is an n-type impurity I, for forming the source/drain regions 3 is implanted into the substrate 1 on which a mask 8 of, for example, 5i02, which is patterned to match the source/drain regions 3, is formed by ion implantation. do.

After this, implantation of In, which is the introduced element E, is added.

This implantation is performed by an ion implantation method, and the conditions are, for example, 100Keν, 3X]O''/cd.

After adding In implantation, the conventional manufacturing process is resumed.

With only the above-mentioned In implantation, the surface layer 7 is formed of Ga, xlnx
It has not changed to As. In order to change to Ga1-xlnxAs, a treatment is required to crystallize the implanted In together with GaAs.

This treatment is simultaneously performed by heat treatment at, for example, 750° C. for 15 minutes to activate the source/drain regions 3 into which Si is implanted.

Therefore, it is possible to form such a surface layer 7 by simply adding a step.

The Ga1-xlnx As of the surface layer 7 thus formed is
Although X changes in the depth direction, it is larger on the surface side, that is, the band gap is narrower on the surface side, and the ohmic resistance of the formed ohmic electrode 6 is significantly reduced to about 1/2 of that of the conventional example.

In the above embodiment, the element E was implanted into the surface layer 7 by the ion implantation method, but it may be performed by other methods such as diffusion.

Further, although the above embodiment is for a GaAs-FET, it is easy to see that the structure of the present invention is also effective in semiconductor devices using other compound semiconductors and other semiconductor devices having ohmic electrodes due to its operation. I can understand.

〔Effect of the invention〕

As explained above, according to the configuration of the present invention, in a semiconductor device using a compound semiconductor, the ohmic resistance of the ohmic electrode can be reduced, and the quality of the semiconductor device can be improved.

[Brief explanation of drawings]

FIG. 1 is a side sectional view showing the gist of the invention, FIG. 2 is a side sectional view of an embodiment of a semiconductor device according to the invention, and FIG. 3 is a side sectional view of a manufacturing process for realizing the invention in the embodiment. , FIG. 4 is a side sectional view of an example of a semiconductor device using a compound semiconductor. In the figure, 1 is the substrate, 2 is the channel region, 3 is the source/drain region (the region where 6 is formed), 4 is the gate electrode, 5 is the insulating layer, 6 is the ohmic electrode, 7 is the surface layer of 3, 8 is a mask, E is an introduced element, and ■ is an impurity. 7i, shows the drinking intention of Rimoe 1 1 time 1 town map 1st g waste banquet direction 4 evening 1 nobu Norizono gamma side B stroke % 2 close a 3 map squid Come on, Iroriba ff1lllc Kude $4
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Claims (1)

[Claims] The surface layer (7) of the region (3) made of the first compound semiconductor and in which the ohmic electrode (6) is formed is caused by the introduction of an element (E) from the outside prior to the formation of the ohmic electrode (6). 1. A semiconductor device characterized by being changed into a second compound semiconductor having a bandgap narrower than that of the first compound semiconductor.