JPS61260646A - Packing method for semiconductor chip - Google Patents

Packing method for semiconductor chip

Info

Publication number
JPS61260646A
JPS61260646A JP60101615A JP10161585A JPS61260646A JP S61260646 A JPS61260646 A JP S61260646A JP 60101615 A JP60101615 A JP 60101615A JP 10161585 A JP10161585 A JP 10161585A JP S61260646 A JPS61260646 A JP S61260646A
Authority
JP
Japan
Prior art keywords
semiconductor chip
sub
die
substrate
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60101615A
Other languages
Japanese (ja)
Inventor
Masabumi Suzuki
正文 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP60101615A priority Critical patent/JPS61260646A/en
Publication of JPS61260646A publication Critical patent/JPS61260646A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To realize a smaller-size, higher-density package by a method wherein a semiconductor chip is die-bonded to a sub-substrate built of a metal plate, the sub-substrate is die-bonded to a main substrate, and wire-bonding is accomplished between an electrode and a conductor on the main substrate. CONSTITUTION:A semiconductor chip 12 is die-bonded to a sub-substrate 11 built of a metal plate. Next, the sub-substrate 11 mounted with the semiconductor chip 12 is die-bonded to a mount 14 positioned on a main substrate 13 and, further, an electrode of the semiconductor chip 12 is directly wired to a conductor 15 located on the main substrate 13 with a wire 16. This design realizes a smaller-size, higher-density package.

Description

【発明の詳細な説明】 （産業上の利用分野） この発明は、マイクロエレクトロニクス分野での１ルチ
半導体テップ実装法として利用できる半導体チップの実
装法に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor chip mounting method that can be used as a single multi-semiconductor chip mounting method in the microelectronics field.

（従来の技術） 半導体チップをワイヤーボンディング法で薄膜または厚
膜基板上に実装する場合、従来は、半導体チップを直接
基板にダイスボンディング、ワイヤーボンディングする
ダイレクトボンディング法と、簡易チップキャリアを用
いて実装する方法がとられている。(Conventional technology) When mounting a semiconductor chip on a thin film or thick film substrate using a wire bonding method, conventionally, the semiconductor chip is mounted using a direct bonding method in which die bonding and wire bonding are performed directly to the substrate, and a simple chip carrier. A method is being taken to do so.

第２図は、例えばＩＣ化実装技術（１９８０−１−１５
）株式会社工業調査会Ｐ　１０２に開示されるようなダ
イレクトボンディング法を具体的に示す断面図である。Figure 2 shows, for example, IC mounting technology (1980-1-15).
) is a sectional view specifically showing a direct bonding method as disclosed in Kogyo Kenkyukai Co., Ltd. P102.

この方法は、基板上のマウント部２に半導体チップ３を
直接ダイスボンディングした後、基板ｌ上の導体４に半
導体チップ３の電極をワイヤ５で直接配線する。In this method, a semiconductor chip 3 is directly die-bonded to a mounting portion 2 on a substrate, and then electrodes of the semiconductor chip 3 are directly wired with wires 5 to conductors 4 on a substrate l.

第３図は、簡易チップキャリアを用いて実装する方法を
具体的に示す断面図である。この方法は、半導体チップ
３を簡易チップキャリア６にダイスボンディングし九後
、この簡易チップキャリア６に半導体チップ３の電極を
ワイヤ７を用いて配線し、しかる後、その簡易チップキ
ャリア６を基板ｌのマウント部２にダイスボンディング
するとともに、その簡易チップキャリア６を基板ｌ上の
導体４にワイヤ８を用いて配線する。FIG. 3 is a sectional view specifically showing a mounting method using a simple chip carrier. This method involves die bonding a semiconductor chip 3 to a simple chip carrier 6, wiring the electrodes of the semiconductor chip 3 to this simple chip carrier 6 using wires 7, and then attaching the simple chip carrier 6 to a substrate. At the same time, the simple chip carrier 6 is wired to the conductor 4 on the substrate l using wires 8.

（発明が解決しようとする問題点） しかるに、ダイレクトボンディング法では、半導体チッ
プ３が基板ｌのマウント部２に直接ダイスボンディング
されるため、ボンディングミスや不良半導体チップ混入
時の半導体チップ交換・改修が困難であるという欠点が
あった。また、簡易チップキャリアを用いる方法では、
実装面積が大きく、小型・高密度実装が不可能で、しか
もダイスボンディングとワイヤーボンディングが二度手
間という欠点があった。(Problems to be Solved by the Invention) However, in the direct bonding method, the semiconductor chip 3 is die-bonded directly to the mount portion 2 of the substrate l, so it is difficult to replace or repair the semiconductor chip when a bonding error occurs or a defective semiconductor chip is mixed in. The drawback was that it was difficult. In addition, in the method using a simple chip carrier,
The problem was that the mounting area was large, making compact and high-density mounting impossible, and that die bonding and wire bonding were required twice.

（問題点を解決するための手段） そこで、この発明では、半導体チップを金属板からなる
サブ基板にダイスボンディングした後、そのサブ基板を
メイン基板にダイスボンディングし、一方、ワイヤーボ
ンディングは、半導体チップの電極とメイン基板上の導
体との間で直接行う。(Means for Solving the Problem) Therefore, in the present invention, a semiconductor chip is dice-bonded to a sub-board made of a metal plate, and then the sub-board is die-bonded to a main board. directly between the electrode and the conductor on the main board.

（作用） このような方法によれば、メイン基板に対するダイスボ
ンディングミスや不良半導体チップ混入時の改修や交換
は、サブ基板ごと行える。また、サブ基板は、半導体チ
ップをダイスビンディングするだけであるから、半導体
チップとほぼ同一面積の小さいものとすることができる
。(Function) According to such a method, when a die bonding error or a defective semiconductor chip is mixed into the main board, repair or replacement can be performed for the entire sub-board. Moreover, since the sub-board only performs die binding of the semiconductor chip, it can be made small and have approximately the same area as the semiconductor chip.

（実施例） 以下この発明の一実施例を図面を参照して説明する。第
１図はこの発明の一実施例を示す断面図である。この図
において、１１はサブ基板で、銅板など金属板（厚みは
最大０．２１程度）からな夛、はぼ半導体チップと同一
の大きさに形成される。(Embodiment) An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing an embodiment of the present invention. In this figure, a sub-substrate 11 is made of a metal plate such as a copper plate (maximum thickness is about 0.21 mm), and is formed to have the same size as the semiconductor chip.

このサブ基板ｌｌ上に半導体チップ１２をダイスボンデ
ィングする。そして、その後、前記半導体チップ１２を
搭載したサブ基板１１をメイン基板１３上のマウント部
１４にダイスボンディングし、さらに、メイン基板１３
上の導体１５に半導体チップ１２の電極をワイヤ１６を
用いて直接配線する。A semiconductor chip 12 is die-bonded onto this sub-substrate ll. After that, the sub-board 11 on which the semiconductor chip 12 is mounted is die-bonded to the mount part 14 on the main board 13, and then the sub-board 11 is mounted on the main board 13.
The electrodes of the semiconductor chip 12 are directly wired to the upper conductor 15 using wires 16 .

なお、このような実装法においては、半導体テップ１２
をサブ基板１１上にダイスビンディングした状態で、第
４図に示すようにグローブカード１７を使用して半導体
チップ１２の特性選別を実施し、以後、良品半導体チッ
プのみ、メイン基板１３に対するダイスボンディングな
どその後の工程を実施するとよい。Note that in such a mounting method, the semiconductor chip 12
With the semiconductor chips 12 dice-bonded onto the sub-board 11, characteristics of the semiconductor chips 12 are selected using a glove card 17 as shown in FIG. It is advisable to carry out the subsequent steps.

この特性選別の時、グランド（ＧＮＤ　）をチップ裏面
よシ取シ出している半導体チップ１２においては、サブ
基板１１から端子を取シ出せば、半導体チップ１２のＶ
／Ｉ　％性を正確にチェックできる。この時、勿論、半
導体チップ１２とサブ基板１１は、例えばＡＰペースト
法、共晶法あるいはハンダ法などの導電法の良い接着法
を用いてダイスボンディングが行われている。また、サ
ブ基板１１の素材は鋼板などであるが、その表面にＡｕ
メッキ。At the time of this characteristic selection, in the semiconductor chip 12 whose ground (GND) is taken out from the back of the chip, if the terminal is taken out from the sub-board 11, the voltage of the semiconductor chip 12 is
/I %ability can be checked accurately. At this time, of course, the semiconductor chip 12 and the sub-substrate 11 are die-bonded using a good conductive bonding method such as an AP paste method, a eutectic method, or a solder method. Furthermore, although the material of the sub-board 11 is a steel plate, the surface of the sub-board 11 is made of Au.
plating.

Ａｒメッキ、　Ｓｎメッキなど表面処理を施すことによ
ってＶ／Ｉ　％性を向上させることもできる。The V/I % property can also be improved by performing surface treatment such as Ar plating or Sn plating.

なお、プローブカード１７は、基板１８に複数の針状の
探触子１９（半導体チップ１２上の電極やサブ基板１１
に接触する）を設けて構成されている。Note that the probe card 17 has a plurality of needle-like probes 19 (electrodes on the semiconductor chip 12 and the sub-board 11 on the substrate 18).
(contact).

（発明の効果） 以上詳細に説明したように、この発明の実装法では、ダ
イスビンディングに関しては金属板からなるサブ基板を
用い、ワイヤーボンディングに関しては直接行うもので
、したがって、次のような効果を有する。(Effects of the Invention) As explained in detail above, in the mounting method of the present invention, die binding is performed using a sub-board made of a metal plate, and wire bonding is performed directly. Therefore, the following effects can be achieved. have

■　メイン基板に対するダイスメンディングミスや不良
半導体チップ混入時の改修や交換はサブ基板ごと行える
から、半導体チップの破片がメイン基板に残るなどのこ
とがなく、改修・交換時の合理化が図れる。特に、ＬＥ
ＤなどＧａ　Ａ＋ｓの半導体チップはもろい欠点がある
ため、この発明の方法は非常に有効である。■ When a die-mending error occurs on the main board or when a defective semiconductor chip is mixed in, repairs or replacements can be performed for each sub-board, so no semiconductor chip fragments remain on the main board, making repairs and replacements more efficient. In particular, L.E.
Since Ga A+s semiconductor chips such as D have the disadvantage of being brittle, the method of the present invention is very effective.

■　サブ基板は、半導体チップをダイスボンディングす
るだけであるから、半導体チップとほぼ同一面積の小さ
いものとすることができ、その結果として簡易チップキ
ャリア法と比較して実装スペースが小さく、高密度実装
が可能である。また、ワイヤーボンディングは一度で済
み、安価になる。■ Since the sub-board is simply die-bonded to the semiconductor chip, it can be made small and have almost the same area as the semiconductor chip.As a result, compared to the simple chip carrier method, the mounting space is smaller and high-density mounting is possible. is possible. Additionally, wire bonding only needs to be done once, making it cheaper.

■　半導体チップをサブ基板にダイスビンディングした
状態で、チップ特性選別ができる。■ Chip characteristics can be selected while semiconductor chips are die-bound to a sub-board.

特に裏面にグランド（ＧＮＤ　）を有する半導体チップ
は、サブ基板と、導電性のある接着とすることによって
Ｖ／Ｉ特性を正確に測定できる。In particular, the V/I characteristics of a semiconductor chip having a ground (GND) on its back surface can be measured accurately by adhering it to a sub-substrate with conductivity.

【図面の簡単な説明】[Brief explanation of drawings]

（図面） 第１図はこの発明の半導体チップの実装法を示す断面図
、第２図および第３図は従来の半導体チップの実装法を
各々示す断面図、第４図はこの発明の実装法において途
中で特性選別を行う方法を説明するための図である。 １１・・・サブ基板、１２・・・半導体チップ、１３・
・・メイン基板、１４・・・マウント部、１５・・・導
体、１６・・・ワイヤ。 第４図 −りり７(Drawings) Figure 1 is a cross-sectional view showing the semiconductor chip mounting method of the present invention, Figures 2 and 3 are cross-sectional views each showing the conventional semiconductor chip mounting method, and Figure 4 is the mounting method of the present invention. FIG. 4 is a diagram for explaining a method of performing characteristic selection midway through. 11... Sub board, 12... Semiconductor chip, 13.
...Main board, 14...Mount part, 15...Conductor, 16...Wire. Figure 4 - Riri 7

Claims (1)

【特許請求の範囲】 （ａ）半導体チップを金属板からなるサブ基板にダイス
ボンデイングした後、 （ｂ）そのサブ基板をメイン基板にダイスボンディング
し、 （ｃ）さらに、そのメイン基板上の導体に前記半導体チ
ップの電極をワイヤーボンディングすることを特徴とす
る半導体チップの実装法。[Claims] (a) After die-bonding a semiconductor chip to a sub-board made of a metal plate, (b) die-bonding the sub-board to a main board, and (c) further bonding the semiconductor chip to a conductor on the main board. A method for mounting a semiconductor chip, comprising wire bonding electrodes of the semiconductor chip.
JP60101615A 1985-05-15 1985-05-15 Packing method for semiconductor chip Pending JPS61260646A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60101615A JPS61260646A (en) 1985-05-15 1985-05-15 Packing method for semiconductor chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60101615A JPS61260646A (en) 1985-05-15 1985-05-15 Packing method for semiconductor chip

Publications (1)

Publication Number Publication Date
JPS61260646A true JPS61260646A (en) 1986-11-18

Family

ID=14305307

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60101615A Pending JPS61260646A (en) 1985-05-15 1985-05-15 Packing method for semiconductor chip

Country Status (1)

Country Link
JP (1) JPS61260646A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63115706A (en) * 1986-11-04 1988-05-20 株式会社大林組 Method of charging admixture for concrete

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63115706A (en) * 1986-11-04 1988-05-20 株式会社大林組 Method of charging admixture for concrete

Similar Documents

Publication Publication Date Title
US6630372B2 (en) Method for routing die interconnections using intermediate connection elements secured to the die face
CA1304170C (en) Highly integrated circuit and method for the production thereof
US6249041B1 (en) IC chip package with directly connected leads
US6433424B1 (en) Semiconductor device package and lead frame with die overhanging lead frame pad
JPH05109802A (en) Semiconductor device
US6531761B1 (en) High density direct connect LOC assembly
US4067041A (en) Semiconductor device package and method of making same
US5075252A (en) Interdigitated trans-die lead method of construction for maximizing population density of chip-on-board construction
JP2003258180A (en) Method of manufacturing semiconductor device
JPS61260646A (en) Packing method for semiconductor chip
JP2000183218A (en) Manufacture of ic package
JP3311867B2 (en) Ball grid array type semiconductor device and manufacturing method thereof
JPH09199374A (en) Thin film capacitor, package for semiconductor device mounted the capacitor, and the semiconductor device
KR100209592B1 (en) Semiconductor package
JPH01208844A (en) Semiconductor device
JP2990120B2 (en) Semiconductor device
JP2822446B2 (en) Hybrid integrated circuit device
JP2002373953A (en) Method for manufacturing hermetically sealed ic package
JPH09252020A (en) Semiconductor device and method for manufacturing the same
JPH03101136A (en) Mounting structure of semiconductor chip
JPH0786486A (en) Lead frame and resin-sealed semiconductor device using it
JPH06333981A (en) Fet chip mounting device
JPS62271443A (en) Semiconductor device
JPH06314720A (en) Semiconductor mounting substrate
JPS61260645A (en) Packaging method for semiconductor chip