JPS61259349A - Memory access system - Google Patents

Abstract

PURPOSE:To write a bit which is desired to be rewritten and to settle a memory access only one time by providing a means to enable respectively independently plural memory chips to constitute the memory. CONSTITUTION:A processor 20 sends an address AD through a multiplexer 41 to a memory 21, and reading/writing signal R/W through a multiplexer 43 to the memory 21. A multiplexer 44, for example, supplies 1 to a chip enable BS of the memory 21. In such a case, the processor 20 accesses the memory 21 by a word unit. A vector generating circuit 40 sends the address AD through the multiplexer 41 to the memory 21, the data DA through a multiplexer 42 to the memory 21, a signal R/W through the multiplexer 43 to the memory 21 and a chip enable signal BS through the multiplexer 44 to the memory 21. In such a case, the circuit 40 accesses the memory 21 at the bit unit.

Description

[Detailed Description of the Invention] [Summary] In a memory that is accessed in units of multiple bits, for example, words, the chip enable terminal of each memory chip is pulled out and this By independently controlling the chip enable, desired bits can be rewritten bit by bit.

[Industrial application field]

The present invention relates to a readable/writable memory, and particularly to a memory access method that allows access not only in word units but also in bit units.

With the spread of information processing devices, many devices have memory that can be randomly accessed and are controlled by processors (
It has come to be used. In these devices, a processor accesses the memory to read/write data, which is usually performed in units of words.

By the way, as the amount of data handled by devices increases,
There is a strong demand to improve the processing speed of processors, and it is desirable that the number of times the processor accesses the memory is small in order to execute a job.

[Conventional technology]

FIG. 5 is a block diagram illustrating a conventional memory access method.

For example, when the processor 20 accesses the memory 21 in word units and writes data, the processor 20 sends the address A to the address line.
D0-15 are sent out, data DA0-15 are sent out to the data line, and a write signal is sent out to the R/W (write/continuation) line.

Also, when reading data from memory 21, address AD0
-15, and sends a read signal to the R/W line to read data DA0-5.

[Problem that the invention seeks to solve]

As mentioned above, (conventionally, memory is accessed in word units, so if you want to rewrite a certain bit in a word, read that word once, rewrite only the bit you want to rewrite,
The rewritten word must be written to memory.

This is because the state of other bits other than the bit to be rewritten is unknown, so it is necessary to read in word units to know the state of the other unknown bits, so three accesses to the memory are required: reading and writing. There is a problem with becoming.

In view of these problems, the present invention aims to make it possible to write only the bit to be rewritten without affecting other unknown bits, and to access the memory only once.

Measures to solve problem C] FIG. 1 is a block diagram of the principle of the present invention.

In FIG. 1, a chip enable signal line is added to FIG. 5 so that a signal for individually enabling each memory chip can be supplied from the memory chips constituting the memory 21.
Chip enable signals BS0 to BS15 can be sent from the processor 20 to individual memory chips.

[Effect]

The processor 20 writes the bits to be rewritten into the memory 21
A signal is sent to the memory chip to enable that memory chip, and data is sent and rewritten. Since memory chips that store bits that are not to be rewritten are not enabled, there is no problem even if the state of the bits is unknown.

〔Example〕

FIG. 2 is a block diagram of a circuit showing one embodiment of the present invention.

For example, there are 16 memory chips 22 to 37, and each memory chip 22 to 37 is connected to 16 address lines 〇〇 to 15, respectively, and is supplied with an address. Therefore, this embodiment has a memory of 64 words.

A read or write signal is commonly supplied to each memory chip 22 to 37 by an R/W line, and a chip enable signal is supplied to the memory chips 22 to 37 by a chip enable signal line BSO.
Then, the memory chip 23 is activated by the chip enable line BS1.
Then, the memory chip 3 is activated by the chip enable line B515.
7, the data is sent to the memory chip 22 via the data line DAO, to the memory chip 23 via the data line DAI, and to the memory chip 23 via the data line DAI.
15 to the memory chips 37, respectively.

FIG. 3 is a diagram illustrating the operation of FIG. 2.

The data stored in a certain address of the memory chips 22 to 37, for example, the address specified by the address line AD15, that is, the data of bits 0 to 15, is shown in FIG. 3(a).
Assume that < 0011001100111100 as shown in .

When the processor rewrites bits 2 to 15 in this data, it sends an address to the address line AD15, and as shown in FIG.
For example, set “0” to S0 to S11 on the chip enable line B5.
For example, "1" is sent to 12 to 15 to enable memory chips 34 to 36 and a memory chip 37 (not shown).

Here, the processor can write pins 1-12 to 15 as 0011 by sending a write signal to the R/W line. Since the memory chips 22 and 23 and the memory chips 24 to 33 (not shown) are not enabled, the contents of bits 0 to 11 do not change, and are set to <00 as shown in FIG. 3(C).
11001100110011 and data rewriting is completed.

Although the above description has been about writing data, it is of course possible to read data from an enabled memory chip by sending a read signal to the R/W line.

FIG. 4 is a block diagram showing an example of application of the present invention.

The processor 20 receives the address A via the multiplexer 41.
D, data DA is sent to the memory 21 via a multiplexer 42, and read/write signal R/W is sent to the memory 21 via a multiplexer 43. Also, the multiplexer 44 is set to "1", for example.
is supplied to the chip enable BS of the memory 21. In this case, processor 20 accesses memory 21 in word units.

The vector generation circuit 40 receives the address AD through the multiplexer 41 and the data DA through the multiplexer 42.
The read/write signal R/W is sent through the multiplexer 43, and the chip enable signal BS is sent through the multiplexer 44.
is sent to /Mori 21. In this case, vector generation circuit 4
0 accesses the memory 21 bit by bit.

That is, the required memory chip is enabled by the chip enable signal BS, and the address AD is given to it.
It is possible to draw a line by writing data bit by bit.

As described above, by using the present invention, it is possible to easily connect a processor that accesses memory in word units and a vector generation circuit that accesses memory in bit units, reducing the number of times the vector generation circuit accesses the memory. I can do it.

〔Effect of the invention〕

As explained above, since the processor can rewrite data in the memory bit by bit, the present invention has the effect of reducing the number of accesses to the memory and enabling high-speed processing.

[Brief explanation of drawings]

Fig. 1 is a principle block diagram of the present invention, Fig. 2 is a block diagram of a circuit showing an embodiment of the present invention, Fig. 3 is a diagram explaining the operation of Fig. 2, and Fig. 4 is a diagram of the present invention. FIG. 5 is a block diagram illustrating an example of application of the method, and FIG. 5 is a diagram illustrating conventional memory access. In the figure, 20 is a processor, 21 is a memory, 22 to 37 are memory chips, 40 is a vector generation circuit, and 41 to 44 are multiplexers. η＼ departure" Month O storage floron 2 figure grass 1 n grass 2 mouths (CL) (b) Kisaitotomo Ka (to) evening + J Kinutsu blower 20th 4th mouth Conventional rho memory 12 cut slot 2゛Otsu Theory May J Rob'Ro゛7
22 years S mouth

Claims (1)

[Claims] In a memory (21) composed of a plurality of memory chips in which one bit is selected by one address, each of the plurality of memory chips constituting the memory (21) can be independently enabled. 1. A memory access method, comprising: means (BS0 to BS15) for accessing the bits of the memory chip enabled by the enabling means among the bits of each designated memory chip.