JPS61258416A - Manufacture of compound semiconductor device - Google Patents
Manufacture of compound semiconductor deviceInfo
- Publication number
- JPS61258416A JPS61258416A JP11076486A JP11076486A JPS61258416A JP S61258416 A JPS61258416 A JP S61258416A JP 11076486 A JP11076486 A JP 11076486A JP 11076486 A JP11076486 A JP 11076486A JP S61258416 A JPS61258416 A JP S61258416A
- Authority
- JP
- Japan
- Prior art keywords
- compound semiconductor
- heat treatment
- arsine
- gas
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 150000001875 compounds Chemical class 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000010438 heat treatment Methods 0.000 claims abstract description 20
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 claims abstract description 15
- 238000005468 ion implantation Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 9
- 239000007789 gas Substances 0.000 abstract description 11
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 10
- 238000009792 diffusion process Methods 0.000 abstract description 9
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 abstract description 6
- 239000012159 carrier gas Substances 0.000 abstract description 6
- 230000007547 defect Effects 0.000 abstract description 5
- 239000012535 impurity Substances 0.000 abstract description 4
- 239000001257 hydrogen Substances 0.000 abstract description 3
- 229910052739 hydrogen Inorganic materials 0.000 abstract description 3
- 150000002500 ions Chemical class 0.000 abstract description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract 1
- 229910000070 arsenic hydride Inorganic materials 0.000 abstract 1
- 229910052593 corundum Inorganic materials 0.000 abstract 1
- 229910001845 yogo sapphire Inorganic materials 0.000 abstract 1
- 239000013078 crystal Substances 0.000 description 7
- 230000008020 evaporation Effects 0.000 description 4
- 238000001704 evaporation Methods 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 150000002431 hydrogen Chemical class 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- 101100215641 Aeromonas salmonicida ash3 gene Proteins 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
Landscapes
- Physics & Mathematics (AREA)
- High Energy & Nuclear Physics (AREA)
- Engineering & Computer Science (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はＡｓを含有する化合物半導体を用いた化合物半
導体装置の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a compound semiconductor device using a compound semiconductor containing As.
イオン打込み技術は、制御性の極めて高い不純物ドープ
方法として半導体デバイス製作に欠かせない技術である
が、打込みイオンのエネルギーによって半導体結晶に欠
陥が導入されるためその回復のために打込み後の熱処理
が必要である。特に化合物半導体の場合には、一般に構
成元素のうち少くとも一つが蒸気圧が高く、高温の熱処
理によってその元素の空格子点が多量に発生しデバイス
として用いることができなくなる。従来は、Ｓｉ３Ｎ４
，５Ｌ０２などを保護膜として熱処理を行なっていたが
、保護膜からの不純物の拡散、逆に膜への成分元素の拡
散、あるいは熱膨張係数の違いによりクラックが入るな
どの問題がある。又、熱処理雰囲気に成分元素を加えて
その元素の蒸発を抑え、結晶には特に保護膜を被着せず
に熱処理を行なうなどの提案がある。しかしＡ ｓ Ｈ
３ガスとキャリアガスとの制御方法で結晶表面の変質が
性の良好な化合物半導体装置を製造できる化合物半導体
装置の製造方法を提供することにある。Ion implantation is an extremely controllable impurity doping method that is indispensable for the production of semiconductor devices, but the energy of the implanted ions introduces defects into the semiconductor crystal, so post-implant heat treatment is required to recover them. is necessary. Particularly in the case of compound semiconductors, at least one of the constituent elements generally has a high vapor pressure, and high-temperature heat treatment generates a large amount of vacancies in that element, making it impossible to use it as a device. Conventionally, Si3N4
, 5L02, etc., as a protective film, but there are problems such as cracks occurring due to diffusion of impurities from the protective film, diffusion of component elements into the film, or differences in thermal expansion coefficients. There are also proposals to add component elements to the heat treatment atmosphere to suppress evaporation of the elements, and to perform heat treatment without specifically covering the crystal with a protective film. But A s H
An object of the present invention is to provide a method for manufacturing a compound semiconductor device, which can manufacture a compound semiconductor device with good quality change on the crystal surface by controlling three gases and a carrier gas.
上記目的を達成するための本発明の構成は、イオン打込
みののちにアルシン（ＡｓＨ３）ガスが０．０４〜０．
２容量パーセントの雰囲気中で８００〜８５０℃の熱処
理を行なって所定の導電領域を設けて化合物半導体装置
を構成することにある。The configuration of the present invention for achieving the above object is such that after ion implantation, arsine (AsH3) gas is injected in the range of 0.04 to 0.0.
A compound semiconductor device is constructed by performing heat treatment at 800 to 850° C. in an atmosphere of 2% by volume to provide a predetermined conductive region.
本発明は上記構成になるので、ＧａＡｓなどのＡｓを含
有する化合物半導体基板もしくは半導体層にイオン打込
みを行なったのちの上記所定の温度で熱処理を行なうと
Ａ Ｂ Ｈｚから分離したＡｓ蒸気圧と結晶層からのＡ
ｓの蒸気圧とが相等しくなり、結局、結晶表面からのＡ
ｓの蒸発が抑えられる。Since the present invention has the above configuration, when heat treatment is performed at the above predetermined temperature after ion implantation into a compound semiconductor substrate or semiconductor layer containing As such as GaAs, the As vapor pressure and crystal separated from A B Hz are A from layer
The vapor pressure of s becomes equal to that of A
Evaporation of s is suppressed.
実験によれば、半絶縁性ＧａＡｓ結晶の電気的特性は８
００℃３０分の熱処理に対しては水素キャリアガス中に
０．０４％以上、８５０℃３０分の熱処理に対しては０
．１％以上のＡ Ｂ Ｈ３ガスを加えれば全く変化しな
いことがわかった。これは明らかにＡｓの蒸発によりで
きたＡｓ空孔が電気的に悪影響を及ぼしていたものが、
ＡｓＨ３の導入により抑えられることを意味する。一方
、熱処理した結晶の表面状態はＡ ８ Ｈ３が不足の場
合には表面からのＡｓの蒸発により（１００）面に対し
ては四角形のピットが見られる。またＡ ｓ Ｈ３が過
剰の場合にもＧ ａ Ａ ｓ表面には細かい波状のパタ
ーンが見られ微細加工のために不都合である。従来Ａｓ
Ｈ３に適正な分圧範囲があることは知られていなかった
。とくに、この傾向は特に高温での熱処理において著し
い。８００℃３０分の熱処理に対して特に好ましいＡ
ｓ Ｈ３濃度は０．０４％以上、０．５％以下、８２５
℃３０分では０．０７％以上０．３５％以下、８５０℃
３０分では０．１％以上０．２％以下である。他の温度
に関しては、上記の値を内挿し目安とすれば十分である
。また、熱処理時間は通常５〜６０分行なわれるが、こ
の時間内では上記ＡｓＨ３濃度が適用される。以下、実
施例を用いて詳細に説明する。According to experiments, the electrical properties of semi-insulating GaAs crystals are 8
0.04% or more in hydrogen carrier gas for heat treatment at 00°C for 30 minutes, and 0.04% for heat treatment at 850°C for 30 minutes.
．． It was found that there was no change at all if 1% or more of A B H3 gas was added. This is clearly because the As vacancies created by the evaporation of As were having an adverse electrical effect.
This means that it can be suppressed by introducing AsH3. On the other hand, when the surface of the heat-treated crystal is insufficient in A 8 H3, rectangular pits are observed on the (100) plane due to the evaporation of As from the surface. Furthermore, when As H3 is excessive, a fine wavy pattern is observed on the Ga As surface, which is inconvenient for microfabrication. Conventional As
It was not known that H3 had a proper partial pressure range. This tendency is particularly remarkable in heat treatment at high temperatures. Particularly preferred A for heat treatment at 800°C for 30 minutes
s H3 concentration is 0.04% or more and 0.5% or less, 825
0.07% or more and 0.35% or less in 30 minutes at 850°C
In 30 minutes, it is 0.1% or more and 0.2% or less. For other temperatures, it is sufficient to interpolate the above values and use them as a guide. Further, the heat treatment time is usually 5 to 60 minutes, and the above AsH3 concentration is applied within this time. Hereinafter, it will be explained in detail using examples.
（１００）面を上面に持つｎ型Ｇ ａ Ａ ｓ基板（電
子濃度ｎｚｌｏ’ ”／ｃｄ）１面上に次の各層をスラ
イドボードを用いた周知の液相エピタキシャル法によっ
て形成する。The following layers are formed on one surface of an n-type GaAs substrate (electron concentration nzlo'''/cd) having the (100) plane on the upper surface by a well-known liquid phase epitaxial method using a slide board.
第１の半導体層２はｎ型Ｇａ、ｘＡＱＡＢ（Ｘ ；０．
２５〜０．３５）層（ｎｚ５ Ｘ １０ ” ／ａＪ）
を厚さ０．５〜２．５μｍにする。ついで、第２の半導
体層３はｎ型Ｇ ａ Ａ ｓ層（ｎｚｌ Ｏ” ／ａｄ
）を厚さ０．０５〜０．１５μｍにする。ついで、第３
の半導体層４はｐ型Ｇａ １− Ｘ Ａ Ｑ Ａｓ （
ｘ ；０．２５〜０．３５）層（正孔濃度ｐｚ５Ｘ１０
”／ｃｄ）を厚さ０．５〜１．５μｍにする。ついで第
４の半導体層５はｐ型Ｇａ １ ＋ Ｘ Ａ Ｑ Ａ８
（Ｘ ；０．２５〜０．３５）層（ｐ＝１ ｘ １０
” ／ａｌ、比抵抗〜６００Ω・３）を厚さ０ 、５
〜１ 、５ μｍにする。ついで第５の半導体層６はｎ
型Ｇ ａ Ａ ｇ（ｎｚ２ Ｘ １０ ” ／ａ＃）
を厚さ０．２〜０．４μｍにする。The first semiconductor layer 2 is made of n-type Ga, xAQAB(X;0.
25~0.35) layer (nz5 x 10''/aJ)
to a thickness of 0.5 to 2.5 μm. Next, the second semiconductor layer 3 is an n-type GaAs layer (nzlO"/ad
) to a thickness of 0.05 to 0.15 μm. Then, the third
The semiconductor layer 4 is made of p-type Ga 1-
x; 0.25 to 0.35) layer (hole concentration pz5X10
”/cd) to a thickness of 0.5 to 1.5 μm.Then, the fourth semiconductor layer 5 is made of p-type Ga 1 + X A Q A8
(X; 0.25-0.35) layer (p=1 x 10
”/al, specific resistance ~600Ω・3) with thickness 0,5
~1.5 μm. Then, the fifth semiconductor layer 6 is n
Type G a A g (nz2 X 10”/a#)
to a thickness of 0.2 to 0.4 μm.
次いで、厚さ０．２μｍのＡＱ２０３、および厚さ０．
３μｍの５ｉ０２の二層の絶縁膜を周知のＣＶＤ （Ｃ
ｈｓｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ）
法で形成する。上記二層の絶縁膜あ半導体レーザー素子
の電極取出し部に対応する部分を幅６μｍに開孔する０
食刻液は弗化水素と弗化アンモニウム混合液（１： ６
）を５ｉ０２用に、そしてリン酸をＡＱ２０３用に用い
た。コノＳｉＯ２−Ａ Ｑ ２０３二層膜が選択拡散用
マスクとなる。この開孔を通して周知のイオン打込み技
術によりＺｎを幅６μｍで拡散する。この打込みによる
不純物拡散層は後述の熱処理によって最終的に層４に到
達する。Next, AQ203 with a thickness of 0.2 μm and a layer with a thickness of 0.2 μm.
A two-layer insulating film of 5i02 with a thickness of 3 μm was deposited by well-known CVD (C
hsmical Vapor Deposition)
form by law. A hole with a width of 6 μm is made in the part of the two-layer insulating film corresponding to the electrode extraction part of the semiconductor laser element.
The etching solution is a mixture of hydrogen fluoride and ammonium fluoride (1:6
) was used for 5i02 and phosphoric acid for AQ203. The Kono SiO2-A Q203 two-layer film serves as a mask for selective diffusion. Through this opening, Zn is diffused in a width of 6 μm using a well-known ion implantation technique. The impurity diffusion layer formed by this implantation finally reaches layer 4 through heat treatment described below.
なお、イオン打込みの条件は８０〜１００ ＫｅＶでド
ープ量を５Ｘ１０１２／ａＪとし既そ１分間行なう、こ
のとき、約０．１５μｍの深さまでＺｎの高濃度領域が
デポジットされる。The ion implantation conditions are 80 to 100 KeV and a doping amount of 5.times.10@12 /aJ for about 1 minute. At this time, a high concentration region of Zn is deposited to a depth of about 0.15 .mu.m.
次いで、キャリアガスとして水素（Ｈ２）が５００ｃｃ
／ｍｉｎ、アルシン（ＡＳＨ３）ガスが０．２ｃ、ｃ／
ｍｉｎの８００℃雰囲気中で上述の化合物半導体層を半
導体結晶基板１を既そ３０分間熱処理を行なう。この熱
処理工程により、Ｇ ａ Ａ ｓ等の化合物半導体にお
けるＡｓは、上記アルシンガスのＡｓの蒸気圧とほぼ対
等となるため、上記ＧａＡｓ中のＡｓは基板１および各
半導体層から遊離もしくは分解して空孔が発生するのを
抑えられることとなる。Next, 500 cc of hydrogen (H2) was added as a carrier gas.
/min, arsine (ASH3) gas is 0.2c, c/min
The above-described compound semiconductor layer and semiconductor crystal substrate 1 are heat-treated in an atmosphere of 800° C. for 30 minutes. Through this heat treatment step, As in the compound semiconductor such as GaAs becomes almost equal to the vapor pressure of As in the arsine gas, so that As in the GaAs is liberated or decomposed from the substrate 1 and each semiconductor layer and becomes empty. This will prevent the formation of holes.
上記アルシンガスは、水素ガス５００ｃｃ／ｌｌ１ｎ゛
に対してｌｃｃ／ｍｉｎまでが最も良好で、半導体層
に欠陥および歪などが導入されることが無かった。また
、水素ガスを１００〜５０００ｃｃ／ｎ＋ｉｎまで変化
させ、それぞれアルシンガスの流量を変化させて試作を
試みた処、アルシンガス流量が水素ガスに対して０．０
４〜０．２容量％が最も良好であった。さらに又、雰囲
気温度を７５０〜９００℃まで変えて試作を試みても同
じように適用ができたが８００〜８５０℃が最も良好で
あった。この温度範囲では、ＡｓＨ３の不足に基づくピ
ットの発生、およびＡｓＨ３の過剰に基づく表面の荒れ
なども全く見られなかった。The arsine gas was best at a rate of up to lcc/min with respect to hydrogen gas of 500cc/ll1n, and no defects or strains were introduced into the semiconductor layer. In addition, when we attempted to produce a prototype by varying the hydrogen gas from 100 to 5000 cc/n+in and changing the arsine gas flow rate, we found that the arsine gas flow rate was 0.0 compared to the hydrogen gas.
4 to 0.2% by volume was the best. Furthermore, even when trial production was attempted by changing the ambient temperature from 750 to 900°C, the same application was achieved, but 800 to 850°C was the best. In this temperature range, neither the occurrence of pits due to a lack of AsH3 nor the surface roughness due to an excess of AsH3 was observed.
この熱処理工程により、上述のイオン打込みによるＺｎ
のデポジット層がおよぞ数μの深さまで拡散しｐ型頭域
１３を形成する。この領域は電流を容易に流し易くする
ためもので第３半導体層４の中途まで拡散層が延びてい
る必要がある。しかし、第２半導体層３に到達して該層
３の活性効率を低下せしめないように予じめ温度、時間
、ドープ量などを調節されであることは勿論である。Through this heat treatment step, the Zn
The deposit layer diffuses to a depth of approximately several microns to form a p-type head region 13. This region is intended to facilitate the flow of current, and the diffusion layer must extend to the middle of the third semiconductor layer 4. However, it goes without saying that the temperature, time, doping amount, etc. should be adjusted in advance so as not to reach the second semiconductor layer 3 and reduce the activity efficiency of the layer 3.
上記熱処理を行なう際の装置の様子を第２図に示す。キ
ャリアガスとアルシンは予じめ流量比により分圧されて
所定の値に希釈されたのち、炉体２１中の反応管２２内
に流入される。２３は化合物半導体基板、２４は上記基
板を保持する治具である。FIG. 2 shows the state of the apparatus when performing the above heat treatment. The carrier gas and arsine are partially pressured and diluted to a predetermined value by a flow rate ratio in advance, and then flowed into the reaction tube 22 in the furnace body 21. 23 is a compound semiconductor substrate, and 24 is a jig for holding the substrate.
次いで上述の選択拡散用マスクを除去したのち、第１の
半導体層２に達する溝７を形成する。上記ｐ型領域１３
上、および上記基板１真面に半導体レーザー用の金属電
極を形成する。上記溝７で隔絶された他方の半導体層６
上にソース、ドレインおよびゲート電極９，１１および
１ｏを形成する。Next, after removing the above-described selective diffusion mask, a groove 7 reaching the first semiconductor layer 2 is formed. Said p-type region 13
A metal electrode for a semiconductor laser is formed on the top and directly on the substrate 1. The other semiconductor layer 6 separated by the groove 7
Source, drain and gate electrodes 9, 11 and 1o are formed thereon.
所定の配線を行なって、半導体レーザー素子と電界効果
トランジスタを結合させた化合物半導体装置が構成され
る。By performing predetermined wiring, a compound semiconductor device in which a semiconductor laser element and a field effect transistor are combined is constructed.
この発光素子はドレイン電極１１とレーザー素子のｎ側
電極１２の間に４〜５ｖの電圧を印加することにより、
レーザー発振を行なわしめることができる。発振波長８
３００人、しきい電流は約３０〜８０ｍＡであった。こ
のように、半導体層４．５および６にイオン打込みによ
っても欠陥もしくは歪、外見上の不整合が生じないので
、しきい値電流の低い、良好な電気的特性の化合物半導
体装置が形成できた。This light emitting element can be manufactured by applying a voltage of 4 to 5 V between the drain electrode 11 and the n-side electrode 12 of the laser element.
Laser oscillation can be performed. Laser wavelength 8
300 people, the threshold current was about 30-80 mA. In this way, no defects, distortions, or apparent mismatches are caused by ion implantation in the semiconductor layers 4.5 and 6, so a compound semiconductor device with low threshold current and good electrical characteristics can be formed. .
本発明の実施例では、レーザー素子の電極用導電層の拡
散層について述べたが、これに限らず、イオン打込み後
にアニールが必要な工程に広く適用できる。また、アニ
ールのキャリアガスとしてもＮ２の他。にＮ２．Ａｒな
どの不活性ガスも適用できる。さらにまた、イオン打込
みの元素もＺｎに限らすＳｎ、Ｃｕ、Ｓｉ、Ｐなど導電
型あるいは用途により適宜選択されたものであっても適
用できる。さらにまた、基板がＧａＡｓに限らず、Ｉｎ
ＧａＡｓＰ、ＧａＡＱＡｓ、ＧａＡｓＰなど一般にＡｓ
を含んだ化合物半導体に同様の趣旨が適用できることは
当業者であれば容易に推察できるであろう。In the embodiments of the present invention, a diffusion layer of a conductive layer for an electrode of a laser element has been described, but the present invention is not limited to this and can be widely applied to processes that require annealing after ion implantation. In addition to N2, it is also used as a carrier gas for annealing. N2. Inert gas such as Ar can also be applied. Furthermore, the element for ion implantation is not limited to Zn, but may be appropriately selected depending on the conductivity type or purpose, such as Sn, Cu, Si, or P. Furthermore, the substrate is not limited to GaAs.
Generally As, such as GaAsP, GaAQAs, and GaAsP
Those skilled in the art will easily infer that the same gist can be applied to compound semiconductors containing.
以上詳述したように１本発明は、化合物半導体層にイオ
ン打込みを行なった後、所定の雰囲気中で所定の分圧の
アルシンの熱処理を行なうことにより、欠陥等のない良
好な化合物半導体装置を得ることができるもので工業的
利益大なるものである。As detailed above, one aspect of the present invention is to implant ions into a compound semiconductor layer and then heat-treat the compound semiconductor layer with arsine at a predetermined partial pressure in a predetermined atmosphere, thereby producing a good compound semiconductor device free of defects. The amount that can be obtained is of great industrial benefit.
第１図は本発明の一実施例における化合物半導体装置の
概略断面図、第２図は本発明を実施するために用いた装
置の概略説明図である。
１・・・化合物半導体基板（ＧａＡｓ） 、２〜６・・
・化合物半導体層、１３・・・イオン打込み拡散領域、
８〜１２・・・電極、７・・・溝。
÷２ 図FIG. 1 is a schematic sectional view of a compound semiconductor device according to an embodiment of the present invention, and FIG. 2 is a schematic explanatory diagram of a device used to carry out the present invention. 1... Compound semiconductor substrate (GaAs), 2-6...
- Compound semiconductor layer, 13... ion implantation diffusion region,
8-12...electrode, 7...groove. ÷2 figure
Claims (1)
層にイオン打込みにより導電領域を形成する化合物半導
体装置の製造方法において、上記導電領域はイオン打込
みの後に、８００〜８５０℃の０．０４〜０．２容量パ
ーセントのアルシンを含んだガス雰囲気中の熱処理によ
り形成されることを特徴とする化合物半導体装置の製造
方法。1. In a method for manufacturing a compound semiconductor device in which a conductive region is formed by ion implantation in a compound semiconductor substrate or a compound semiconductor layer containing As, the conductive region is heated at 800 to 850° C. by 0.04 to 0.0° C. after ion implantation. 1. A method for manufacturing a compound semiconductor device, characterized in that the device is formed by heat treatment in a gas atmosphere containing 2% by volume of arsine.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11076486A JPS61258416A (en) | 1986-05-16 | 1986-05-16 | Manufacture of compound semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11076486A JPS61258416A (en) | 1986-05-16 | 1986-05-16 | Manufacture of compound semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61258416A true JPS61258416A (en) | 1986-11-15 |
Family
ID=14543978
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11076486A Pending JPS61258416A (en) | 1986-05-16 | 1986-05-16 | Manufacture of compound semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61258416A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63160327A (en) * | 1986-12-24 | 1988-07-04 | Mitsubishi Monsanto Chem Co | Annealing system for semiconductor wafer |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5678120A (en) * | 1979-11-30 | 1981-06-26 | Fujitsu Ltd | Manufacture of compound semiconductor device |
-
1986
- 1986-05-16 JP JP11076486A patent/JPS61258416A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5678120A (en) * | 1979-11-30 | 1981-06-26 | Fujitsu Ltd | Manufacture of compound semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63160327A (en) * | 1986-12-24 | 1988-07-04 | Mitsubishi Monsanto Chem Co | Annealing system for semiconductor wafer |
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