JPS61256464A - Method for controlling shared memory - Google Patents

Abstract

PURPOSE:To make an efficient access by monitoring a memory use request state from respective access sources, detecting the largest priority to perform a memory access, and removing only the memory use request produced in its access source. CONSTITUTION:When request signals REQ1-REQ4 are generated from respective interface circuits 4-7, the request signal is set to a request detecting FF 803 through an OR gate 801 synchronously with a clock from an oscillation circuit 802. Then, the clock is inputted to a timing generating circuit 805 through an AND gate 804 and timing signals A-D are formed. In a register 806, all the states of the signals REQ1-REQ4 are stored. By the signal B, any one of the outputs of a priority discriminating circuit 807 is selected. The outputs of the circuit 807 are obtained as control signal GATEs by the circuits 4-7 and logically multiplied by a signal D in AND gates 812-815 to obtain a control signal RESET. In this manner, an efficient access can be performed.

Description

Detailed Description of the Invention [Field of Application of the Invention] The present invention relates to a shared memory control method when a plurality of processor units or data transmitting/receiving units access a shared memory. The present invention relates to a shared memory control method for accessing shared memory.

[Background of the invention]

As a conventional shared memory control method, for example, one disclosed in Japanese Patent Application Laid-Open No. 58-29060 is known. In this case, a latch circuit for temporarily storing data is provided in the individual interface circuit, and memory use request signals are sequentially detected at predetermined regular intervals. However, it does not take into account the quick response when the number of processors using the shared memory increases, or the point of sharing with a device that transmits several words at high speed, such as a transmission device. In general, when multiple access sources share memory, the access sources can be assigned a priority order of access in advance, and the access sources can also be It is necessary to efficiently access the shared memory depending on the number of sources.

[Purpose of the invention]

An object of the present invention is to provide a shared memory control method that allows each of the access sources to access the shared memory most efficiently when a plurality of access sources with different priorities and access modes share the memory. It is in.

[Summary of the invention]

For this purpose, the present invention assumes that each access source issues a memory use request every time the need for memory access arises, and when there is a memory use request from any of these access sources, the memory use request is made at that time. Detects the access source with the highest priority among the access sources issuing the request, and after the memory access from the access source with the highest priority is executed, only the memory use requests issued by that access source are processed. It was designed to be canceled.

[Embodiments of the invention]

The present invention will be explained below with reference to FIGS. 1 to 6. First, a processing device according to the present invention having a shared memory will be explained. FIG. 2 shows the overall configuration of one example, and this example functions as one terminal in a processing system. This means that data can be exchanged with other terminals.

Now, according to this, the processor l that performs arithmetic processing can exchange data with other devices via the data bus To, while the data exchange with the shared memory 9 is carried out by the write interface circuit 4. and the subsequent interface circuit 5. Also,
The transmission and reception circuit 2 exchanges data with the shared memory 9 via a reception interface circuit 6, and the transmission and transmission circuit 3 via a transmission interface circuit 7. Data exchange between each of the interface circuits 4 to 7 and the shared memory 9 is executed under timing control by the shared memory control circuit 8.

The transmission and reception circuit 2 exchanges data with an external processing device (not shown) through a transmission path Tm, and the transmission and transmission circuit 3 through a transmission path Ts.

Next, the write interface circuit and the like will be explained in order. FIG. 3(a) shows the configuration of an example thereof. As shown in the figure, the signal W/R is set in the request signal flip-flop 401 by the data request signal SII from the processor 1, but when the signal W/EL is 11'', writing is disabled.

@0# indicates a continuous request. Therefore, when "1#" is set, the memory use request signal aE
Ql is output from the 7 lip-flop 401,
Depending on the rising edge of the address storage circuit 402. Address 8A1 and data 8o from processor 1 are set in data storage circuit 403, respectively. After this, since it is possible to separate the operation from the processor 1, the data request signal S1 and the memory use request signal aE
The data request signal 5lt- is transferred to the processor 1.
This is where it will fall. Now.

When the memory use request signal E4=E Qt is accepted by the shared memory control circuit 8, two types of timing signals are sent to the write interface circuit 4 as a response signal ANS1.

Among these, the control signal GATE outputs each data in the address storage circuit 402 and the data storage circuit 403 onto the address bus Sms and the data bus Sa, and transfers it to the shared memory 9. In addition, the control signal aEs
ET is output at time 9 after data writing to the shared memory 9 is completed, and as a result, the memory use request signal 7 lip 401 is reset. When a request to write data is issued to processor l, the above operation is repeated for each data unit.

FIG. 3(b) shows the configuration of an example of the successive interface circuit. The data request signal Sm from the processor 1 sets the signal W/R via the inverter 505 in the memory use request signal 7 lip-flop 501.

A memory use request signal RE is sent from the flip-flop 501.
Q2 is now output. When the request signals R and EQ are accepted by the shared memory control circuit 8, three types of trimming signals are sent to the successive interface circuit 5 as a response signal ANS2. Among these, the control signal GATE is the gate circuit 502t- Open is processor l
address S, from address bus 8. To output to
It was. The control signal LATCH functions to latch data from the shared memory 9 via the data bus S4 into the data storage circuit 503. The remaining control signals R and ESET are also output when the latching to the data storage circuit 503 is completed, thereby resetting the memory use request signal flip-flop 501. After this reset, the request signal flip-flop 50
The reset output of 1 is output from the AND gate 504 as the interface section end signal SQ together with the data request signal Sm and the inverted signal W/&, and is then sent back to the processor 1. At the same time, the data in the data storage circuit 503 is outputted to the data bus 8oK by the termination signal 8Q, and the processor 1 which has received the termination signal SQ takes in the data from the data bus So.

FIG. 4(a) shows the configuration of an example of the reception interface circuit. In the case of a transmission device, unlike the data exchange with the processor 1, it is common to exchange data in several words in succession, and it is necessary to have a configuration and function suitable for the purpose.

According to this, data is output from the transmission reception circuit 2 to the reception interface circuit 6 via the data bus So at the same time as the data request signal Sml, but the delay circuit 6
The data determined by the data request signal Sm sent through 01 is set in the data storage circuit 505. When the transmission/reception circuit 2 receives the end signal 8Q, which is the delayed data request signal, it drops the data request signal 8m, but if necessary, it outputs the data compensation signal Sl and the data again. By repeating such operations, several words of data are stored in the data storage circuit 6051C. In this case, the data storage circuit 605 has a capacity to store several words of data, and the subsequent data is output in the order in which they are written.

After the data is set as described above, the control signal 8cVC from the transmission/reception circuit 2 is sent to the register 602.
3 is set with control data from the data bus So. The contents of the data set are as shown in FIG. 5(a).

That is, data specifying an arbitrary area of the address in the shared memory 9 is set in the register 602, and the number of data to be transferred is set in the register 603. This results in Figure 5 (
As shown in b), the write address area in the shared memory 9 is specified. Incidentally, in this example, all addresses are 1
It is divided into 6 areas, each area consisting of 16 addresses, and 8 addresses are specified in the address area 3VC. Transfer data a″0″ indicates that the number of data is 1.

On the other hand, depending on the control signal BcVC, RI 87 lip 7
The 0 knob 610 is set, and gate control is performed by an ant game 611 based on the set output.

The clock from the oscillation circuit 608 is input to the flip-flop 609 for the first time.
09 is set. The output of this flip-flop 609 causes the counter 606 to count up by 1, and at the same time,
A memory use request signal FLEQ3 is sent to the shared memory control circuit 8.
K is set so that it is output as . This request signal R
When E Qs is received by the shared memory control circuit 8, two types of timing signals are sent to the reception interface circuit 6 as a response signal AN83, as in the case of the write interface circuit 4. It's been 60 years
6 is output as an address to the address bus S, while data from the data storage circuit 605 as a FIFO is output to the data bus 8-, with the data also serving as a successive clock. therefore,
The flip-flop 609 repeats the operation of being set immediately every time it is reset until all data in the data storage circuit 605 is written. The match detection circuit 604 compares the contents of the register 603 and the counter 606, and when they match, that is, when all the data has been transferred and stored, the transfer end signal 8 is output.
g to the transmission/reception circuit 2, while transmitting the transfer end signal Ss.
also resets the RS flip 70 knob 610, thus resetting the request signal flip flop 609.
is no longer set, and data transfer and storage to the shared memory 9 is completed.

4) shows the configuration of an example of the transmission interface circuit. This configuration is almost the same as that of the receiving interface circuit 2, but it is reversed as a VJ product. That is, first, the address area designation data and the number of transfer data are set in the registers 702 and 703 by the control signal Sc from the transmission circuit 3, and at the same time, the R and S flicks 70 and 710 are set by the control signal Sc. It has become. As a result, the request signal EQ4 is output from the memory use request signal flip-flop 709.
is output, but when this is received by the shared memory control circuit 8, three types of timing signals are obtained as the response signal AN84 in the same manner as in the case of the successive interface circuit 5. However, in this case, since the flip-flop 709 is set immediately every time it is reset as in the previous case, data from the shared memory 9 is sequentially transferred and stored in the data storage circuit 705. Eventually, the match detection circuit 704 detects that the contents of the counter 706 and the register 703 match, and the transfer end signal Ss is obtained as in the previous case. Upon receiving this transfer end signal Sg, the transmission/sending circuit 3 sequentially outputs the data request signal Sm for the first time, and the data determined by the delay circuit 701 can be received.

Finally, the shared memory control circuit according to the present invention will be explained. FIG. 1 shows an example of the configuration. As shown in the figure, when there is a request signal EQI to EQ4 from any of the interface circuits 4 to 7, the request signal is sent to the request detection flip-flop 803 via the 1 oscillation circuit 802. It is a trap so that it is set synchronously at the time of rising.

When the 7-lip prop 803 is set, the clock from the oscillation circuit 802 via the AND gate 804 is input to the timing generation circuit 805.

The timing generation circuit 805 is designed to generate various timing signals A to D at the timings shown in FIG. The generation timing is synchronized with the rising edge of the clock except for timing signal B obtained from the delay circuit 816.
The register 806 stores the states of all the request signals EL E Q r -a EQ4 according to the timing signal A.
Also, depending on the timing signal B, the priority determination circuit 807
One of the outputs is selected. The priority determination circuit 807 is for determining a request signal to be processed preferentially when two or more request signals are set at the same time. By the way, the control signal GAT mentioned above
E is output in synchronization with signal B, control signal LATCf (signal C, and control signal RESET are output in synchronization with signal RI).As shown in the figure, the output of priority determination circuit 807 is directly output to each interface circuit 4 to Control signal GA to 7
Obtained as TE.

Further, by logically multiplying each of the outputs and the timing signal by AND gates 812 to 815, a control signal ELE SET to each interface circuit 4 to 7 can be obtained. Further, the control signal LATCH required by the continuous interface circuit 5 and the transmission interface circuit 7 is supplied to the AND gates 810 and 81.
1, the AND gate 809 outputs a memory write signal Sv in synchronization with the timing signal C, and the timing signal B is also used as a memory selection signal 8 e a.

By making the oscillation period of the activation circuit in the transmitting/receiving interface circuit shown in FIGS. 4(a) and 4(b) K variable, the access period becomes variable and a configuration suitable for the required system speed becomes possible.

The shared memory control method according to the present invention has been described above, and when an arbitrary access source generates a memory use request signal, all the use request states are captured and processing related to the use request is executed according to a preset priority order. Therefore, requests can be responded to immediately.

In the conventional scanning method, when the cycle is T and the number of connected access sources is n, a maximum of nT waits are required. Considering the present invention, the maximum number of competing machines at the same time is two.

Therefore, nw8. If T = 2 μS, the difference in waiting time Δ
T becomes ΔT=-8X2-2X2-12μS. A memory access time of 2 μS or less is considered a large value in current systems. Furthermore, since zero-issue BAK allows high-speed processing of multiple data transfer requests, it is also possible to handle transfer requests from various access sources.

〔Effect of the invention〕

As explained above, according to the present invention, when a plurality of access sources with different priorities and access modes share memory, each of the access sources can access the shared memory most efficiently. There is.

[Brief explanation of the drawing]

1 is a diagram showing the configuration of an example of a shared memory control circuit according to the present invention; FIG. 2 is a diagram showing the overall configuration of an example of a processing device according to the present invention having a plurality of access sources; 3
Figures (a) and (b) are diagrams showing the configuration of an example of the write and successive interface circuits, respectively, and Figure 4 (
5(a) and 5(b) are diagrams respectively showing the configuration of an example of the reception and transmission interface circuits, and FIGS. 5(a) and 5(b) are diagrams showing the configuration of the registers in the transmission and reception interface circuits. A diagram for explaining a data setting format. FIG. 6 is a diagram showing the input/output deformation of the main part in FIG. 1. 1... Processor, 2... Transmission/reception circuit, 3...
Transmission sending circuit, 4...Writing interface circuit, 5
. . . successive interface circuits, 6 . . . interface circuit for reception, 7 . . . interface circuit for transmission. 8... Shared memory control circuit, 9... Shared memory. 401;・501,609,709,803...7 lipflop, 402,502,604,704...
Address storage circuit, 403, 503, 605゜705・
...Data storage circuit, 608,708°802...Excavation circuit, 602,803,702°703.806...
・Register, 606, 706...Counter, 604,
704... Match detection circuit, 805... Timing creation circuit, 807... Priority determination circuit. 607.707...Gate circuit.

Claims (1)

[Claims] 1. Monitor the status of memory use requests from each access source that issues a memory use request every time a memory access is needed for the shared memory, and if a memory use request is received from any of them, issue a memory use request at that time. After detecting the access source with the highest priority among the issuing access sources and executing memory access from the access source,
A shared memory control method characterized by dropping only memory use requests issued by the access source.