JP2567109B2 - Main memory data transfer control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Industrial field of application) The present invention relates to a bus interface between a first bus to which a main memory device is connected and a second bus which is an expansion bus of the same bus. Regarding the information processing system connected by the mechanism,
Particularly, the present invention relates to a main memory data transfer control method suitable for transferring read data from the main memory device to the second bus.

(Prior Art) Conventionally, as shown in FIG. 4, a bus (data transfer bus) 20 to which the main memory device 10 is connected and a bus (expansion bus) 30 to which the main memory device 10 is not connected are In the information processing system coupled by the interface mechanism 40,
Reading data from a device on the bus 30 such as the processor 50 to the main memory device 10 is performed by a bus interface mechanism.
Through 40, the procedure shown in the timing chart of FIG. 5 was executed as follows.

When data is read from the processor 50 to the main memory device 10, first, in a cycle TB1 of the bus 30, the processor 50 outputs a bus acquisition request signal Q1 for requesting acquisition of the bus 30.

When the bus 30 can be acquired by the output of the bus acquisition request signal Q1, the processor 50 in the next cycle TB2, the main memory access request signal Q2, the main memory address, and the function (address &
Read function) Q3 is output to the bus interface mechanism 40 via the bus 30.

When the bus interface mechanism 40 receives the main memory access request signal Q2 and the address & read function Q3 from the processor 50 in the cycle TB2, the cycle TA1 of the bus 20 (usually, the cycle of the bus cycle of the bus 20 is
Bus acquisition request signal Q1 to request acquisition of bus 20 at shorter than that of 30, ie bus 20 is faster)
Output 1

When the bus 20 can be acquired by the output of the bus acquisition request signal Q11, the bus interface mechanism 40 determines the next cycle T.
In A2, main memory access request signal Q12 and address (main memory address) & read function Q13
To the main memory device 10 via the bus 20.

When the main memory device 10 receives the main memory access request signal Q12 and the address & read function Q13 from the bus interface mechanism 40 in the cycle TA2, if the target main memory address is accessible,
From the next cycle TA3, a data read cycle for the memory cell array in the main memory device 10 is started. This data read cycle is TA3 to T in the example of FIG.
It is a 4-bus cycle of A6.

When the main memory device 10 completes the above data read cycle, it outputs the bus acquisition request signal Q14 for requesting acquisition of the bus 20 in the next cycle TA7.

The bus acquisition request signal Q14 from the main memory device 10 is set to have the highest priority for bus acquisition. Therefore,
The main memory device 10 can acquire the bus 20 in the next cycle TA8, and in the same cycle TA8, outputs the main memory read data output notification signal Q15 and the main memory read data Q16 to the bus interface mechanism 40 via the bus 20.

When the bus interface mechanism 40 receives the main memory read data output notification signal Q15 and the main memory read data Q16 from the main memory device 10 in the cycle TA8, the bus acquisition request for requesting the acquisition of the bus 30 in the cycle TB6 of the bus 30. The signal Q4 is output to the bus 30.

The bus acquisition request signal Q4 output from the bus interface mechanism 40 at the time of reading data from the main memory device 10 is set to have the highest priority of bus acquisition. Therefore, the bus interface mechanism 40 can acquire the bus 30 in the next cycle TB7, and outputs the main memory read data output notification signal Q15 and the main memory read data Q16 received in the cycle TA8 of the bus 20 to the main memory read data output notification signal, respectively. Q5 and main memory read data Q6 are transferred to the main memory data read request source processor 50 via the bus 20.

(Problems to be Solved by the Invention) As described above, conventionally, the main memory device (10) is connected to the processor (50) connected to the bus (30) to which the main memory device (10) is not connected. When the data is transferred by the data transfer destination processor (40), the bus interface mechanism (40) mediating the data transfer receives the main memory read data output notification signal and the main memory data from the main memory device (10). It started to get the bus (30) to which 50) is connected. Therefore, it takes a long time until the main memory data is transferred to the processor connected to the main memory data via the transfer destination bus, and there is a problem that the data transfer speed cannot be increased.

The present invention has been made in view of the above circumstances, and an object thereof is to minimize an overhead that occurs when a read data is transferred from a main memory device to a device on a bus to which the main memory device is not connected. An object of the present invention is to provide a main memory data transfer control method capable of increasing the transfer speed.

[Configuration of the Invention] (Means for Solving the Problems) The present invention relates to a main memory utilization device on a second bus in which this main memory device is not connected to a main memory device connected to a first bus. Means for outputting to the first bus an advance notification signal for notifying beforehand that the read data requested by the main memory device will be output to the first bus. The bus interface mechanism connecting the bus and the second bus is provided with means for starting a bus acquisition operation for acquiring the second bus in response to a prior notification signal on the first bus. It is characterized by.

(Operation) According to the above configuration, before the read data to be transferred to the utilization device connected to the second bus is output from the main memory device to the first bus, the output of the read data is notified in advance. An advance notification signal is output from the main memory device on the first bus. The bus interface mechanism uses the advance notification signal (read data output advance notification signal) on the first bus to transfer the read data output from the main memory device on the first bus to the transfer destination utilization device. Initiate a bus acquisition operation to acquire the second bus used to transfer. As a result, the start timing of the bus acquisition operation is earlier than that of the conventional method in which the acquisition operation of the second bus is started after the read data is output from the main memory device to the first bus, and the start time is shortened accordingly. Overhead can be reduced.

Embodiment An embodiment of the present invention will be described below with reference to the drawings. The same components as those in FIG. 4 and the same signals as those in FIG. 5 are designated by the same reference numerals, and detailed description thereof will be omitted. Also,
The main memory device and the bus interface mechanism have a different configuration from that of FIG. 4, but for convenience of explanation in conjunction with FIG. 4, the same reference numerals as those in FIG. Note that there is.

FIG. 1 is a block diagram mainly showing the internal configuration of a main memory device and a bus interface mechanism of an information processing system similar to that of FIG. In the main memory device 10 of FIG. 1, 11 is a memory cell array, 12 is a memory cell array 11
Is a memory access control circuit for controlling access to the memory. The memory access control circuit 12 includes various timing signals Q17 necessary to access the memory cell array 11 according to the main memory access request signal Q12 and the address & read function Q13 provided from the bus interface mechanism 40 via the bus 20. A bus 20 used for transferring the read data from the memory cell array 11 (main memory read data) Q16
In addition to the function to send a bus acquisition request signal Q14 to the bus 20 to acquire the above, the function to send the main memory read data output notification signal Q15 to the bus 20 to notify the output of the read data Q16, and the above-mentioned read Data Q16 is bus 20
It also has a function of sending a main memory read data output advance notification signal Q18 to the bus 20 to notify in advance that it will be output to the bus 20.

In the bus interface mechanism 40 of FIG. 1, 41 is a memory read data buffer for temporarily storing read data Q16 from the main memory device 10, and 42 is control of the memory read data buffer 41 and acquisition control of the bus 30. It is a buffer control circuit. The buffer control circuit 42 uses a control signal Q7 for controlling the memory read data buffer 41.
To the buffer 41, and a bus acquisition request signal Q4 for acquiring the bus 30 according to the delayed signal of the main memory read data output advance notification signal Q18 (output signal of the selector 48 described later). It also has a function of sending to the bus 30, a main memory read data output notification signal Q5 for notifying the output of the read data Q16 fetched from the memory read data buffer 41. 43 is a register (REG) for holding the main memory read data output advance notification signal Q18 on the bus 20 in synchronization with the bus cycle of the bus 20, and 44-1 to 44-n are the outputs of the register 43 on the bus 2
Registers (REG) connected in multiple stages for sequentially delaying and holding in synchronization with the 0 bus cycle. 45 is a selector for selectively outputting any one of the output signals of the registers 43, 44-1 to 44-n to the buffer control circuit 42, and 46 is a selector
It is a switch for generating 45 select signals.

Next, as in the case of the conventional example, the operation of one embodiment of the present invention will be described with reference to FIG. 2 regarding the data read from the processor 50 on the bus 30 to which the main memory device 10 is not connected to the main memory device 10. The timing chart will be described. The ratio of the transfer speed between the bus 20 and the bus 30 is
It is assumed to be the same as the case of the conventional example.

When data is read from the processor 50 to the main memory device 10, first, in a cycle TB1 of the bus 30, the processor 50 outputs a bus acquisition request signal Q1 for acquiring the bus 30.

When the bus 30 can be acquired by the output of the bus acquisition request signal Q1, the processor 50 in the next cycle TB2, the main memory access request signal Q2, the main memory address, and the function (address &
Read function) Q3 is output to the bus interface mechanism 40 via the bus 30.

Upon receiving the main memory access request signal Q2 and the address & read function Q3 from the processor 50 in the cycle TB2, the bus interface mechanism 40 outputs the bus acquisition request signal Q11 for requesting the acquisition of the bus 20 in the cycle TA1 of the bus 20. Output.

When the bus 20 can be acquired by the output of the bus acquisition request signal Q11, the bus interface mechanism 40 determines the next cycle T.
At A2, the main memory access request signal Q12 and the address & read function Q13 are output onto the bus 20.

The operations up to this point are the same as the operations (1) to (3) described in the conventional example.

The main memory access request signal Q12 and the address & read function Q13 output from the bus interface mechanism 40 onto the bus 20 are input to the memory access control circuit 12 in the main memory device 10. When the memory access control circuit 12 receives the main memory access request signal Q12 and the address & read function Q13 from the bus interface mechanism 40 in the cycle TA2, if the target main memory address is accessible, the next cycle A data read cycle for the memory cell array 11 in the main memory device 10 is started from TA3, and various timing signals Q17 are output to the memory cell array 11. In the example of FIG. 3, the above data read cycle is 4 of TA3 to TA6.
It is a bus cycle.

Then, when the memory access control circuit 12 receives the main memory access request signal Q12 and the address & read function Q13 from the bus interface mechanism 40, the reception cycle TA2, the data read cycles TA3 to TA6 following the cycle TA2, And, in any one bus cycle of the output cycle TA7 of the bus acquisition request signal Q14 for acquiring the bus 20 necessary for the transfer of main memory read data described later, the advance notification of the output of the main memory read data (advance notification) The main memory read data output advance notification signal Q18 for outputting) is output to the bus 20. here,
The main memory read data output advance notification signal Q18 is output in the cycle TA4 as shown in FIG.

The main memory read data output advance notification signal Q18 output on the bus 20 from the memory access control circuit 12 in the main memory device 10 in the cycle TA4 is input to the bus interface mechanism 40, and the register 43 in the mechanism 40 receives the following information. It is held in cycle TA5. The contents held in the register 43 (main memory read data output advance notification signal Q18) are input to the selector 45 together with the contents held in the registers 44-1 to 44-n. The selector 45 includes registers 43, 44-1 to 44-n.
Among them, the output signal of the register designated by the switch 46 is selectively output to the buffer control circuit 42. Here, the register 43 is designated by the switch 46, and therefore the output signal of the register 43 is selected by the selector 45 and output to the buffer control circuit 42. In this case, the selection output signal of the selector 45 becomes active in the cycle TAT.

Buffer control circuit 42 in bus interface mechanism 40
When the selection output signal from the selector 45, that is, the delay signal of the main memory read data output advance notification signal Q18 (here, the delay signal only by the register 43) becomes active, the state of the read data buffer 41 is checked and the buffer 41 In the empty state, the bus acquisition request signal Q4 for requesting acquisition of the bus 30 is output in the cycle next to the cycle of the bus 30 at that time (cycle TB5 in this case).

Now, the memory access control circuit in the main memory device 10
When the data read cycle TA3 to TA6 is completed,
In the next cycle TA7 of the bus 20, the bus acquisition request signal Q14 is output to the bus 20 for transfer of the main memory read data. The bus acquisition request signal Q14 from the memory access control circuit 12 in the main memory device 10 is set to have the highest priority of bus acquisition. Therefore, the main memory device 10
Can obtain the bus 20 in the next cycle TA8, and the main memory read data output notification signal Q15 and the main memory read data Q16 can be obtained in the bus 20 in the cycle TA8 as in the conventional example.
To the bus interface mechanism 40 via. The buffer control circuit 42 in the bus interface mechanism 40 temporarily stores the main memory read data Q16 on the bus 20 in the read data buffer 41 in response to the main memory read data output notification signal Q15.

On the other hand, the bus acquisition request signal Q4 output from the buffer control circuit 42 in the bus interface mechanism 40 to the bus 30 in the cycle TB5 of the bus 30 also has the priority of bus acquisition because it is during the data read from the main memory device 10. It is set to the highest. Therefore, the bus interface mechanism 40 can acquire the bus 30 in the next cycle TB7, and the main memory read data output notification signal Q1 received in the cycle TA8 of the bus 20.
5 and the main memory read data Q16 (in the read data buffer 41) are transferred as the main memory read data output notification signal Q1 and the main memory read data Q6 to the processor 50 which is the main memory data read request source via the bus 30. To do.

The above has described the case where the ratio of the transfer rates of the bus 20 and the bus 30 is the same as that of the conventional example. However, when the ratio is different from that of the conventional example, specifically, the transfer rate of the bus 20 is the conventional example. A case later than the above embodiment will be described with reference to the timing chart of FIG.
It should be noted that the magnification of the time axis of FIG. 3 is smaller than that of FIG.

First, the processor 50 outputs the bus acquisition request signal Q1 of the bus 30 in the cycle TB1, and the memory access control circuit 12 in the main memory device 10 outputs the main memory read data output advance notification signal Q18 to the bus 20 in the cycle TA4. The operation up to this is the same as that of the above-described embodiment shown in the timing chart of FIG.

The main memory read data output advance notification signal Q18 output on the bus 20 from the memory access control circuit 12 in the main memory device 10 in the cycle TA4 is input to the bus interface mechanism 40, and the register 43 in the mechanism 40 receives the following information. It is held in cycle TA5. The contents held in the register 43 (main memory read data output advance notification signal Q18) are sequentially transmitted to the register 44-1, the register 44-2, ..., The register 44-n in synchronization with the bus cycle of the bus 20. As a result, the output signal of the register 43 becomes active in the cycle TA5, the output signal of the register 44-1 becomes active in the next cycle TA6, and the output signal of the register 44-2 becomes active in the next cycle TA7. The output signals of the registers 43, 44-1 to 44-n are input to the selector 45. The selector 45 selectively outputs the output signal of the register designated by the switch 46 among the registers 43, 44-1 to 44-n of the buffer control circuit 42. Here, register 44 is set by switch 46.
-2 is designated, so that the output signal of the register 44-2 is output to the buffer control circuit 42 selected by the selector 45. In this case, the selection output signal of the selector 45 becomes active in the cycle TA7 as described above.

Buffer control circuit 42 in bus interface mechanism 40
When the selection output signal from the selector 45, that is, the delay signal of the main memory read data output advance notification signal Q18 (here, the output signal of the register 44-2) becomes active, the state of the read data buffer 41 is checked and the buffer 41 Is empty, in order to request acquisition of the bus 30 in the next cycle (here, cycle TB9) of the cycle (TB8) of the bus 30 corresponding to the bus cycle (TA7) of the bus 20 at that time. The bus acquisition request signal Q4 is output.

Now, the memory access control circuit in the main memory device 10
When the data read cycle TA3 to TA6 is completed,
In the next cycle TA7 of the bus 20, the bus acquisition request signal Q14 is output to the bus 20 for transfer of the main memory read data. The bus acquisition request signal Q14 from the memory accelerator control circuit 12 in the main memory device 10 is set to have the highest priority of bus acquisition. Therefore, the main memory device 10
Can obtain the bus 20 in the next cycle TA8, and the main memory read data output notification signal Q15 and the main memory read data Q16 can be obtained in the bus 20 in the cycle TA8 as in the conventional example.
To the bus interface mechanism 40 via. The buffer control circuit 42 in the bus interface mechanism 40 reads the main memory read data Q16 on the bus 20 from the read data buffer 41 in response to the main memory read data output notification signal Q15.
To be stored temporarily.

On the other hand, in the cycle TB9 of the bus 30, the bus acquisition request signal Q4 output from the buffer 30 from the buffer control circuit 42 in the bus interface mechanism 40 is also at the time of reading data from the main memory device 10, so that the priority of bus acquisition is high. It is set to the highest. Therefore, the bus interface mechanism 40 can acquire the bus 30 in the next cycle TB10, and the main memory read data output notification signal received in the cycle TA8 of the bus 20.
Q15 and the main memory read data Q16 (in the read data buffer 41) are designated as the main memory read data output notification signal Q5 and main memory read data Q6 via the bus 30, and the processor 50 which is the main memory data read request source.
Transfer to.

In the example of FIG. 3, the contents of the register 43 is the selector 45.
, The output signal of the selector 45 becomes active in the cycle TA5. Therefore, the buffer control circuit 42 uses the cycle T of the bus 30 at that time.
In the cycle TB8 next to B7, the bus acquisition request signal Q4 for requesting the acquisition of the bus 30 is output, and in the next cycle TB9, the main memory read data can be output in timing. But this cycle T
In B9, the main memory read data (Q16) is at the stage where the bus 20 is being output from the main memory device 10 (third part).
(Refer to the drawing), it is not yet held in the read data buffer 41 in the bus interface mechanism 40. Therefore, in the example shown in FIG. 3, the main memory read data output advance notification signal Q18 held in the register 43 is connected to the register 44-
1 to 44-n are sequentially delayed in synchronism with the bus cycle of the bus 20, and one of the registers 43, 44-1 to 44-n is set to the bus 2
By selecting and outputting from the selector 45 according to the setting contents of the switch 46 which is determined according to the transfer rate ratio between 0 and the bus 30, the bus acquisition timing of the bus 30 by the main memory read data output advance notification signal and the bus 30 The main memory read data output timing can be adjusted.

[Effect of the Invention] As described in detail above, according to the present invention, the main memory device connected to the first bus to the device on the second bus to which the main memory device is not connected is connected to the main memory device. In transferring the memory read data, a pre-notification signal for notifying the output of the main memory read data from the main memory device before the data is output from the main memory device to the first bus. Since the bus interface mechanism starts the bus acquisition operation of the second bus before receiving the main memory read data in response to this advance notification signal, the bus acquisition is performed after receiving the main memory read data. Minimizes the overhead that occurs when transferring main memory read data to a device on the second bus to which the main memory device is not connected, as compared to the conventional method in which the operation is started. Therefore, the data transfer speed can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation, and FIG.
FIG. 4 is a timing chart for explaining the operation when the transfer speed ratio between the bus 20 and the bus 30 shown in FIG. 1 is different from that in FIG. 2, and FIG. 4 is the bus to which the main memory device is connected and the main memory. A block configuration diagram showing a basic configuration of an information processing system in which a bus to which no device is connected is coupled by a bus interface mechanism, and FIG. 5 explains a conventional main memory read data transfer operation in the system shown in FIG. 3 is a timing chart for 10 …… Main memory device, 11 …… Memory cell array, 12 ……
Memory accelerator control circuit, 20 ... Bus (first bus),
30 ... Bus (second bus), 40 ... Bus interface mechanism, 41 ... Read data buffer, 42 ... Buffer control circuit, 43, 44-1 to 44-n ... Register (REG), 50 ...
… Processor (device), Q18 …… Main memory read data output Advance notification signal.

Claims (1)

(57) [Claims] 1. A first bus to which various devices including a main memory device are connected, at least one second bus to which the main memory device is not connected, and a second bus connected to the second bus, A utilization device that utilizes a main memory device;
And a bus interface mechanism for connecting the second bus and controlling the data transfer between the two buses, the read data requested by the utilization device is stored in the main memory device. Means is provided for outputting to the first bus an advance notification signal for notifying in advance that the main memory device will output to the first bus, and the bus interface mechanism is provided with the second bus. A means for starting a bus acquisition operation for acquiring in response to the advance notification signal on the first bus is provided, and the read data to be transferred to the utilization device connected to the second bus is the main memory. Before the output from the device to the first bus, the acquisition operation of the second bus used for transferring the read data to the utilization device is started. Main memory data transfer control method according to claim.