JPS61256463A - Microcomputer equipment - Google Patents

Abstract

PURPOSE:To smoothly carry out the information transmission between CPUs by prohibiting one CPU from making access to a memory area when the other CPU makes access to a shared memory area. CONSTITUTION:Before a CPU 1 makes access to a shared memory area 4, the area 4 is made access after a specific address is outputted to an address buffer 3. After the CPU 1 outputs the specific address to the buffer 3, when a CPU 2 tries to make access to the area 4 and outputs the address to the buffer 3, an HALT input signal 8 to the CPU 2 is activated by the buffer 3 to make the CPU 2 halt, thereby the CPU 2 is prohibited from making access to the area 4. When the CPU 1 completes the access of the area 4, a specific address is outputted to the buffer again to release the signal 8 and enable the CPU 2 to make access to the area 4. Thus, the information transmission between the CPUs can be smoothly performed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a microcomputer device using two or more CPUs in a single circuit.

@ to the microcomputer device that is a bait for efficiently transmitting information between CPUs.

[Back mold of invention]

In the conventional device, it is possible to transfer FF between cpvs by having CPUs 211a1 and above access a common memory area seven times, but this area can be accessed by two or more CPUs at the same time.

There is a problem that the system no longer operates normally.

ξObject of the Invention] An object of the present invention is to enable a certain CPU to access a common memory area while another CPU accesses that memory area.

[View of the invention]

In order to accomplish the above purpose, the present invention adds a signal line indicating that a certain CPU is accessing a common memory location, and other CPUs access the common memory while that signal is active. Access to the area is limited.

[Example of invention]

Hereinafter, an example of the present invention will be explained with reference to the drawings. The diagram is C
The circuit diagram is shown when PU 2111 is used. 1
is CpUl, 2 is CPU2.3 decodes the address output from 2 and sends HAL to 2 according to the content of that address.
A circuit 8 for manually generating a signal for temporarily stopping the creation of the CCPU, and an address bus buffer when 1 and 2 access 4, 4 is a common memory gL area,
5 is address bus 1, 6 is address bus 2, 7 is address bus 4
8 is the BALT manual signal to 2. Since 1 outputs an incorrect address to 3 before accessing 4, it accesses 4. 1 outputs an address to 5, and 2 tries to access 4 and outputs the address to 5, 3 activates 8, and 2
By making it HALT, 2 is forced to access 4. ◎ 1 accesses 4 '4I: When finished, it is surprised by 5, outputs the special foot address, divides 8 by 'S, and selects 2 or 4. Make it accessible.Also, instead of 1ALTq, Ike no Kirigomi No. 91 may be used, or a flag sense method may be used.

〔Effect of the invention〕

As explained above, according to the present invention, by adding a simple circuit, it is possible to smoothly transmit information between CPUs.

[Brief explanation of drawings]

The figure is a block diagram of one embodiment of the present invention.

Claims (1)

[Claims] 1. Two or more CPUs (Central Processing Units) are used in the same circuit, and this memory area is buffered by switching banks of part of the memory area as a means of transmitting information from one CPU to another. 1. A microcomputer device used as a memory for use in a microcomputer device, characterized in that it is possible to prohibit each CPU from accessing the memory area at the same time.