JPS6125240B2 - - Google Patents
Info
- Publication number
- JPS6125240B2 JPS6125240B2 JP55179409A JP17940980A JPS6125240B2 JP S6125240 B2 JPS6125240 B2 JP S6125240B2 JP 55179409 A JP55179409 A JP 55179409A JP 17940980 A JP17940980 A JP 17940980A JP S6125240 B2 JPS6125240 B2 JP S6125240B2
- Authority
- JP
- Japan
- Prior art keywords
- printed circuit
- circuit components
- base
- circuit board
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000002093 peripheral effect Effects 0.000 claims description 9
- 238000000034 method Methods 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Combinations Of Printed Boards (AREA)
- Mounting Of Printed Circuit Boards And The Like (AREA)
Description
本発明はIC等の回路素子をプリント基板に実
装する際の平面スペースを節約し、かつ回路部品
間の配線距離を最小とする高密度実装構造に関す
るものである。
IC等の回路部品をプリント基板に実装する場
合、従来は回路部品をプリント基板の表面に平面
的に配置して実装しているが、この実装構造では
実装に要する平面スペースの節約に限度があり、
平面スペースに制約がある場合にはこれに代る高
密度実装構造が要望されている。又、平面にチツ
プを配置した場合には、チツプ相互間の配線が長
くなり、システムの高速化の要求を満足出来ない
結果となつている。
本発明はこの要望を実現するためのもので、平
面スペースを大幅に節約するとともに、チツプ間
の配線長を最小に出来る高密度実装構造を提供す
ることを目的としている。
次に図面に関連して本発明の実施例を説明す
る。
本発明は、上面に回路部品接続用端子部を有す
ると共に内部配線パターンが形成されたプリント
基板の下に、それぞれ各周面に回路部品接続用端
子部を露出させ、対向する多数のプリント基板の
積み重ねによつて、各プリント基板間が立体配線
接続される角柱状の基体を形成するとともに、該
基体の下面に各プリント基板に形成されたパター
ンを介し導通する信号及び電源接続用端子部を形
成し、基体の上面および各周面にそれぞれ回路部
品を実装できるようにしたものである。次にその
構成および製造法の詳細について説明する。
第1図は基体の概要を示す分解斜視図で、基体
1は多数のプリント基板21,22,23,…
…,2oを積重ねてなる。プリント基板21の上
面には回路部品端子接続用端子部3が設けられて
いる。またプリント基板22,23,……2oに
はそれぞれ各周面に露出する回路部品端子接続用
端子部4が所定の配置で設けられている。これら
の端子部4は、通常のグリーンシート製造法によ
り端面にパターンを出し焼成後研磨して薄膜又は
スクリーン印刷でパツドを作る等の方法により形
成可能である。プリント基板2oの下面には、詳
細図示を省略したが複数個の信号及び電源接続用
端子部が設けられ、該端子部は各端子部3および
4と各プリント基板に形成されたパターンを介し
導通している。
このように基体1の上面および各周面には端子
部3および4が形成されているため、第2図に示
すように基体1の上面および各周面に回路部品5
をその各端子部6を端子部3,4に接続して実装
することが可能である。
第3図には、この基体1に対する回路部品の他
の実装要領を示す。本例の場合は、基体1の上面
には第2図の場合と同様に回路部品5を実装し、
基体1の各周面にはそれぞれ回路部品5′を実装
したプリント基板7を取付けるようになつてい
る。プリント基板7の回路部品5′実装側と反対
側には端子部4′が露出しており、この端子部を
基体1の周面の端子部4に接続してプリント基板
7は取付けられる。第4図は回路部品5、プリン
ト基板7の取付完了状態を示している。
このような実装構造を採用した場合と従来のよ
うに回路部品をプリント基板上に平面的に実装す
る場合の平面スペースの比較をすると次のように
なる。
いま回路部品の寸法をS×Sとし、その実装ピ
ツチを2Sとすると、従来の方式により4個の回
路部品を従横に隣接して配置させるのに要する平
面スペースは第5図aに鎖線で囲む範囲で、その
面積は4S×4S=16S2となる。図中5″は回路部品
である。
これに対し、本発明の方式により各基体表面に
回路部品5を同一ピツチで配置させるのに要す
る平面スペースは第5図bに鎖線で示す範囲で、
その面積は例えば5S×5S=25S2とする。ここに
5Sは回路部品を実装した基体を配列するのに要
する標準的なピツチである。
前者の場合は、16S2の中に回路部品5″が4個
実装されるので、1個当りの平面スペースは16S2/
4
=4S2となり、後者の場合は、25S2の中に回路部
品5が4×5=20個実装されるので、1個当り
の平面スペースは25S2/20=5/4S2となる。
すなわち、本発明の方式の場合、平面スペース
を従来の方式の場合の
The present invention relates to a high-density mounting structure that saves plane space when mounting circuit elements such as ICs on a printed circuit board and minimizes the wiring distance between circuit components. Conventionally, when mounting circuit components such as ICs on a printed circuit board, the circuit components are placed flat on the surface of the printed circuit board. However, with this mounting structure, there is a limit to the saving of the flat space required for mounting. ,
If planar space is limited, an alternative high-density mounting structure is desired. Furthermore, when the chips are arranged on a plane, the wiring between the chips becomes long, which results in the inability to satisfy the demand for higher speed systems. The present invention is intended to fulfill this need, and aims to provide a high-density packaging structure that can significantly save planar space and minimize the wiring length between chips. Embodiments of the invention will now be described with reference to the drawings. The present invention exposes a circuit component connection terminal section on each peripheral surface under a printed circuit board that has a circuit component connection terminal section on the top surface and has an internal wiring pattern formed thereon, and connects a large number of facing printed circuit boards. By stacking, each printed circuit board is formed into a prismatic base to which three-dimensional wiring is connected, and a terminal portion for signal and power connection is formed on the bottom surface of the base for conduction through the patterns formed on each printed circuit board. However, circuit components can be mounted on the upper surface and each peripheral surface of the base. Next, the structure and manufacturing method will be explained in detail. FIG. 1 is an exploded perspective view showing the outline of the base body 1, which includes a large number of printed circuit boards 2 1 , 2 2 , 2 3 , . . .
..., 2 o are stacked on top of each other. A terminal portion 3 for connecting circuit component terminals is provided on the upper surface of the printed circuit board 21 . Further, the printed circuit boards 2 2 , 2 3 , . . . 2 o are each provided with circuit component terminal connection terminal portions 4 exposed on their respective peripheral surfaces in a predetermined arrangement. These terminal portions 4 can be formed by a method such as forming a pattern on the end face using a conventional green sheet manufacturing method, baking and polishing the green sheet to form a pad using a thin film or screen printing. The lower surface of the printed circuit board 2o is provided with a plurality of signal and power connection terminals (not shown in detail), and the terminals are connected to each terminal section 3 and 4 through the patterns formed on each printed circuit board. Conductive. Since the terminal parts 3 and 4 are formed on the top surface and each peripheral surface of the base 1 in this way, the circuit components 5 are formed on the top surface and each peripheral surface of the base 1 as shown in FIG.
can be mounted by connecting each terminal portion 6 to the terminal portions 3 and 4. FIG. 3 shows another method for mounting circuit components on the base 1. As shown in FIG. In this example, the circuit component 5 is mounted on the top surface of the base 1 as in the case of FIG.
A printed circuit board 7 on which circuit components 5' are mounted is attached to each peripheral surface of the base 1. A terminal portion 4' is exposed on the opposite side of the printed circuit board 7 from the side on which the circuit component 5' is mounted, and the printed circuit board 7 is mounted by connecting this terminal portion to the terminal portion 4 on the peripheral surface of the base body 1. FIG. 4 shows a state in which the circuit components 5 and the printed circuit board 7 have been completely installed. A comparison of the planar space when such a mounting structure is adopted and when circuit components are mounted two-dimensionally on a printed circuit board as in the past is as follows. Assuming that the dimensions of the circuit components are S x S and the mounting pitch is 2S, the planar space required to arrange four circuit components side by side in the conventional method is shown by the chain line in Figure 5a. The area of the enclosed area is 4S x 4S = 16S 2 . 5'' in the figure is a circuit component.On the other hand, the planar space required to arrange the circuit components 5 at the same pitch on each substrate surface according to the method of the present invention is within the range shown by the chain line in FIG.
The area is, for example, 5S x 5S = 25S 2 . Here
5S is the standard pitch required for arranging substrates with circuit components mounted on them. In the former case, four circuit components 5" are mounted in 16S 2 , so the planar space per one is 16S 2 /
4 = 4S 2 , and in the latter case, 4×5=20 circuit components 5 are mounted in 25S 2 , so the planar space for each component is 25S 2 /20=5/4S 2 . In other words, in the case of the method of the present invention, the plane space is
【式】にす
ることが可能である。
第1図〜第5図では、Zo枚の回路基板の積重
ねにより、その方向に2段の回路部品を配した
が、他の応用例では、同じ積重ね数Zoで2段以
上の実装が可能となる。
第6図a,bには3段の例を示している。第6
図aは完成状態の斜視図、第6図bはそのプリン
ト基板積重ね要領を示す斜視図である。
この場合の実装密度は、平面的にはその占有面
積は変わらないので5S×5Sの面積に4×6+4
=28Yの回路部品が搭載されることになる。
平面実装との比は、It is possible to make [Formula]. In Figures 1 to 5, two stages of circuit components are arranged in that direction by stacking Z o circuit boards, but in other application examples, two or more stages can be mounted with the same number of stacks Zo . It becomes possible. An example of three stages is shown in FIGS. 6a and 6b. 6th
Figure a is a perspective view of the completed state, and Figure 6b is a perspective view showing how to stack the printed circuit boards. In this case, the mounting density is 4 x 6 + 4 in the area of 5S x 5S, since the occupied area does not change on a plane.
=28Y circuit components will be installed. The ratio with flat mounting is
【式】とな
る。
以上述べたように、本発明によれば、回路部品
実装に要する平面スペースを大幅に節約すること
が可能で、特に高さの制約がなく平面スペースを
節約したい場合に効果的である。更に本発明によ
れば、チツプ間の配線を立体の形状をした基体内
で行なうため配線長を最小に押えることができ
る。[Formula] becomes. As described above, according to the present invention, it is possible to significantly save the planar space required for mounting circuit components, and it is particularly effective when there is no height restriction and it is desired to save the planar space. Further, according to the present invention, since the wiring between chips is performed within a three-dimensional base, the wiring length can be kept to a minimum.
図面は本発明に係る高密度実装構造の実施例を
示すもので、第1図は基体の分解斜視図、第2図
は回路部品実装要領を示す斜視図、第3図は他の
回路部品実装要領を示す斜視図、第4図はその組
立完了状態を示す斜視図、第5図aおよびbは従
来の方式および本発明の方式による所要実装平面
スペース比較説明図、第6図a,bは他の応用例
を示す斜視図で、図中、1は基体、21,22,
……,2o,7はプリント基板、3,4は回路部
品接続用端子部、5,5′,5″,5は回路部
品、6は端子部である。
The drawings show an embodiment of the high-density mounting structure according to the present invention. Fig. 1 is an exploded perspective view of the base, Fig. 2 is a perspective view showing the procedure for mounting circuit components, and Fig. 3 is an example of mounting other circuit components. FIG. 4 is a perspective view showing the completed assembly state; FIGS. 5 a and b are comparative illustrations of the required mounting plane space between the conventional method and the method of the present invention; FIGS. 6 a and b are diagrams showing the required mounting plane space. This is a perspective view showing another application example, in which 1 is a base, 2 1 , 2 2 ,
. . . , 2 o and 7 are printed circuit boards, 3 and 4 are terminals for connecting circuit components, 5, 5', 5'' and 5 are circuit components, and 6 is a terminal section.
Claims (1)
内部配線パターンが形成されたプリント基板の下
に、それぞれ各周面に回路部品接続用端子部を露
出させ、対向する多数のプリント基板の積み重ね
によつて、各プリント基板間が立体配線接続され
る角柱状の基体を形成するとともに、該基体の下
面に前記各プリント基板に形成されたパターンを
介し導通する信号及び電源接続用端子部を形成
し、前記基体の上面および各周面にそれぞれ回路
部品を実装できるようにしたことを特徴とする高
密度実装構造。1 Underneath the printed circuit board that has a terminal section for connecting circuit components on the top surface and has an internal wiring pattern formed thereon, terminal sections for connecting circuit components are exposed on each peripheral surface, and a number of printed circuit boards facing each other are stacked. forming a prismatic base body to which three-dimensional wiring connections are made between the respective printed circuit boards, and forming terminal portions for signal and power supply connection on the lower surface of the base body for conduction through the patterns formed on the respective printed circuit boards; A high-density mounting structure characterized in that circuit components can be mounted on the upper surface and each peripheral surface of the base.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17940980A JPS57103389A (en) | 1980-12-18 | 1980-12-18 | High density mounting structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17940980A JPS57103389A (en) | 1980-12-18 | 1980-12-18 | High density mounting structure |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57103389A JPS57103389A (en) | 1982-06-26 |
JPS6125240B2 true JPS6125240B2 (en) | 1986-06-14 |
Family
ID=16065355
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17940980A Granted JPS57103389A (en) | 1980-12-18 | 1980-12-18 | High density mounting structure |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57103389A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03109945U (en) * | 1990-02-27 | 1991-11-12 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH069262B2 (en) * | 1984-09-21 | 1994-02-02 | 株式会社日立製作所 | Superconducting device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5092684A (en) * | 1973-12-13 | 1975-07-24 |
-
1980
- 1980-12-18 JP JP17940980A patent/JPS57103389A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5092684A (en) * | 1973-12-13 | 1975-07-24 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03109945U (en) * | 1990-02-27 | 1991-11-12 |
Also Published As
Publication number | Publication date |
---|---|
JPS57103389A (en) | 1982-06-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6162997A (en) | Circuit board with primary and secondary through holes | |
JPS58159360A (en) | Semiconductor device | |
US5095407A (en) | Double-sided memory board | |
US6121679A (en) | Structure for printed circuit design | |
US5691569A (en) | Integrated circuit package that has a plurality of staggered pins | |
JPS6125240B2 (en) | ||
CN216146514U (en) | Circuit board and electronic device | |
JP2833521B2 (en) | Wiring board | |
JPH06111869A (en) | Surface mount terminal | |
JPH0129802Y2 (en) | ||
CA1312387C (en) | Hybrid printed circuit board | |
JPH023621Y2 (en) | ||
JPH0211032B2 (en) | ||
JPS6228791Y2 (en) | ||
JPH11177245A (en) | 3-dimentional mounting method | |
JP3769881B2 (en) | Electronic circuit equipment | |
JPH0439668Y2 (en) | ||
JP2502535Y2 (en) | PGA type ceramic package | |
JP2527326Y2 (en) | Circuit board device | |
JP2785475B2 (en) | Wiring device for mounting semiconductor elements | |
JP2813406B2 (en) | Semiconductor package mounting method | |
JPH02288201A (en) | Chip component | |
JPS62583B2 (en) | ||
JPH0432291A (en) | Mounting method for electronic circuit board | |
JPH05136182A (en) | Hybrid integrated circuit substrate |