JPS6125178B2 - - Google Patents

Info

Publication number
JPS6125178B2
JPS6125178B2 JP54080817A JP8081779A JPS6125178B2 JP S6125178 B2 JPS6125178 B2 JP S6125178B2 JP 54080817 A JP54080817 A JP 54080817A JP 8081779 A JP8081779 A JP 8081779A JP S6125178 B2 JPS6125178 B2 JP S6125178B2
Authority
JP
Japan
Prior art keywords
memory
line
read
processors
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54080817A
Other languages
English (en)
Japanese (ja)
Other versions
JPS567161A (en
Inventor
Tadaaki Bando
Yasushi Fukunaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8081779A priority Critical patent/JPS567161A/ja
Publication of JPS567161A publication Critical patent/JPS567161A/ja
Publication of JPS6125178B2 publication Critical patent/JPS6125178B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Memory System (AREA)
  • Multi Processors (AREA)
JP8081779A 1979-06-28 1979-06-28 Memory interface device Granted JPS567161A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8081779A JPS567161A (en) 1979-06-28 1979-06-28 Memory interface device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8081779A JPS567161A (en) 1979-06-28 1979-06-28 Memory interface device

Publications (2)

Publication Number Publication Date
JPS567161A JPS567161A (en) 1981-01-24
JPS6125178B2 true JPS6125178B2 (US20110009641A1-20110113-C00256.png) 1986-06-14

Family

ID=13728996

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8081779A Granted JPS567161A (en) 1979-06-28 1979-06-28 Memory interface device

Country Status (1)

Country Link
JP (1) JPS567161A (US20110009641A1-20110113-C00256.png)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57143658A (en) * 1981-03-02 1982-09-04 Nec Corp Microcomputer compounding system
DE3151120C2 (de) * 1981-12-23 1983-12-01 Siemens AG, 1000 Berlin und 8000 München Datenverarbeitungsanlage mit Arbeitsspeicher und mehreren in Serie geschalteten Prozessoren
NO173304C (no) * 1984-12-20 1993-11-24 Honeywell Inc Dobbelt buss-system
JPS63257051A (ja) * 1987-04-15 1988-10-24 Hitachi Ltd マルチコンピユ−タシステム

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5221736A (en) * 1975-08-08 1977-02-18 Western Electric Co Multiprocessor processor and device for poling memory request

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5221736A (en) * 1975-08-08 1977-02-18 Western Electric Co Multiprocessor processor and device for poling memory request

Also Published As

Publication number Publication date
JPS567161A (en) 1981-01-24

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