JPS61251285A - Descramble device - Google Patents

Abstract

PURPOSE:To correspond to both modes of NTSC, and scramble without using a delay correcting circuit of analog by operating a whole of the system as a PLL system using a digital synchronous signal in a scramble mode and as the PLL system using a burst signal in the NTSC mode. CONSTITUTION:PLL arithmetic circuits 120, 120 used in the descramble device have PLL error arithmetic circuits 121, 122 correspondingly to a scramble mode, an NTSC mode respectively and comprises a change over circuit 123 for changing over and outputting in accordance with a mode outputs of the error arithmetic circuits 121, 122 and a loop filter 124. Respectively calculated error signals Es, En are supplied together to the change-over circuit 123. The change-over circuit 123 selects Es during the scramble mode in accordance with a mode change over signal 53, and En during the NTSC mode, respectively and supplies as an output signal 125 to the loop filter 124. The loop filter 124 smoothes the inputted error signal 125 and supplies as a phase error signal 15 to a D/A converting circuit.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a descrambling device having a function of receiving a scrambled (encrypted) television signal and descrambling (decoding) it. .

[Technical background of the invention]

In recent years, one of the transmission formats of television broadcast signals is that the signals are transformed and transmitted, and the receiving side has to prepare a special descrambling device for decoding in order to obtain a normal image. can.

Various methods have been proposed for scrambling television signals, and one of them, the intra-line rotation method, will be described below.

The intra-twin rotation method is shown in Figure 4 (
11) The video period P of the NT8C video signal 91 as shown in FIG. scrambled signal 96
Send as. At this time, information on the division point is sent out together with another system 1, for example, audio data.

Therefore, the dividing point address
It is given in units of 8 blocks. The video period P is replaced at the division point X mentioned above.

1 address X-1, for superposition when decoding on the receiving side.
Prepare a new block of 94.95 and 94.
5 is added after each address x-1. When the scrambled video signal is digitized and processed on the receiving side, sampling is normally performed at 4 feet (fsc: color subcarrier frequency). Therefore, Fig. 5 (
As shown in a), one horizontal period has 910 sample points.
It will be divided equally. The absolute address corresponds to this sample point], so the address X of the boot stock unit is address 140, address 147, etc.

A value will be taken for every 7 addresses such as 903rd address, 910th address, etc.

FIG. 5(b) is an enlarged view of the digital synchronization signal 93 added to the horizontal synchronization portion 92. The digital synchronization signal 93 is inserted between addresses 19 and 6, has a frequency of Tfsc, and has 7 cycles.

The above-mentioned address (See Figure 4 Φ)) can also be known accurately.

The scrambled signal % can be properly decoded without causing hue shift or the like. In addition, scramble signal%
In addition to the above-mentioned digital synchronization signal 93, the horizontal synchronization part 97 includes a frame synchronization signal frame that is transmitted at a rate of one per frame and serves as a reference signal for 7-frame synchronization, and one signal per horizontal period. A scrambling timing signal 9 is added which is transmitted as a switching reference signal for various scrambled data.

The scramble signal detailed above is generated during the video period P based on the decoding point information y read from the dividing point information X on the receiving side.
Along with the re-replacement of.

removal of margins 94, 95 and digital synchronization signal 93;

The synchronization signal 92 is also changed, as shown in
It is decoded as shown in C).

Next, an example of a descrambling device for descrambling the above-mentioned scramble signal 96 will be explained with reference to the drawings.

FIG. 6 is a block diagram showing the decoding circuit 100 portion of the descrambler.

After the scramble signal % is band-limited by a low-frequency ν filter (I, PF) 1, it is supplied to an A/D conversion circuit 2. Sampling and quantization are performed here, and a digital scrambled video signal 3 is output. In this case, the sampling frequency afS is fs = 4 fsc, and the sampling phase is synchronized with the feed address of the digital synchronization signal. A system clock 4 that provides sampling timing is generated by a clock generation circuit 5, and is generated by an A/D conversion circuit 2. It is supplied to the decoding circuit 100 and used as a reference for circuit operation.

The digital scrambled video signal 3 is supplied to a clamp calculation circuit 6, subjected to clamp error calculation (based on the timing of the burst gate pulse 8 which is output multiple times from the timing generation circuit 7), and then subjected to a clamp error calculation as a digital clamp control signal 9.
The signal is supplied to the conversion circuit 10.

The burst gate pulse 8 provides timing for color burst integration for detecting the magnitude of the pedestal level in the clamp calculation circuit 6, and has a width of 2 - 3 burst cycles, or t#) 12 samples.

The D/A conversion circuit 10 converts the input digital clamp control signal 9 into an analog clamp control signal 11.
Output as . The clamp control signal 11 is added to the scramble signal % as an offset voltage and clamped.

Further, the digital scrambled video signal 3 is supplied to the PLL operation circuit, and is subjected to PLL error calculation between it and the digital synchronization reference signal 14 according to the timing of the digital synchronization gate pulse 13 outputted by the timing generation circuit 7. The digital synchronization gate pulse 13 provides timing for integrating the phase error to detect the phase of the digital synchronization signal 93 in the PLL arithmetic circuit. It has a width of 15 samples. Further, the digital synchronization reference signal 14 is obtained by dividing the system frequency 4 by 5 by the frequency dividing circuit amount, and its phase is at the absolute addresses 19, 24, and 24 of the digital synchronization signal.
It matches the location of No. 29. The above FLU, arithmetic circuit 12
The digital phase error signal 15 outputted by the converter is converted into an analog phase error signal 17 via the D/A converter circuit 16, and is supplied to the clock generating circuit 5. The clock generation circuit 5 outputs a system clock 4 subjected to multi-phase control using the analog phase error signal 17. As a result, the sampling phase matches the absolute address of the digital synchronizing signal 93.

Now, the scramble signal % is also supplied to the sync separation circuit 18, where sync separation is performed and a composite sync signal 19 is output. This synchronization signal 19 is further supplied to a horizontal synchronization detection circuit 20, where it undergoes horizontal synchronization separation and outputs a horizontal synchronization signal 21. The horizontal synchronizing signal 8. is supplied to a timing generation circuit 7, which generates a burst pulse 8. A digital synchronization clock l and a digital synchronization timing pulse n are generated and output. The digital synchronization timing pulse n is a gate pulse for detecting the first digital synchronization signal 93, and in order to detect address n, which is the first falling edge of the digital synchronization signal 93, it rises near address 19.
It is designed to fall near address D24 (Figure 5 (d)
)reference).

A digital scramble video signal 3, a digital synchronization reference signal 14, and a digital synchronization timing pulse n are supplied to the digital synchronization detection circuit, detects the absolute address, and outputs a descramble reference signal (fifth
(See figure (e)). The descrambling reference signal is supplied to the phase comparator circuit 5.

The phase is compared with the Kakuunta U address signal I output from the horizontal write counter. If the phase is shifted.

A phase control signal path is provided to the horizontal write capacitor.

The phase shift of the next address signal n output from the horizontal write counter is corrected.

The horizontal read counter 4 is supplied with a decoding point address signal I from another system, and outputs a read address 31 for descrambling. This horizontal read counter 4 is controlled by a phase control signal 32 from the horizontal write counter % so that both counters operate synchronously.

Scramble signal 3 is supplied to the 2H memory.

Here, the scramble signal 3 is written by the write address diagonal supplied from the horizontal write counter 4, and read by the read address 31 supplied from the horizontal read counter 4, and the video period P is replaced again. .

By the way, the digital synchronization replacement circuit B detects the frame synchronization signal 98 added to the horizontal synchronization portion 97 of the scramble signal 3, and supplies the frame synchronization detection signal A, which is a reference signal for frame synchronization, to the phase comparison circuit side. . The frame counter M and the frame synchronization reference signal A are also supplied to the phase comparison circuit A, and the phase comparison is performed between the frame synchronization detection signal A and the frame counter M. If the comparison results in a one phase shift, the comparator circuit supplies a phase control signal to the frame shifter 37 in order to correct the phase between the frame synchronization reference signals. In addition, the frame counter, 37
The output frequency of the horizontal write counter is 2fH (
An input signal (chrysanthemum) of fH (mizuko frequency) is supplied.

Now, the horizontal write counter and the outputs 41 and 42 of the frame counter 37 are both supplied to the synchronizing signal generating circuit 4. The synchronization signal generation circuit 43 generates a synchronization signal,
This is then supplied to the synchronization change circuit 45. The reswitched video signal 46 output from the 2H memory is also guided to the synchronization switching circuit 45. Since the video signal 46 remains between the digital synchronization signals, the synchronization change circuit 45 connects the digital synchronization signal 93 and the synchronization signal 4.
6 is replaced, and the digital NTSC video signal 4
Outputs 7. The video signal 47 is converted into an analog/4G NTSC video signal 49 via a D/A converter, and then interpolated by a primary stage LPF 50 and output as a decoded video signal 51.

The decoded video signal 51 is then supplied to a selection circuit 52 together with the video signal %. This selection circuit 52 determines that the video signal % is not a scrambled signal but a normal N
TSC (if it is No. 1, the decoded video signal 51
is provided for selectively outputting one of the above-mentioned normal NTSC signals in response to an instruction from the mode switching signal &. That is, the mode switching signal & is a control signal for the switching circuit 8 in the selection circuit 52, and when the instruction mode of the switching signal S is scramble mode, the decoded video signal 51 is passed through the switching circuit 8. output, and if the instruction mode is NTSC mode, 1 normal NT
The SC signal is sequentially passed through the delay correction circuit and the switching circuit and then output. The reason why the normal NTSC decoding signal is once passed through a group of delay correction circuits is as follows. In other words, since the 2H memory is used to obtain the decoded video signal 51, the NTS
When the C signal and the decoded video signal 51 are switched and output, 1
A relative delay occurs between the two signals in the horizontal direction. The delay correction circuit amount is provided to correct the above-mentioned relative outer delay in the horizontal direction, and is intended to eliminate instantaneous deviation of the screen at the time of mode switching. .

[Problems with background technology]

The delay correction circuit 5 needs to have an accurate amount of delay, sufficient frequency, and characteristics. This delay correction circuit 5 is an LC
It is composed of passive components such as (), and it becomes very expensive if you try to reduce the fluctuation, obtain accurate delay, and obtain sufficient frequency characteristics.

By the way, in order to improve the S deterioration in the transmission system, as is well known, it is more effective to perform signal processing in the digital signal domain, and it is suitable for use in integrated circuits. Therefore, in the system of FIG.

It is optimal to perform signal processing with an improvement of 87N using the synchronized digital video signal 47 and the amount of D/A conversion circuitry. However, in such a case, since the signal path is different in the NTSC mode, the S cannot be improved.

As shown in FIG. 6, there is still room for improvement in terms of cost and additional functions in the future, as typified by improvements in S.

[Purpose of the invention]

The present invention has been made in view of the above problems.

The object of the present invention is to provide a desk 2 sample device capable of supporting both NTSC and scramble modes without using an analog delay correction circuit.

[Summary of the invention]

The present invention is achieved by switching the J PLL operation using a mode signal! In both 1, NT8C mode, and scramble mode, the signal is digitized, processed, and output.

Specifically, the system is characterized in that in the scramble mode, the PLL method using a digital synchronization signal is used, and in the NT8C mode, the entire system is operated as a PLL method using a burst signal.

〔Effect of the invention〕

As a result, the input signal is digitized and processed regardless of mode, eliminating the need for conventional delay correction circuits and switching circuits. Therefore, the cost of the descrambling device can be reduced. Further, according to the present invention, additional functions such as S improvement can be performed in the digital signal domain through both modes.

It is possible to improve the performance of the descrambling device and increase the possibility of making it multi-functional.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. In the description, only the points that are different from the descrambler shown in FIG. 6 will be explained. FIG. 1 shows a PLL operation circuit 12 used in the descrambling device of the present invention.
0 is shown. The PLL arithmetic circuit 120 performs a PLL operation corresponding to each of scramble mode and NTSC mode.
It includes error calculation circuits 121 and 122, a switching circuit 123 that switches and outputs the outputs of these error calculation circuits 121 and 122 according to the mode, and a loop filter 124.

In addition, the reference clock for performing PLL calculations is
According to the mode switching signal, the system clock 4 can be supplied to the frequency dividing circuit 560 whose division ratio is switched to 115 in the scramble mode and 1/4Vc in the NTSC mode.

Now, the digital synchronous PLL error calculation circuit 121 that operates effectively in the scramble mode has a digital scramble video signal 3. The digital synchronization gate pulse 13 and the frequency divider circuit 560 are supplied with a reference clock 140 ('15 fsc in scramble mode). Upon receiving these signals, the PLL error calculation circuit 121 sets the value of the sampling point of the digital synchronization signal 93 to Q (see FIG. 5(b)), performs the calculations shown below, and outputs an error signal Es.

On the other hand, the burst PLL calculation circuit 122, which operates effectively in the NT8C mode, has a digital scrambled video signal 3.
Burst gate pulse 8 and reference clock 140N
fsc is supplied in T8C mode.

Upon receiving these signals, the PLL error calculation circuit 12
As shown in FIG. 2, as shown in FIG. 2, the value of the sampling point of the burst signal signal of the digital scrambled video signal 3 is set as P, and the calculation shown below is performed to output an error signal FtN.

The error signals Es are calculated as described above.

IN are also supplied to the switching circuit 123. Switching circuit 12
3 selects Es in the scramble mode and EN in the NT8C mode in accordance with the mode switching signal profile, and supplies them as an output signal 125 to the loop filter 124. The loop filter 124 receives the input error signal 125.
is smoothed and output as a phase error signal 15 to the D/A converter circuit 1.
6 (see Figure 6). In this manner, the PLL operation circuit 120 used in the present invention performs PLL operation based on the digital synchronization signal 93 in the scramble mode.
In addition, in NTSC mode, < PL
The L operation is selected and performed.

Furthermore, the descrambling apparatus of the present invention differs from the descrambling apparatus shown in FIG.

As shown in Fig. 3, a switching circuit 30 is provided in front of the 2H memory.
0 is provided, and a new write address 340. This is the point at which the read address 310 is supplied. That is, in the case of the NTSC mode, the switch 301 is turned to the N side in response to an instruction from the mode switching signal &. As a result, the write address outputted by the horizontal write counter % is the same as the read address 310 to the 2H memory.
, 2H memory (writing and reading control are both performed by the same write address 34. Therefore, the NT
In the case of SC mode, the 2H mesorio operates simply as an IH delay line. Oh, this time 2
The synchronization switching circuit 6 to which the output 46 (delayed NTSC video signal) of the H memory is supplied is controlled so as to simply supply the output 46 to the D/A conversion circuit without performing a switching operation. on the other hand.

In the case of scramble mode, switch 301 is 8@
, the write control of the conventional J72H memory is performed by the write address A, and the continuation control is performed by the continuation address 31.

As described above, in the nine scrambling devices shown in FIG.
rIA, with the changes shown in FIG. 3 and the selection circuit 5
By deleting 2, a scrambling device according to the present invention can be obtained.

According to the scrambling device of the present invention, by controlling mode switching of the PLL arithmetic circuit, 2H memory, and synchronization switching circuit,! p, $6 The decoding circuit 100 portion shown in the figure can be shared in both modes. As a result, there is no phase change in the output video signal due to differences in modes, and at the same time signal processing in the digital signal domain (
For example, S/N improvement, etc.) can be performed, and the functionality of the descrambling device is expanded.

Easily expand performance.

1. In order to obtain the desk temple device according to the present invention, it is necessary to add a mode switching control function to the PLL calculation circuit etc. as described above, but considering that this can be handled by IC, the number of IC chips will increase. is completely negligible and does not cause any increase in circuit scale or cost.

Rather, from the same point of view, it can be said that it is extremely beneficial to be able to reduce the number of selection circuits that are conventionally used analog circuits.

[Brief explanation of drawings]

Figure 1 shows the PL used in the descrambling device of the present invention.
FIG. 2 is a diagram of the burst waveform of the video signal, FIG. 3 is a diagram of the configuration of the 2H memory used in the descrambling device of the present invention, and FIG. 4 explains the in-line rotation system. FIG. 5 is a ninth signal waveform diagram illustrating the address detection method in the descrambling device, and FIG. 6 is a configuration diagram of the descrambling device. 2... A/D converter, 3... Digital video signal. 4...System clock, 5...Clock generation circuit. 15... Phase error signal, 16... D/A converter, 1
7... Analog phase error signal, 91... Video signal. 93... Digital synchronization signal, 96... Scramble signal. G...Burst signal, 120...PLL calculation circuit. 121...Digital synchronous PLL error calculation circuit. 122...Burst PLL error calculation circuit. Agent Patent attorney Kensuke Norichika (and 1 other person) Graduation 2 Figure 312] Figure 4 Kaya 51 (.) 24

Claims (1)

[Claims] An A/D converter samples and digitizes a video signal using a system clock, and a digital video signal output from this A/D converter is supplied, and when this digital video signal is an encrypted scramble signal, is a digital decoding circuit that decodes this, a PLL arithmetic circuit located in this digital decoding circuit that detects an error between the phase of the digital video signal and a predetermined phase, and a phase error outputted from this PLL arithmetic circuit. D/A supplied with
In a descrambling device comprising a converter and a clock generation circuit that receives an analog phase error signal output from the D/A converter and controls the phase of the system clock that is the output thereof, the PLL operation circuit is a digital synchronization PL that performs phase error calculation based on a digital synchronization signal that is a reference signal inserted into the scrambled signal.
L error calculation circuit; and a burst PLL error calculation circuit that calculates a phase error based on a burst signal in the video signal, and when the video signal is a scramble signal, the output of the digital synchronous PLL error calculation circuit is A descrambling device that selectively outputs an output of the burst PLL error calculation circuit as a phase error signal when the video signal is not encrypted.